Patent
US 9,214,528METHOD TO FABRICATE SELF-ALIGNED ISOLATION IN GALLIUM NITRIDE DEVICES AND INTEGRATED CIRCUITS
Chunhua Zhou, Jianjun Cao, Alexander Lidow, Robert Beach et al.
US
Copyright © 2026 Matter42. All rights reserved.
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Atlas literature
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US 9,214,528Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 schematically illustrates a top view of a conventional GaN integrated circuit having two adjacent devices each with a corresponding isolation area. …
FIG. 2 schematically illustrates a top view of another conventional GaN integrated circuit having two adjacent devices each with a corresponding isolation …
FIG. 3B illustrates a cross-sectional view of a conventional isolation area formed by implanting ions into active layers. 1 0021]
FIG. 4B illustrates a cross-sectional view of a conventional isolation area formed by ion- implantation with a dedicated mask. [0023 1
FIG. 5 illustrates a flow chart to fabricate self-aligned isolation areas according to an example embodiment of the present invention. [0024]
FIGS. 6A-6G illustrate example process steps according to one embodiment of the present invention. 5 Docket No.: E 0 101.0024/P024 [0025]
FIGS. 7C-7D illustrate a top view and cross-sectional view of an exemplary embodiment of the present invention with a formed isolation area that is …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Application No.: 14/322,641 Docket No.: E 010 1.0024 AMENDMENTS TO THE CLAIMS 1. A method of forming an integrated circuit having at least two transistor devices, the method comprising: forming a buffer layer on a substrate; forming a GaN layer over the buffer layer; forming a barrier layer over the GaN layer; forming a dielectric layer over the barrier layer; forming at least one device contact opening in the dielectric layer for each of the at least two transistor devices and an isolation contact opening in the dielectric layer between the at least two transistor devices; forming a metal layer over the dielectric layer, the device contact openings and the isolation contact opening; forming a photoresist film above each of the device contact openings th itozresistfi etching the metal layer teabn: -e-andthe Sametetavethirc etching a portion o f the ba rri er layer an d the GaN layer to formn '"X'rgo whiere
The method of claim 1, wherein the isolation contact opening is wider than the metal mask window.
The method of claim 1, wherein the metal mask window is wider than the isolation contact opening.
The method of claim 1, where the step of etching the metal layer comprises metal etching using a plasma comprising at least one of a C 1 2, BC l 3, and Ar plasma.
The method of claim 1, where the step of forming the device contact openings and the isolation contact opening in the dielectric layer comprises etching the dielectric layer to expose the barrier layer.
The method of claim 1, further comprising stripping the photoresist film.
The method of claim 1, wherein the device contact openings for each of the at least two transistor devices define respective gate contacts.
The method of claim 1, wherein the device contact openings comprise a pair of device contact openings for each of the at least two transistor devices that define respective drain and source ohmic contacts.
The method of claim 1, wherein the GaN layer is un-doped and comprises a thickness between 0.5 and 10 gm.
The method of claim 1, wherein the barrier layer is un-doped and comprises a thickness between 50A to 300 A.
A method of forming a transistor device, the method comprising: forming a buffer layer on a substrate; forming a GaN layer over the buffer layer; forming a barrier layer over the GaN layer; forming a dielectric layer over the barrier layer; forming at least one device contact opening and an isolation contact opening in the dielectric layer; forming a metal layer over the dielectric layer, the at least one device contact opening and the isolation contact opening; forming a photoresist film above the at least one device contact opening, me h es SVG 14322641.07-27-2015.ICMB₃DJ₀PXXIFW3.CLM.1.svg 0.18 2.54 Black and white etc h ing the meta l layer mr _ "-iA and etching a portion o f the ba rri er layer an d the GaN layer to form aniisolfion region wi e
The method of claim 14, wherein the isolation contact opening is wider than the metal mask window.
The method of claim 14, wherein the metal mask window is wider than the isolation contact opening.
The method of claim 14, wherein the step of forming the at least one device contact opening and the isolation contact opening in the dielectric layer comprises etching the dielectric layer to expose the barrier layer.
The method of claim 14, further comprising stripping the photoresist film.
The method of claim 14, wherein the at least one device contact opening defines a gate contact for the transistor device.
The method of claim 14, wherein the at least one device contact opening comprise a pair of device contact openings that define respective drain and source ohmic contacts for the transistor device.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HFET integrated circuit with self-aligned isolation
Materials described outside the worked examples.
buffer layer
GaN
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,214,528Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 schematically illustrates a top view of a conventional GaN integrated circuit having two adjacent devices each with a corresponding isolation area. …
FIG. 2 schematically illustrates a top view of another conventional GaN integrated circuit having two adjacent devices each with a corresponding isolation …
FIG. 3B illustrates a cross-sectional view of a conventional isolation area formed by implanting ions into active layers. 1 0021]
FIG. 4B illustrates a cross-sectional view of a conventional isolation area formed by ion- implantation with a dedicated mask. [0023 1
FIG. 5 illustrates a flow chart to fabricate self-aligned isolation areas according to an example embodiment of the present invention. [0024]
FIGS. 6A-6G illustrate example process steps according to one embodiment of the present invention. 5 Docket No.: E 0 101.0024/P024 [0025]
FIGS. 7C-7D illustrate a top view and cross-sectional view of an exemplary embodiment of the present invention with a formed isolation area that is …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Application No.: 14/322,641 Docket No.: E 010 1.0024 AMENDMENTS TO THE CLAIMS 1. A method of forming an integrated circuit having at least two transistor devices, the method comprising: forming a buffer layer on a substrate; forming a GaN layer over the buffer layer; forming a barrier layer over the GaN layer; forming a dielectric layer over the barrier layer; forming at least one device contact opening in the dielectric layer for each of the at least two transistor devices and an isolation contact opening in the dielectric layer between the at least two transistor devices; forming a metal layer over the dielectric layer, the device contact openings and the isolation contact opening; forming a photoresist film above each of the device contact openings th itozresistfi etching the metal layer teabn: -e-andthe Sametetavethirc etching a portion o f the ba rri er layer an d the GaN layer to formn '"X'rgo whiere
The method of claim 1, wherein the isolation contact opening is wider than the metal mask window.
The method of claim 1, wherein the metal mask window is wider than the isolation contact opening.
The method of claim 1, where the step of etching the metal layer comprises metal etching using a plasma comprising at least one of a C 1 2, BC l 3, and Ar plasma.
The method of claim 1, where the step of forming the device contact openings and the isolation contact opening in the dielectric layer comprises etching the dielectric layer to expose the barrier layer.
The method of claim 1, further comprising stripping the photoresist film.
The method of claim 1, wherein the device contact openings for each of the at least two transistor devices define respective gate contacts.
The method of claim 1, wherein the device contact openings comprise a pair of device contact openings for each of the at least two transistor devices that define respective drain and source ohmic contacts.
The method of claim 1, wherein the GaN layer is un-doped and comprises a thickness between 0.5 and 10 gm.
The method of claim 1, wherein the barrier layer is un-doped and comprises a thickness between 50A to 300 A.
A method of forming a transistor device, the method comprising: forming a buffer layer on a substrate; forming a GaN layer over the buffer layer; forming a barrier layer over the GaN layer; forming a dielectric layer over the barrier layer; forming at least one device contact opening and an isolation contact opening in the dielectric layer; forming a metal layer over the dielectric layer, the at least one device contact opening and the isolation contact opening; forming a photoresist film above the at least one device contact opening, me h es SVG 14322641.07-27-2015.ICMB₃DJ₀PXXIFW3.CLM.1.svg 0.18 2.54 Black and white etc h ing the meta l layer mr _ "-iA and etching a portion o f the ba rri er layer an d the GaN layer to form aniisolfion region wi e
The method of claim 14, wherein the isolation contact opening is wider than the metal mask window.
The method of claim 14, wherein the metal mask window is wider than the isolation contact opening.
The method of claim 14, wherein the step of forming the at least one device contact opening and the isolation contact opening in the dielectric layer comprises etching the dielectric layer to expose the barrier layer.
The method of claim 14, further comprising stripping the photoresist film.
The method of claim 14, wherein the at least one device contact opening defines a gate contact for the transistor device.
The method of claim 14, wherein the at least one device contact opening comprise a pair of device contact openings that define respective drain and source ohmic contacts for the transistor device.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HFET integrated circuit with self-aligned isolation
Materials described outside the worked examples.
buffer layer
GaN
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,214,528Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 schematically illustrates a top view of a conventional GaN integrated circuit having two adjacent devices each with a corresponding isolation area. …
FIG. 2 schematically illustrates a top view of another conventional GaN integrated circuit having two adjacent devices each with a corresponding isolation …
FIG. 3B illustrates a cross-sectional view of a conventional isolation area formed by implanting ions into active layers. 1 0021]
FIG. 4B illustrates a cross-sectional view of a conventional isolation area formed by ion- implantation with a dedicated mask. [0023 1
FIG. 5 illustrates a flow chart to fabricate self-aligned isolation areas according to an example embodiment of the present invention. [0024]
FIGS. 6A-6G illustrate example process steps according to one embodiment of the present invention. 5 Docket No.: E 0 101.0024/P024 [0025]
FIGS. 7C-7D illustrate a top view and cross-sectional view of an exemplary embodiment of the present invention with a formed isolation area that is …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Application No.: 14/322,641 Docket No.: E 010 1.0024 AMENDMENTS TO THE CLAIMS 1. A method of forming an integrated circuit having at least two transistor devices, the method comprising: forming a buffer layer on a substrate; forming a GaN layer over the buffer layer; forming a barrier layer over the GaN layer; forming a dielectric layer over the barrier layer; forming at least one device contact opening in the dielectric layer for each of the at least two transistor devices and an isolation contact opening in the dielectric layer between the at least two transistor devices; forming a metal layer over the dielectric layer, the device contact openings and the isolation contact opening; forming a photoresist film above each of the device contact openings th itozresistfi etching the metal layer teabn: -e-andthe Sametetavethirc etching a portion o f the ba rri er layer an d the GaN layer to formn '"X'rgo whiere
The method of claim 1, wherein the isolation contact opening is wider than the metal mask window.
The method of claim 1, wherein the metal mask window is wider than the isolation contact opening.
The method of claim 1, where the step of etching the metal layer comprises metal etching using a plasma comprising at least one of a C 1 2, BC l 3, and Ar plasma.
The method of claim 1, where the step of forming the device contact openings and the isolation contact opening in the dielectric layer comprises etching the dielectric layer to expose the barrier layer.
The method of claim 1, further comprising stripping the photoresist film.
The method of claim 1, wherein the device contact openings for each of the at least two transistor devices define respective gate contacts.
The method of claim 1, wherein the device contact openings comprise a pair of device contact openings for each of the at least two transistor devices that define respective drain and source ohmic contacts.
The method of claim 1, wherein the GaN layer is un-doped and comprises a thickness between 0.5 and 10 gm.
The method of claim 1, wherein the barrier layer is un-doped and comprises a thickness between 50A to 300 A.
A method of forming a transistor device, the method comprising: forming a buffer layer on a substrate; forming a GaN layer over the buffer layer; forming a barrier layer over the GaN layer; forming a dielectric layer over the barrier layer; forming at least one device contact opening and an isolation contact opening in the dielectric layer; forming a metal layer over the dielectric layer, the at least one device contact opening and the isolation contact opening; forming a photoresist film above the at least one device contact opening, me h es SVG 14322641.07-27-2015.ICMB₃DJ₀PXXIFW3.CLM.1.svg 0.18 2.54 Black and white etc h ing the meta l layer mr _ "-iA and etching a portion o f the ba rri er layer an d the GaN layer to form aniisolfion region wi e
The method of claim 14, wherein the isolation contact opening is wider than the metal mask window.
The method of claim 14, wherein the metal mask window is wider than the isolation contact opening.
The method of claim 14, wherein the step of forming the at least one device contact opening and the isolation contact opening in the dielectric layer comprises etching the dielectric layer to expose the barrier layer.
The method of claim 14, further comprising stripping the photoresist film.
The method of claim 14, wherein the at least one device contact opening defines a gate contact for the transistor device.
The method of claim 14, wherein the at least one device contact opening comprise a pair of device contact openings that define respective drain and source ohmic contacts for the transistor device.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HFET integrated circuit with self-aligned isolation
Materials described outside the worked examples.
buffer layer
GaN
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,214,528Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 schematically illustrates a top view of a conventional GaN integrated circuit having two adjacent devices each with a corresponding isolation area. …
FIG. 2 schematically illustrates a top view of another conventional GaN integrated circuit having two adjacent devices each with a corresponding isolation …
FIG. 3B illustrates a cross-sectional view of a conventional isolation area formed by implanting ions into active layers. 1 0021]
FIG. 4B illustrates a cross-sectional view of a conventional isolation area formed by ion- implantation with a dedicated mask. [0023 1
FIG. 5 illustrates a flow chart to fabricate self-aligned isolation areas according to an example embodiment of the present invention. [0024]
FIGS. 6A-6G illustrate example process steps according to one embodiment of the present invention. 5 Docket No.: E 0 101.0024/P024 [0025]
FIGS. 7C-7D illustrate a top view and cross-sectional view of an exemplary embodiment of the present invention with a formed isolation area that is …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Application No.: 14/322,641 Docket No.: E 010 1.0024 AMENDMENTS TO THE CLAIMS 1. A method of forming an integrated circuit having at least two transistor devices, the method comprising: forming a buffer layer on a substrate; forming a GaN layer over the buffer layer; forming a barrier layer over the GaN layer; forming a dielectric layer over the barrier layer; forming at least one device contact opening in the dielectric layer for each of the at least two transistor devices and an isolation contact opening in the dielectric layer between the at least two transistor devices; forming a metal layer over the dielectric layer, the device contact openings and the isolation contact opening; forming a photoresist film above each of the device contact openings th itozresistfi etching the metal layer teabn: -e-andthe Sametetavethirc etching a portion o f the ba rri er layer an d the GaN layer to formn '"X'rgo whiere
The method of claim 1, wherein the isolation contact opening is wider than the metal mask window.
The method of claim 1, wherein the metal mask window is wider than the isolation contact opening.
The method of claim 1, where the step of etching the metal layer comprises metal etching using a plasma comprising at least one of a C 1 2, BC l 3, and Ar plasma.
The method of claim 1, where the step of forming the device contact openings and the isolation contact opening in the dielectric layer comprises etching the dielectric layer to expose the barrier layer.
The method of claim 1, further comprising stripping the photoresist film.
The method of claim 1, wherein the device contact openings for each of the at least two transistor devices define respective gate contacts.
The method of claim 1, wherein the device contact openings comprise a pair of device contact openings for each of the at least two transistor devices that define respective drain and source ohmic contacts.
The method of claim 1, wherein the GaN layer is un-doped and comprises a thickness between 0.5 and 10 gm.
The method of claim 1, wherein the barrier layer is un-doped and comprises a thickness between 50A to 300 A.
A method of forming a transistor device, the method comprising: forming a buffer layer on a substrate; forming a GaN layer over the buffer layer; forming a barrier layer over the GaN layer; forming a dielectric layer over the barrier layer; forming at least one device contact opening and an isolation contact opening in the dielectric layer; forming a metal layer over the dielectric layer, the at least one device contact opening and the isolation contact opening; forming a photoresist film above the at least one device contact opening, me h es SVG 14322641.07-27-2015.ICMB₃DJ₀PXXIFW3.CLM.1.svg 0.18 2.54 Black and white etc h ing the meta l layer mr _ "-iA and etching a portion o f the ba rri er layer an d the GaN layer to form aniisolfion region wi e
The method of claim 14, wherein the isolation contact opening is wider than the metal mask window.
The method of claim 14, wherein the metal mask window is wider than the isolation contact opening.
The method of claim 14, wherein the step of forming the at least one device contact opening and the isolation contact opening in the dielectric layer comprises etching the dielectric layer to expose the barrier layer.
The method of claim 14, further comprising stripping the photoresist film.
The method of claim 14, wherein the at least one device contact opening defines a gate contact for the transistor device.
The method of claim 14, wherein the at least one device contact opening comprise a pair of device contact openings that define respective drain and source ohmic contacts for the transistor device.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HFET integrated circuit with self-aligned isolation
Materials described outside the worked examples.
buffer layer
GaN
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
GaN HFET transistor device with self-aligned isolation
AlGaN
dielectric layer
metal layer
GaN HFET transistor device with self-aligned isolation
AlGaN
dielectric layer
metal layer
GaN HFET transistor device with self-aligned isolation
AlGaN
dielectric layer
metal layer
GaN HFET transistor device with self-aligned isolation
AlGaN
dielectric layer
metal layer