Patent
US 12,501,699 B1SEMICONDUCTOR DEVICE WITH VERTICALLY STACKED GAN COMPLEMENTARY FETS
Nadim Chowdhury
E2GAN S.A., Luxembourg (LU)·Dec. 16, 2025·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 12,501,699 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic illustrating a three-dimensional view of a semiconductor device, according to an embodi- ment of the disclosure.
FIG. 2 is a schematic illustrating a cross-section view along an AA' axis of
FIG. 3 is a schematic illustrating a cross-section view along a BB' axis of
FIG. 4 is a schematic illustrating a cross-section view 20 along a CC' axis of
FIG. 5 is a schematic illustrating a cross-section view along a DD' axis of
FIG. 6 is a schematic illustrating a view from the top of the device according to an embodiment of the present disclosure.
FIG. 7A is a schematic illustrating a first side view of the device according to an embodiment of the present disclo- 30 sure.
FIG. 8 is a schematic illustrating an equivalent circuit of 35 the device according to an embodiment of the present disclosure. The provided figures depict one …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: 10 a substrate layer; a buffer layer disposed on the substrate layer; a channel layer disposed on the buffer layer; a barrier layer disposed on the channel layer, the barrier layer forming a two-dimensional electron gas (2DEG) 15 at an interface with the channel layer; a plurality of epitaxial layers disposed on the barrier layer, forming a two-dimensional hole gas (2DHG) at an interface with the barrier layer; at least two source terminals, a first of the at least two source terminals, called first source terminal, being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two source terminals, called second source terminal, being electri-cally connected to the two-dimensional hole gas (2DHG); at least two drain terminals, a first of the at least two drain terminals, called first drain terminal, being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two drain terminals, called 30 second drain terminal, being electrically connected to the two-dimensional hole gas (2DHG); and a gate terminal disposed over a passivation layer of the semiconductor device, the passivation layer being posi-tioned over one of the epitaxial layers, wherein the gate terminal is configured to control elec-trical conduction in the two-dimensional electron gas (2DEG) and in the two-dimensional hole gas (2DHG).
The semiconductor device according to claim 1, wherein one of the epitaxial layers comprises unintention-ally doped gallium nitride, UID-GaN.
The semiconductor device according to claim 1, wherein one of the epitaxial layers comprises p-type doped gallium nitride, p-GaN.
The semiconductor device according to claim 1, wherein one of the epitaxial layers comprises p++-doped gallium nitride, p++-GaN.
The semiconductor device according to claim 1, wherein the barrier layer is a III-N barrier layer.
The semiconductor device according to claim 1, wherein the barrier layer comprises aluminum gallium nitride, AlGaN.
The semiconductor device according to claim 1, wherein the first source terminal and the first drain terminal are disposed on a first plane extending substantially along the channel layer, and wherein the second source terminal and the second drain terminal are disposed on a second plane distinct from the first plane and extending substantially along one of the epitaxial layers.
The semiconductor device according to claim 1, wherein the gate terminal is disposed over the passivation layer, the passivation layer being positioned between the gate terminal and one of the epitaxial layers.
The semiconductor device according to claim 1, wherein the first source terminal and the first drain terminal are ohmic to electrons, and wherein the second source terminal and the second drain terminal are ohmic to holes.
The semiconductor device according to claim 1, wherein the gate terminal consists of a single gate terminal, the single gate terminal encapsulating a plurality of fins of the semiconductor device, each fin extending into the chan-nel layer, the plurality of fins including a first set of fins extending into a region of the formed two-dimensional electron gas (2DEG), the plurality of fins further including a second set of fins extending into a region of the formed two-dimensional hole gas (2DHG), the first set of fins and the second set of fins being disposed transversely to each other.
A method of manufacturing a semiconductor device, the method comprising: forming a buffer layer on a substrate; forming a channel layer on the buffer layer; forming a barrier layer on the channel layer, a two-dimensional electron gas (2DEG) being induced at an interface between the channel layer and the barrier layer; forming a plurality of epitaxial layers on the barrier layer, a two-dimensional hole gas (2DHG) being induced at an interface between the barrier layer and at least one of the epitaxial layers; forming a passivation layer over one of the epitaxial layers; 17 18 forming a gate terminal over the passivation layer, the gate terminal being configured to control electrical conduction in both the two-dimensional electron gas (2DEG) and the two-dimensional hole gas (2DHG); forming at least two source terminals, a first of the at least two source terminals, called first source terminal, being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two source terminals, called second source terminal, being electri-cally connected to the two-dimensional hole gas (2DHG); and forming at least two drain terminals, wherein a first of the at least two drain terminals, called first drain terminal, is electrically connected to the two-dimensional electron gas (2DEG), and wherein a 15 second of the at least two drain terminals, called second drain terminal, is electrically connected to the two-dimensional hole gas (2DHG). ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN complementary FET (CMOS) with vertically stacked 2DEG n-FET and 2DHG p-FET
Materials described outside the worked examples.
substrate layer
buffer layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–30 nm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,501,699 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic illustrating a three-dimensional view of a semiconductor device, according to an embodi- ment of the disclosure.
FIG. 2 is a schematic illustrating a cross-section view along an AA' axis of
FIG. 3 is a schematic illustrating a cross-section view along a BB' axis of
FIG. 4 is a schematic illustrating a cross-section view 20 along a CC' axis of
FIG. 5 is a schematic illustrating a cross-section view along a DD' axis of
FIG. 6 is a schematic illustrating a view from the top of the device according to an embodiment of the present disclosure.
FIG. 7A is a schematic illustrating a first side view of the device according to an embodiment of the present disclo- 30 sure.
FIG. 8 is a schematic illustrating an equivalent circuit of 35 the device according to an embodiment of the present disclosure. The provided figures depict one …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: 10 a substrate layer; a buffer layer disposed on the substrate layer; a channel layer disposed on the buffer layer; a barrier layer disposed on the channel layer, the barrier layer forming a two-dimensional electron gas (2DEG) 15 at an interface with the channel layer; a plurality of epitaxial layers disposed on the barrier layer, forming a two-dimensional hole gas (2DHG) at an interface with the barrier layer; at least two source terminals, a first of the at least two source terminals, called first source terminal, being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two source terminals, called second source terminal, being electri-cally connected to the two-dimensional hole gas (2DHG); at least two drain terminals, a first of the at least two drain terminals, called first drain terminal, being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two drain terminals, called 30 second drain terminal, being electrically connected to the two-dimensional hole gas (2DHG); and a gate terminal disposed over a passivation layer of the semiconductor device, the passivation layer being posi-tioned over one of the epitaxial layers, wherein the gate terminal is configured to control elec-trical conduction in the two-dimensional electron gas (2DEG) and in the two-dimensional hole gas (2DHG).
The semiconductor device according to claim 1, wherein one of the epitaxial layers comprises unintention-ally doped gallium nitride, UID-GaN.
The semiconductor device according to claim 1, wherein one of the epitaxial layers comprises p-type doped gallium nitride, p-GaN.
The semiconductor device according to claim 1, wherein one of the epitaxial layers comprises p++-doped gallium nitride, p++-GaN.
The semiconductor device according to claim 1, wherein the barrier layer is a III-N barrier layer.
The semiconductor device according to claim 1, wherein the barrier layer comprises aluminum gallium nitride, AlGaN.
The semiconductor device according to claim 1, wherein the first source terminal and the first drain terminal are disposed on a first plane extending substantially along the channel layer, and wherein the second source terminal and the second drain terminal are disposed on a second plane distinct from the first plane and extending substantially along one of the epitaxial layers.
The semiconductor device according to claim 1, wherein the gate terminal is disposed over the passivation layer, the passivation layer being positioned between the gate terminal and one of the epitaxial layers.
The semiconductor device according to claim 1, wherein the first source terminal and the first drain terminal are ohmic to electrons, and wherein the second source terminal and the second drain terminal are ohmic to holes.
The semiconductor device according to claim 1, wherein the gate terminal consists of a single gate terminal, the single gate terminal encapsulating a plurality of fins of the semiconductor device, each fin extending into the chan-nel layer, the plurality of fins including a first set of fins extending into a region of the formed two-dimensional electron gas (2DEG), the plurality of fins further including a second set of fins extending into a region of the formed two-dimensional hole gas (2DHG), the first set of fins and the second set of fins being disposed transversely to each other.
A method of manufacturing a semiconductor device, the method comprising: forming a buffer layer on a substrate; forming a channel layer on the buffer layer; forming a barrier layer on the channel layer, a two-dimensional electron gas (2DEG) being induced at an interface between the channel layer and the barrier layer; forming a plurality of epitaxial layers on the barrier layer, a two-dimensional hole gas (2DHG) being induced at an interface between the barrier layer and at least one of the epitaxial layers; forming a passivation layer over one of the epitaxial layers; 17 18 forming a gate terminal over the passivation layer, the gate terminal being configured to control electrical conduction in both the two-dimensional electron gas (2DEG) and the two-dimensional hole gas (2DHG); forming at least two source terminals, a first of the at least two source terminals, called first source terminal, being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two source terminals, called second source terminal, being electri-cally connected to the two-dimensional hole gas (2DHG); and forming at least two drain terminals, wherein a first of the at least two drain terminals, called first drain terminal, is electrically connected to the two-dimensional electron gas (2DEG), and wherein a 15 second of the at least two drain terminals, called second drain terminal, is electrically connected to the two-dimensional hole gas (2DHG). ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN complementary FET (CMOS) with vertically stacked 2DEG n-FET and 2DHG p-FET
Materials described outside the worked examples.
substrate layer
buffer layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–30 nm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,501,699 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic illustrating a three-dimensional view of a semiconductor device, according to an embodi- ment of the disclosure.
FIG. 2 is a schematic illustrating a cross-section view along an AA' axis of
FIG. 3 is a schematic illustrating a cross-section view along a BB' axis of
FIG. 4 is a schematic illustrating a cross-section view 20 along a CC' axis of
FIG. 5 is a schematic illustrating a cross-section view along a DD' axis of
FIG. 6 is a schematic illustrating a view from the top of the device according to an embodiment of the present disclosure.
FIG. 7A is a schematic illustrating a first side view of the device according to an embodiment of the present disclo- 30 sure.
FIG. 8 is a schematic illustrating an equivalent circuit of 35 the device according to an embodiment of the present disclosure. The provided figures depict one …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: 10 a substrate layer; a buffer layer disposed on the substrate layer; a channel layer disposed on the buffer layer; a barrier layer disposed on the channel layer, the barrier layer forming a two-dimensional electron gas (2DEG) 15 at an interface with the channel layer; a plurality of epitaxial layers disposed on the barrier layer, forming a two-dimensional hole gas (2DHG) at an interface with the barrier layer; at least two source terminals, a first of the at least two source terminals, called first source terminal, being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two source terminals, called second source terminal, being electri-cally connected to the two-dimensional hole gas (2DHG); at least two drain terminals, a first of the at least two drain terminals, called first drain terminal, being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two drain terminals, called 30 second drain terminal, being electrically connected to the two-dimensional hole gas (2DHG); and a gate terminal disposed over a passivation layer of the semiconductor device, the passivation layer being posi-tioned over one of the epitaxial layers, wherein the gate terminal is configured to control elec-trical conduction in the two-dimensional electron gas (2DEG) and in the two-dimensional hole gas (2DHG).
The semiconductor device according to claim 1, wherein one of the epitaxial layers comprises unintention-ally doped gallium nitride, UID-GaN.
The semiconductor device according to claim 1, wherein one of the epitaxial layers comprises p-type doped gallium nitride, p-GaN.
The semiconductor device according to claim 1, wherein one of the epitaxial layers comprises p++-doped gallium nitride, p++-GaN.
The semiconductor device according to claim 1, wherein the barrier layer is a III-N barrier layer.
The semiconductor device according to claim 1, wherein the barrier layer comprises aluminum gallium nitride, AlGaN.
The semiconductor device according to claim 1, wherein the first source terminal and the first drain terminal are disposed on a first plane extending substantially along the channel layer, and wherein the second source terminal and the second drain terminal are disposed on a second plane distinct from the first plane and extending substantially along one of the epitaxial layers.
The semiconductor device according to claim 1, wherein the gate terminal is disposed over the passivation layer, the passivation layer being positioned between the gate terminal and one of the epitaxial layers.
The semiconductor device according to claim 1, wherein the first source terminal and the first drain terminal are ohmic to electrons, and wherein the second source terminal and the second drain terminal are ohmic to holes.
The semiconductor device according to claim 1, wherein the gate terminal consists of a single gate terminal, the single gate terminal encapsulating a plurality of fins of the semiconductor device, each fin extending into the chan-nel layer, the plurality of fins including a first set of fins extending into a region of the formed two-dimensional electron gas (2DEG), the plurality of fins further including a second set of fins extending into a region of the formed two-dimensional hole gas (2DHG), the first set of fins and the second set of fins being disposed transversely to each other.
A method of manufacturing a semiconductor device, the method comprising: forming a buffer layer on a substrate; forming a channel layer on the buffer layer; forming a barrier layer on the channel layer, a two-dimensional electron gas (2DEG) being induced at an interface between the channel layer and the barrier layer; forming a plurality of epitaxial layers on the barrier layer, a two-dimensional hole gas (2DHG) being induced at an interface between the barrier layer and at least one of the epitaxial layers; forming a passivation layer over one of the epitaxial layers; 17 18 forming a gate terminal over the passivation layer, the gate terminal being configured to control electrical conduction in both the two-dimensional electron gas (2DEG) and the two-dimensional hole gas (2DHG); forming at least two source terminals, a first of the at least two source terminals, called first source terminal, being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two source terminals, called second source terminal, being electri-cally connected to the two-dimensional hole gas (2DHG); and forming at least two drain terminals, wherein a first of the at least two drain terminals, called first drain terminal, is electrically connected to the two-dimensional electron gas (2DEG), and wherein a 15 second of the at least two drain terminals, called second drain terminal, is electrically connected to the two-dimensional hole gas (2DHG). ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN complementary FET (CMOS) with vertically stacked 2DEG n-FET and 2DHG p-FET
Materials described outside the worked examples.
substrate layer
buffer layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–30 nm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,501,699 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic illustrating a three-dimensional view of a semiconductor device, according to an embodi- ment of the disclosure.
FIG. 2 is a schematic illustrating a cross-section view along an AA' axis of
FIG. 3 is a schematic illustrating a cross-section view along a BB' axis of
FIG. 4 is a schematic illustrating a cross-section view 20 along a CC' axis of
FIG. 5 is a schematic illustrating a cross-section view along a DD' axis of
FIG. 6 is a schematic illustrating a view from the top of the device according to an embodiment of the present disclosure.
FIG. 7A is a schematic illustrating a first side view of the device according to an embodiment of the present disclo- 30 sure.
FIG. 8 is a schematic illustrating an equivalent circuit of 35 the device according to an embodiment of the present disclosure. The provided figures depict one …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: 10 a substrate layer; a buffer layer disposed on the substrate layer; a channel layer disposed on the buffer layer; a barrier layer disposed on the channel layer, the barrier layer forming a two-dimensional electron gas (2DEG) 15 at an interface with the channel layer; a plurality of epitaxial layers disposed on the barrier layer, forming a two-dimensional hole gas (2DHG) at an interface with the barrier layer; at least two source terminals, a first of the at least two source terminals, called first source terminal, being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two source terminals, called second source terminal, being electri-cally connected to the two-dimensional hole gas (2DHG); at least two drain terminals, a first of the at least two drain terminals, called first drain terminal, being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two drain terminals, called 30 second drain terminal, being electrically connected to the two-dimensional hole gas (2DHG); and a gate terminal disposed over a passivation layer of the semiconductor device, the passivation layer being posi-tioned over one of the epitaxial layers, wherein the gate terminal is configured to control elec-trical conduction in the two-dimensional electron gas (2DEG) and in the two-dimensional hole gas (2DHG).
The semiconductor device according to claim 1, wherein one of the epitaxial layers comprises unintention-ally doped gallium nitride, UID-GaN.
The semiconductor device according to claim 1, wherein one of the epitaxial layers comprises p-type doped gallium nitride, p-GaN.
The semiconductor device according to claim 1, wherein one of the epitaxial layers comprises p++-doped gallium nitride, p++-GaN.
The semiconductor device according to claim 1, wherein the barrier layer is a III-N barrier layer.
The semiconductor device according to claim 1, wherein the barrier layer comprises aluminum gallium nitride, AlGaN.
The semiconductor device according to claim 1, wherein the first source terminal and the first drain terminal are disposed on a first plane extending substantially along the channel layer, and wherein the second source terminal and the second drain terminal are disposed on a second plane distinct from the first plane and extending substantially along one of the epitaxial layers.
The semiconductor device according to claim 1, wherein the gate terminal is disposed over the passivation layer, the passivation layer being positioned between the gate terminal and one of the epitaxial layers.
The semiconductor device according to claim 1, wherein the first source terminal and the first drain terminal are ohmic to electrons, and wherein the second source terminal and the second drain terminal are ohmic to holes.
The semiconductor device according to claim 1, wherein the gate terminal consists of a single gate terminal, the single gate terminal encapsulating a plurality of fins of the semiconductor device, each fin extending into the chan-nel layer, the plurality of fins including a first set of fins extending into a region of the formed two-dimensional electron gas (2DEG), the plurality of fins further including a second set of fins extending into a region of the formed two-dimensional hole gas (2DHG), the first set of fins and the second set of fins being disposed transversely to each other.
A method of manufacturing a semiconductor device, the method comprising: forming a buffer layer on a substrate; forming a channel layer on the buffer layer; forming a barrier layer on the channel layer, a two-dimensional electron gas (2DEG) being induced at an interface between the channel layer and the barrier layer; forming a plurality of epitaxial layers on the barrier layer, a two-dimensional hole gas (2DHG) being induced at an interface between the barrier layer and at least one of the epitaxial layers; forming a passivation layer over one of the epitaxial layers; 17 18 forming a gate terminal over the passivation layer, the gate terminal being configured to control electrical conduction in both the two-dimensional electron gas (2DEG) and the two-dimensional hole gas (2DHG); forming at least two source terminals, a first of the at least two source terminals, called first source terminal, being electrically connected to the two-dimensional electron gas (2DEG), and a second of the at least two source terminals, called second source terminal, being electri-cally connected to the two-dimensional hole gas (2DHG); and forming at least two drain terminals, wherein a first of the at least two drain terminals, called first drain terminal, is electrically connected to the two-dimensional electron gas (2DEG), and wherein a 15 second of the at least two drain terminals, called second drain terminal, is electrically connected to the two-dimensional hole gas (2DHG). ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN complementary FET (CMOS) with vertically stacked 2DEG n-FET and 2DHG p-FET
Materials described outside the worked examples.
substrate layer
buffer layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–30 nm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
channel layer
unintentionally doped gallium nitride
GaN
p-type doped gallium nitride
p-GaN
p++-doped gallium nitride
p++-GaN
aluminum gallium nitride
AlGaN
channel layer
unintentionally doped gallium nitride
GaN
p-type doped gallium nitride
p-GaN
p++-doped gallium nitride
p++-GaN
aluminum gallium nitride
AlGaN
channel layer
unintentionally doped gallium nitride
GaN
p-type doped gallium nitride
p-GaN
p++-doped gallium nitride
p++-GaN
aluminum gallium nitride
AlGaN
channel layer
unintentionally doped gallium nitride
GaN
p-type doped gallium nitride
p-GaN
p++-doped gallium nitride
p++-GaN
aluminum gallium nitride
AlGaN