Patent
US 11,062,818STACKING STRUCTURE HAVING MATERIAL LAYER ON GRAPHENE LAYER AND METHOD OF FORMING MATERIAL LAYER ON GRAPHENE LAYER
Seong-jun JEONG
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,062,818Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a stacking structure having a material layer formed on a graphene layer according to an example embodiment; [0018]
FIG. 2 is a flow chart illustrating a method of forming a material layer on a graphene layer according to an example embodiment; [0019]
FIGS. 3A through 3D are schematic perspective views illustrating a process of forming a material layer on a graphene layer according to an example embodiment; …
FIGS. 4A and 4B show a molecular structure of diethylzinc as an example of a linear type precursor; and [0021]
FIG. 5 is a cross-sectional view of an electronic device having a material layer formed on a graphene layer according to an example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device comprising; a source electrode; a drain electrode; a channel layer formed between the source electrode and the drain electrode, the channel layer including graphene; an intermediate layer formed on the channel layer, the intermediate la yer being directly in contact with the channel la y er; a gate insulating layer formed on the intermediate layer; and a gate electrode formed on the gate insulating layer; wherein the intermediate layer includes at least one of Ge oxide, Ni oxide, Fe oxide and Sn oxide; [[and]] wherein the gate insulating layer comprises a material having a dielectric constant greater than a dielectric constant of Si, or one of Al oxide, Ti oxide, Hf oxide, W oxide, Ta oxide, Ru oxide, Zr oxide, and Zn oxide s wherein the intermediate la y er act as a seed la y er making the gate insulating la y er have physical stability, and wherein the intermediate la y er is formed on the channel la y er from a linear type precursor, the linear type precursor comprises at least one of dieth y lzin c, (Be(N(SiMe 3 121 2, Co(N(SiEtMe 2 121 2, Fe(N(SiMe 3 121 2, Ge(NtBu 2 1 2, Ge(NtBuSiMe j 2 = Ni(N(SiMe 3)2) 2, and Sn(NtBuSiMe 3) 2. Currently amended
The electronic device of claim 1, wherein the intermediate layer has a thickness in a range of about 0.1 nm to about 5 nm. Previously presented
-4. Canceled
Canceled
-7. Canceled
Canceled
A method of forming an electronic device, the method comprising: forming a source electrode, a drain electrode, a channel layer formed between the source electrode and the drain electrode, the channel layer including graphene; forming an intermediate layer that is a board-shaped thin layer lying on a surface of the channel layer by using a linear type precursor, the intermediate layer including at least one of Ge oxide, Ni oxide, Fe oxide and Sn oxide and being directly in contact with the channel layer; [[and]] forming a gate insulating layer on the intermediate layer by using an ALD method, the gate insulating layer comprising a material having a dielectric constant greater than a dielectric constant of Si, or at least one of Al oxide, Ti oxide, Hf oxide, W oxide, Ta oxide, Ru oxide, Zr oxide, and Zn oxide wherein the intermediate layer act as a seed layer making the gate insulating layer have physical precursor comprises at least one of diethylzin c, Fe(N(SiMe 3 12 1 2, Ge(NtBu 2 1 2, Ge(NtBuSiMe 3) 2. Currently amended
The method of claim 8, wherein the intermediate nm to about 5 nm. Original
- 11. Canceled
Canceled
-14. Canceled
Canceled stability, and wherein the linear type (Be(N(SiMe 3 121 2, Co(N(SiEtMe 2 121 2, 3 j 2, Ni(N(SiMe 3) 2) 2, and Sn(NtBuSiMe layer has a thickness in a range of about 0.1
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor
Materials described outside the worked examples.
graphene
Ge oxide
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
intermediate layer thickness | 0.1–5 nm | Ge oxideNi oxideFe oxide |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,062,818Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a stacking structure having a material layer formed on a graphene layer according to an example embodiment; [0018]
FIG. 2 is a flow chart illustrating a method of forming a material layer on a graphene layer according to an example embodiment; [0019]
FIGS. 3A through 3D are schematic perspective views illustrating a process of forming a material layer on a graphene layer according to an example embodiment; …
FIGS. 4A and 4B show a molecular structure of diethylzinc as an example of a linear type precursor; and [0021]
FIG. 5 is a cross-sectional view of an electronic device having a material layer formed on a graphene layer according to an example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device comprising; a source electrode; a drain electrode; a channel layer formed between the source electrode and the drain electrode, the channel layer including graphene; an intermediate layer formed on the channel layer, the intermediate la yer being directly in contact with the channel la y er; a gate insulating layer formed on the intermediate layer; and a gate electrode formed on the gate insulating layer; wherein the intermediate layer includes at least one of Ge oxide, Ni oxide, Fe oxide and Sn oxide; [[and]] wherein the gate insulating layer comprises a material having a dielectric constant greater than a dielectric constant of Si, or one of Al oxide, Ti oxide, Hf oxide, W oxide, Ta oxide, Ru oxide, Zr oxide, and Zn oxide s wherein the intermediate la y er act as a seed la y er making the gate insulating la y er have physical stability, and wherein the intermediate la y er is formed on the channel la y er from a linear type precursor, the linear type precursor comprises at least one of dieth y lzin c, (Be(N(SiMe 3 121 2, Co(N(SiEtMe 2 121 2, Fe(N(SiMe 3 121 2, Ge(NtBu 2 1 2, Ge(NtBuSiMe j 2 = Ni(N(SiMe 3)2) 2, and Sn(NtBuSiMe 3) 2. Currently amended
The electronic device of claim 1, wherein the intermediate layer has a thickness in a range of about 0.1 nm to about 5 nm. Previously presented
-4. Canceled
Canceled
-7. Canceled
Canceled
A method of forming an electronic device, the method comprising: forming a source electrode, a drain electrode, a channel layer formed between the source electrode and the drain electrode, the channel layer including graphene; forming an intermediate layer that is a board-shaped thin layer lying on a surface of the channel layer by using a linear type precursor, the intermediate layer including at least one of Ge oxide, Ni oxide, Fe oxide and Sn oxide and being directly in contact with the channel layer; [[and]] forming a gate insulating layer on the intermediate layer by using an ALD method, the gate insulating layer comprising a material having a dielectric constant greater than a dielectric constant of Si, or at least one of Al oxide, Ti oxide, Hf oxide, W oxide, Ta oxide, Ru oxide, Zr oxide, and Zn oxide wherein the intermediate layer act as a seed layer making the gate insulating layer have physical precursor comprises at least one of diethylzin c, Fe(N(SiMe 3 12 1 2, Ge(NtBu 2 1 2, Ge(NtBuSiMe 3) 2. Currently amended
The method of claim 8, wherein the intermediate nm to about 5 nm. Original
- 11. Canceled
Canceled
-14. Canceled
Canceled stability, and wherein the linear type (Be(N(SiMe 3 121 2, Co(N(SiEtMe 2 121 2, 3 j 2, Ni(N(SiMe 3) 2) 2, and Sn(NtBuSiMe layer has a thickness in a range of about 0.1
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor
Materials described outside the worked examples.
graphene
Ge oxide
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
intermediate layer thickness | 0.1–5 nm | Ge oxideNi oxideFe oxide |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,062,818Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a stacking structure having a material layer formed on a graphene layer according to an example embodiment; [0018]
FIG. 2 is a flow chart illustrating a method of forming a material layer on a graphene layer according to an example embodiment; [0019]
FIGS. 3A through 3D are schematic perspective views illustrating a process of forming a material layer on a graphene layer according to an example embodiment; …
FIGS. 4A and 4B show a molecular structure of diethylzinc as an example of a linear type precursor; and [0021]
FIG. 5 is a cross-sectional view of an electronic device having a material layer formed on a graphene layer according to an example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device comprising; a source electrode; a drain electrode; a channel layer formed between the source electrode and the drain electrode, the channel layer including graphene; an intermediate layer formed on the channel layer, the intermediate la yer being directly in contact with the channel la y er; a gate insulating layer formed on the intermediate layer; and a gate electrode formed on the gate insulating layer; wherein the intermediate layer includes at least one of Ge oxide, Ni oxide, Fe oxide and Sn oxide; [[and]] wherein the gate insulating layer comprises a material having a dielectric constant greater than a dielectric constant of Si, or one of Al oxide, Ti oxide, Hf oxide, W oxide, Ta oxide, Ru oxide, Zr oxide, and Zn oxide s wherein the intermediate la y er act as a seed la y er making the gate insulating la y er have physical stability, and wherein the intermediate la y er is formed on the channel la y er from a linear type precursor, the linear type precursor comprises at least one of dieth y lzin c, (Be(N(SiMe 3 121 2, Co(N(SiEtMe 2 121 2, Fe(N(SiMe 3 121 2, Ge(NtBu 2 1 2, Ge(NtBuSiMe j 2 = Ni(N(SiMe 3)2) 2, and Sn(NtBuSiMe 3) 2. Currently amended
The electronic device of claim 1, wherein the intermediate layer has a thickness in a range of about 0.1 nm to about 5 nm. Previously presented
-4. Canceled
Canceled
-7. Canceled
Canceled
A method of forming an electronic device, the method comprising: forming a source electrode, a drain electrode, a channel layer formed between the source electrode and the drain electrode, the channel layer including graphene; forming an intermediate layer that is a board-shaped thin layer lying on a surface of the channel layer by using a linear type precursor, the intermediate layer including at least one of Ge oxide, Ni oxide, Fe oxide and Sn oxide and being directly in contact with the channel layer; [[and]] forming a gate insulating layer on the intermediate layer by using an ALD method, the gate insulating layer comprising a material having a dielectric constant greater than a dielectric constant of Si, or at least one of Al oxide, Ti oxide, Hf oxide, W oxide, Ta oxide, Ru oxide, Zr oxide, and Zn oxide wherein the intermediate layer act as a seed layer making the gate insulating layer have physical precursor comprises at least one of diethylzin c, Fe(N(SiMe 3 12 1 2, Ge(NtBu 2 1 2, Ge(NtBuSiMe 3) 2. Currently amended
The method of claim 8, wherein the intermediate nm to about 5 nm. Original
- 11. Canceled
Canceled
-14. Canceled
Canceled stability, and wherein the linear type (Be(N(SiMe 3 121 2, Co(N(SiEtMe 2 121 2, 3 j 2, Ni(N(SiMe 3) 2) 2, and Sn(NtBuSiMe layer has a thickness in a range of about 0.1
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor
Materials described outside the worked examples.
graphene
Ge oxide
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
intermediate layer thickness | 0.1–5 nm | Ge oxideNi oxideFe oxide |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,062,818Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a stacking structure having a material layer formed on a graphene layer according to an example embodiment; [0018]
FIG. 2 is a flow chart illustrating a method of forming a material layer on a graphene layer according to an example embodiment; [0019]
FIGS. 3A through 3D are schematic perspective views illustrating a process of forming a material layer on a graphene layer according to an example embodiment; …
FIGS. 4A and 4B show a molecular structure of diethylzinc as an example of a linear type precursor; and [0021]
FIG. 5 is a cross-sectional view of an electronic device having a material layer formed on a graphene layer according to an example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device comprising; a source electrode; a drain electrode; a channel layer formed between the source electrode and the drain electrode, the channel layer including graphene; an intermediate layer formed on the channel layer, the intermediate la yer being directly in contact with the channel la y er; a gate insulating layer formed on the intermediate layer; and a gate electrode formed on the gate insulating layer; wherein the intermediate layer includes at least one of Ge oxide, Ni oxide, Fe oxide and Sn oxide; [[and]] wherein the gate insulating layer comprises a material having a dielectric constant greater than a dielectric constant of Si, or one of Al oxide, Ti oxide, Hf oxide, W oxide, Ta oxide, Ru oxide, Zr oxide, and Zn oxide s wherein the intermediate la y er act as a seed la y er making the gate insulating la y er have physical stability, and wherein the intermediate la y er is formed on the channel la y er from a linear type precursor, the linear type precursor comprises at least one of dieth y lzin c, (Be(N(SiMe 3 121 2, Co(N(SiEtMe 2 121 2, Fe(N(SiMe 3 121 2, Ge(NtBu 2 1 2, Ge(NtBuSiMe j 2 = Ni(N(SiMe 3)2) 2, and Sn(NtBuSiMe 3) 2. Currently amended
The electronic device of claim 1, wherein the intermediate layer has a thickness in a range of about 0.1 nm to about 5 nm. Previously presented
-4. Canceled
Canceled
-7. Canceled
Canceled
A method of forming an electronic device, the method comprising: forming a source electrode, a drain electrode, a channel layer formed between the source electrode and the drain electrode, the channel layer including graphene; forming an intermediate layer that is a board-shaped thin layer lying on a surface of the channel layer by using a linear type precursor, the intermediate layer including at least one of Ge oxide, Ni oxide, Fe oxide and Sn oxide and being directly in contact with the channel layer; [[and]] forming a gate insulating layer on the intermediate layer by using an ALD method, the gate insulating layer comprising a material having a dielectric constant greater than a dielectric constant of Si, or at least one of Al oxide, Ti oxide, Hf oxide, W oxide, Ta oxide, Ru oxide, Zr oxide, and Zn oxide wherein the intermediate layer act as a seed layer making the gate insulating layer have physical precursor comprises at least one of diethylzin c, Fe(N(SiMe 3 12 1 2, Ge(NtBu 2 1 2, Ge(NtBuSiMe 3) 2. Currently amended
The method of claim 8, wherein the intermediate nm to about 5 nm. Original
- 11. Canceled
Canceled
-14. Canceled
Canceled stability, and wherein the linear type (Be(N(SiMe 3 121 2, Co(N(SiEtMe 2 121 2, 3 j 2, Ni(N(SiMe 3) 2) 2, and Sn(NtBuSiMe layer has a thickness in a range of about 0.1
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor
Materials described outside the worked examples.
graphene
Ge oxide
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
intermediate layer thickness | 0.1–5 nm | Ge oxideNi oxideFe oxide |
Related documents with shared materials, methods, properties, or citations.
Ni oxide
Fe oxide
Sn oxide
Al oxide
Al₂O₃
Ti oxide
Hf oxide
HfO₂
W oxide
Ta oxide
Ru oxide
Zr oxide
ZrO₂
Zn oxide
ZnO
diethylzinc
Zn(C₂H₅)2
Be(N(SiMe₃)2)2
Co(N(SiEtMe₂)2)2
Fe(N(SiMe₃)2)2
Ge(NtBu₂)2
Ge(NtBuSiMe₃)2
Ni(N(SiMe₃)2)2
Sn(NtBuSiMe₃)2
Thickness | 0.1–20 nm | — |
Ni oxide
Fe oxide
Sn oxide
Al oxide
Al₂O₃
Ti oxide
Hf oxide
HfO₂
W oxide
Ta oxide
Ru oxide
Zr oxide
ZrO₂
Zn oxide
ZnO
diethylzinc
Zn(C₂H₅)2
Be(N(SiMe₃)2)2
Co(N(SiEtMe₂)2)2
Fe(N(SiMe₃)2)2
Ge(NtBu₂)2
Ge(NtBuSiMe₃)2
Ni(N(SiMe₃)2)2
Sn(NtBuSiMe₃)2
Thickness | 0.1–20 nm | — |
Ni oxide
Fe oxide
Sn oxide
Al oxide
Al₂O₃
Ti oxide
Hf oxide
HfO₂
W oxide
Ta oxide
Ru oxide
Zr oxide
ZrO₂
Zn oxide
ZnO
diethylzinc
Zn(C₂H₅)2
Be(N(SiMe₃)2)2
Co(N(SiEtMe₂)2)2
Fe(N(SiMe₃)2)2
Ge(NtBu₂)2
Ge(NtBuSiMe₃)2
Ni(N(SiMe₃)2)2
Sn(NtBuSiMe₃)2
Thickness | 0.1–20 nm | — |
Ni oxide
Fe oxide
Sn oxide
Al oxide
Al₂O₃
Ti oxide
Hf oxide
HfO₂
W oxide
Ta oxide
Ru oxide
Zr oxide
ZrO₂
Zn oxide
ZnO
diethylzinc
Zn(C₂H₅)2
Be(N(SiMe₃)2)2
Co(N(SiEtMe₂)2)2
Fe(N(SiMe₃)2)2
Ge(NtBu₂)2
Ge(NtBuSiMe₃)2
Ni(N(SiMe₃)2)2
Sn(NtBuSiMe₃)2
Thickness | 0.1–20 nm | — |