Patent
US 9,257,528GRAPHENE ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME
Hyun-jong CHUNG
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 9,257,528Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view showing a structure of a graphene electronic device according to example embodiments; [0016]
FIG. 2 is a plan view of the graphene electronic device of
FIG. 3 is a plane view of a graphene electronic device according to example embodiments; [0018]
FIGS. 4A through 4E are side views for explaining a method of manufacturing a graphene electronic device, according to example embodiments; and [0019]
FIGS. 5A through 5E are side views for explaining a method of manufacturing a graphene electronic device, according to example embodiments. 3 Atty. Dkt. No. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene electronic device comprising: a graphene channel layer on a substrate, the graphene channel layer consisting of at least one layer of a graphene sheet; a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer; a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, the gate oxide having substantially the same shape as the graphene channel layer between the source electrode and the drain electrode when viewed from a plan view; and a gate electrode on the gate oxide, wherein the graphene channel layer has a channel width of about 1 to about 20 nm, and the graphene electronic device is a field effect transistor.
The graphene electronic device of claim 1, wherein the substrate is a nonconductive substrate.
The graphene electronic device of claim 1, wherein the substrate is a silicon substrate, further comprising: an insulating layer between the silicon substrate and the graphene channel layer.
The graphene electronic device of claim 1, wherein the graphene channel layer comprises a chemical vapor deposition (CVD) graphene. Page 2 Application No.: 14/244,275 Attorney Docket No.: 2557S I -001689-US-DVA
The graphene electronic device of claim 1, wherein the graphene channel layer comprises at least one of a single-layered graphene sheet and a bi-layered graphene sheet.
4-5.. canceled
canceled
A method of fabricating a graphene electronic device, the method comprising: transferring a graphene layer on a substrate; forming a source electrode and a drain electrode on the graphene layer, the source electrode and the drain electrode being spaced apart from each other; forming an insulating layer covering the source electrode, the drain electrode and the graphene layer; forming a photoresist layer on the insulating layer between the source electrode and the drain electrode, the photoresist layer having a channel shape; removing portions of the insulating layer exposed by the photoresist layer; forming a graphene channel layer by removing portions of the graphene layer exposed by the source electrode, the drain electrode, and the photoresist layer; removing the photoresist layer; and forming a gate electrode on the insulating layer.
The method of claim 8, wherein the forming the graphene channel layer comprises using oxygen plasma.
The method of claim 8, wherein the removing the photoresist layer comprises using oxygen plasma.
The method of claim 8, wherein the fo rm ing the graphene channel layer comprises forming the graphene channel layer having a channel width of about 1 to about 20 nm, and wherein the graphene electronic device is a field effect transistor.
The method of claim 8, wherein forming the graphene channel layer comprises forming the graphene channel layer having a channel width of at least 100 nm, and wherein the graphene electronic device is a radio frequency (RF) transistor. Page 3 Application No.: 14/244,275 Attorney Docket No.: 2557S I -001689-US-DVA
The method of claim 8, wherein the graphene layer comprises at least one of a single-layered graphene and a bi-layered graphene.
A graphene electronic device comprising: a graphene channel layer on a substrate, the graphene channel layer consisting of at least one layer of a graphene sheet; a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer; a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, the gate oxide having substantially the same shape as the graphene channel layer between the source electrode and the drain electrode when viewed from a plan view; and a gate electrode on the gate oxide, wherein the graphene channel layer has a channel width of at least 100 nm, and the graphene electronic device is a radio frequency (RF) transistor.
The graphene electronic device of claim 15, substrate.
The graphene electronic device of claim 15, further comprising: an insulating layer between layer.
The graphene electronic device of claim 15, chemical vapor deposition (CVD) graphene.
The graphene electronic device of claim 15, least one of a single-layered graphene sheet and a LISTING *** Page 4 wherein the substrate is a nonconductive wherein the substrate is a silicon substrate, the silicon substrate and the graphene channel wherein the graphene channel layer comprises a wherein the graphene channel layer comprises at bi- layered graphene sheet. *** END CLAIM
Layer stacks claimed or described, ordered top of device to substrate.
graphene field effect transistor (FET)
Materials described outside the worked examples.
graphene
CVD graphene
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene mobility at room temperature | 100000 cm2V-1s-1 | graphene |
Thickness | 1–20 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,257,528Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view showing a structure of a graphene electronic device according to example embodiments; [0016]
FIG. 2 is a plan view of the graphene electronic device of
FIG. 3 is a plane view of a graphene electronic device according to example embodiments; [0018]
FIGS. 4A through 4E are side views for explaining a method of manufacturing a graphene electronic device, according to example embodiments; and [0019]
FIGS. 5A through 5E are side views for explaining a method of manufacturing a graphene electronic device, according to example embodiments. 3 Atty. Dkt. No. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene electronic device comprising: a graphene channel layer on a substrate, the graphene channel layer consisting of at least one layer of a graphene sheet; a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer; a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, the gate oxide having substantially the same shape as the graphene channel layer between the source electrode and the drain electrode when viewed from a plan view; and a gate electrode on the gate oxide, wherein the graphene channel layer has a channel width of about 1 to about 20 nm, and the graphene electronic device is a field effect transistor.
The graphene electronic device of claim 1, wherein the substrate is a nonconductive substrate.
The graphene electronic device of claim 1, wherein the substrate is a silicon substrate, further comprising: an insulating layer between the silicon substrate and the graphene channel layer.
The graphene electronic device of claim 1, wherein the graphene channel layer comprises a chemical vapor deposition (CVD) graphene. Page 2 Application No.: 14/244,275 Attorney Docket No.: 2557S I -001689-US-DVA
The graphene electronic device of claim 1, wherein the graphene channel layer comprises at least one of a single-layered graphene sheet and a bi-layered graphene sheet.
4-5.. canceled
canceled
A method of fabricating a graphene electronic device, the method comprising: transferring a graphene layer on a substrate; forming a source electrode and a drain electrode on the graphene layer, the source electrode and the drain electrode being spaced apart from each other; forming an insulating layer covering the source electrode, the drain electrode and the graphene layer; forming a photoresist layer on the insulating layer between the source electrode and the drain electrode, the photoresist layer having a channel shape; removing portions of the insulating layer exposed by the photoresist layer; forming a graphene channel layer by removing portions of the graphene layer exposed by the source electrode, the drain electrode, and the photoresist layer; removing the photoresist layer; and forming a gate electrode on the insulating layer.
The method of claim 8, wherein the forming the graphene channel layer comprises using oxygen plasma.
The method of claim 8, wherein the removing the photoresist layer comprises using oxygen plasma.
The method of claim 8, wherein the fo rm ing the graphene channel layer comprises forming the graphene channel layer having a channel width of about 1 to about 20 nm, and wherein the graphene electronic device is a field effect transistor.
The method of claim 8, wherein forming the graphene channel layer comprises forming the graphene channel layer having a channel width of at least 100 nm, and wherein the graphene electronic device is a radio frequency (RF) transistor. Page 3 Application No.: 14/244,275 Attorney Docket No.: 2557S I -001689-US-DVA
The method of claim 8, wherein the graphene layer comprises at least one of a single-layered graphene and a bi-layered graphene.
A graphene electronic device comprising: a graphene channel layer on a substrate, the graphene channel layer consisting of at least one layer of a graphene sheet; a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer; a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, the gate oxide having substantially the same shape as the graphene channel layer between the source electrode and the drain electrode when viewed from a plan view; and a gate electrode on the gate oxide, wherein the graphene channel layer has a channel width of at least 100 nm, and the graphene electronic device is a radio frequency (RF) transistor.
The graphene electronic device of claim 15, substrate.
The graphene electronic device of claim 15, further comprising: an insulating layer between layer.
The graphene electronic device of claim 15, chemical vapor deposition (CVD) graphene.
The graphene electronic device of claim 15, least one of a single-layered graphene sheet and a LISTING *** Page 4 wherein the substrate is a nonconductive wherein the substrate is a silicon substrate, the silicon substrate and the graphene channel wherein the graphene channel layer comprises a wherein the graphene channel layer comprises at bi- layered graphene sheet. *** END CLAIM
Layer stacks claimed or described, ordered top of device to substrate.
graphene field effect transistor (FET)
Materials described outside the worked examples.
graphene
CVD graphene
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene mobility at room temperature | 100000 cm2V-1s-1 | graphene |
Thickness | 1–20 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,257,528Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view showing a structure of a graphene electronic device according to example embodiments; [0016]
FIG. 2 is a plan view of the graphene electronic device of
FIG. 3 is a plane view of a graphene electronic device according to example embodiments; [0018]
FIGS. 4A through 4E are side views for explaining a method of manufacturing a graphene electronic device, according to example embodiments; and [0019]
FIGS. 5A through 5E are side views for explaining a method of manufacturing a graphene electronic device, according to example embodiments. 3 Atty. Dkt. No. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene electronic device comprising: a graphene channel layer on a substrate, the graphene channel layer consisting of at least one layer of a graphene sheet; a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer; a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, the gate oxide having substantially the same shape as the graphene channel layer between the source electrode and the drain electrode when viewed from a plan view; and a gate electrode on the gate oxide, wherein the graphene channel layer has a channel width of about 1 to about 20 nm, and the graphene electronic device is a field effect transistor.
The graphene electronic device of claim 1, wherein the substrate is a nonconductive substrate.
The graphene electronic device of claim 1, wherein the substrate is a silicon substrate, further comprising: an insulating layer between the silicon substrate and the graphene channel layer.
The graphene electronic device of claim 1, wherein the graphene channel layer comprises a chemical vapor deposition (CVD) graphene. Page 2 Application No.: 14/244,275 Attorney Docket No.: 2557S I -001689-US-DVA
The graphene electronic device of claim 1, wherein the graphene channel layer comprises at least one of a single-layered graphene sheet and a bi-layered graphene sheet.
4-5.. canceled
canceled
A method of fabricating a graphene electronic device, the method comprising: transferring a graphene layer on a substrate; forming a source electrode and a drain electrode on the graphene layer, the source electrode and the drain electrode being spaced apart from each other; forming an insulating layer covering the source electrode, the drain electrode and the graphene layer; forming a photoresist layer on the insulating layer between the source electrode and the drain electrode, the photoresist layer having a channel shape; removing portions of the insulating layer exposed by the photoresist layer; forming a graphene channel layer by removing portions of the graphene layer exposed by the source electrode, the drain electrode, and the photoresist layer; removing the photoresist layer; and forming a gate electrode on the insulating layer.
The method of claim 8, wherein the forming the graphene channel layer comprises using oxygen plasma.
The method of claim 8, wherein the removing the photoresist layer comprises using oxygen plasma.
The method of claim 8, wherein the fo rm ing the graphene channel layer comprises forming the graphene channel layer having a channel width of about 1 to about 20 nm, and wherein the graphene electronic device is a field effect transistor.
The method of claim 8, wherein forming the graphene channel layer comprises forming the graphene channel layer having a channel width of at least 100 nm, and wherein the graphene electronic device is a radio frequency (RF) transistor. Page 3 Application No.: 14/244,275 Attorney Docket No.: 2557S I -001689-US-DVA
The method of claim 8, wherein the graphene layer comprises at least one of a single-layered graphene and a bi-layered graphene.
A graphene electronic device comprising: a graphene channel layer on a substrate, the graphene channel layer consisting of at least one layer of a graphene sheet; a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer; a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, the gate oxide having substantially the same shape as the graphene channel layer between the source electrode and the drain electrode when viewed from a plan view; and a gate electrode on the gate oxide, wherein the graphene channel layer has a channel width of at least 100 nm, and the graphene electronic device is a radio frequency (RF) transistor.
The graphene electronic device of claim 15, substrate.
The graphene electronic device of claim 15, further comprising: an insulating layer between layer.
The graphene electronic device of claim 15, chemical vapor deposition (CVD) graphene.
The graphene electronic device of claim 15, least one of a single-layered graphene sheet and a LISTING *** Page 4 wherein the substrate is a nonconductive wherein the substrate is a silicon substrate, the silicon substrate and the graphene channel wherein the graphene channel layer comprises a wherein the graphene channel layer comprises at bi- layered graphene sheet. *** END CLAIM
Layer stacks claimed or described, ordered top of device to substrate.
graphene field effect transistor (FET)
Materials described outside the worked examples.
graphene
CVD graphene
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene mobility at room temperature | 100000 cm2V-1s-1 | graphene |
Thickness | 1–20 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,257,528Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view showing a structure of a graphene electronic device according to example embodiments; [0016]
FIG. 2 is a plan view of the graphene electronic device of
FIG. 3 is a plane view of a graphene electronic device according to example embodiments; [0018]
FIGS. 4A through 4E are side views for explaining a method of manufacturing a graphene electronic device, according to example embodiments; and [0019]
FIGS. 5A through 5E are side views for explaining a method of manufacturing a graphene electronic device, according to example embodiments. 3 Atty. Dkt. No. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene electronic device comprising: a graphene channel layer on a substrate, the graphene channel layer consisting of at least one layer of a graphene sheet; a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer; a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, the gate oxide having substantially the same shape as the graphene channel layer between the source electrode and the drain electrode when viewed from a plan view; and a gate electrode on the gate oxide, wherein the graphene channel layer has a channel width of about 1 to about 20 nm, and the graphene electronic device is a field effect transistor.
The graphene electronic device of claim 1, wherein the substrate is a nonconductive substrate.
The graphene electronic device of claim 1, wherein the substrate is a silicon substrate, further comprising: an insulating layer between the silicon substrate and the graphene channel layer.
The graphene electronic device of claim 1, wherein the graphene channel layer comprises a chemical vapor deposition (CVD) graphene. Page 2 Application No.: 14/244,275 Attorney Docket No.: 2557S I -001689-US-DVA
The graphene electronic device of claim 1, wherein the graphene channel layer comprises at least one of a single-layered graphene sheet and a bi-layered graphene sheet.
4-5.. canceled
canceled
A method of fabricating a graphene electronic device, the method comprising: transferring a graphene layer on a substrate; forming a source electrode and a drain electrode on the graphene layer, the source electrode and the drain electrode being spaced apart from each other; forming an insulating layer covering the source electrode, the drain electrode and the graphene layer; forming a photoresist layer on the insulating layer between the source electrode and the drain electrode, the photoresist layer having a channel shape; removing portions of the insulating layer exposed by the photoresist layer; forming a graphene channel layer by removing portions of the graphene layer exposed by the source electrode, the drain electrode, and the photoresist layer; removing the photoresist layer; and forming a gate electrode on the insulating layer.
The method of claim 8, wherein the forming the graphene channel layer comprises using oxygen plasma.
The method of claim 8, wherein the removing the photoresist layer comprises using oxygen plasma.
The method of claim 8, wherein the fo rm ing the graphene channel layer comprises forming the graphene channel layer having a channel width of about 1 to about 20 nm, and wherein the graphene electronic device is a field effect transistor.
The method of claim 8, wherein forming the graphene channel layer comprises forming the graphene channel layer having a channel width of at least 100 nm, and wherein the graphene electronic device is a radio frequency (RF) transistor. Page 3 Application No.: 14/244,275 Attorney Docket No.: 2557S I -001689-US-DVA
The method of claim 8, wherein the graphene layer comprises at least one of a single-layered graphene and a bi-layered graphene.
A graphene electronic device comprising: a graphene channel layer on a substrate, the graphene channel layer consisting of at least one layer of a graphene sheet; a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer; a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, the gate oxide having substantially the same shape as the graphene channel layer between the source electrode and the drain electrode when viewed from a plan view; and a gate electrode on the gate oxide, wherein the graphene channel layer has a channel width of at least 100 nm, and the graphene electronic device is a radio frequency (RF) transistor.
The graphene electronic device of claim 15, substrate.
The graphene electronic device of claim 15, further comprising: an insulating layer between layer.
The graphene electronic device of claim 15, chemical vapor deposition (CVD) graphene.
The graphene electronic device of claim 15, least one of a single-layered graphene sheet and a LISTING *** Page 4 wherein the substrate is a nonconductive wherein the substrate is a silicon substrate, the silicon substrate and the graphene channel wherein the graphene channel layer comprises a wherein the graphene channel layer comprises at bi- layered graphene sheet. *** END CLAIM
Layer stacks claimed or described, ordered top of device to substrate.
graphene field effect transistor (FET)
Materials described outside the worked examples.
graphene
CVD graphene
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene mobility at room temperature | 100000 cm2V-1s-1 | graphene |
Thickness | 1–20 nm |
Related documents with shared materials, methods, properties, or citations.
graphene radio frequency (RF) transistor
Si
insulating layer (silicon oxide)
SiO₂
single-layered graphene sheet
bi-layered graphene sheet
gate oxide
alumina
Al₂O₃
hafnium oxide
HfO₂
| — |
Thickness | 100–300 nm | — |
Thickness | 5–30 nm | — |
Thickness | ≥ 1 nm | — |
graphene radio frequency (RF) transistor
Si
insulating layer (silicon oxide)
SiO₂
single-layered graphene sheet
bi-layered graphene sheet
gate oxide
alumina
Al₂O₃
hafnium oxide
HfO₂
| — |
Thickness | 100–300 nm | — |
Thickness | 5–30 nm | — |
Thickness | ≥ 1 nm | — |
graphene radio frequency (RF) transistor
Si
insulating layer (silicon oxide)
SiO₂
single-layered graphene sheet
bi-layered graphene sheet
gate oxide
alumina
Al₂O₃
hafnium oxide
HfO₂
| — |
Thickness | 100–300 nm | — |
Thickness | 5–30 nm | — |
Thickness | ≥ 1 nm | — |
graphene radio frequency (RF) transistor
Si
insulating layer (silicon oxide)
SiO₂
single-layered graphene sheet
bi-layered graphene sheet
gate oxide
alumina
Al₂O₃
hafnium oxide
HfO₂
| — |
Thickness | 100–300 nm | — |
Thickness | 5–30 nm | — |
Thickness | ≥ 1 nm | — |