Patent
US 8,724,402GRAPHENE-BASED NON-VOLATILE MEMORY
Wenjuan Zhu
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,724,402Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a memory device according to one embodiment of the present disclosure; [0010]
FIG. 2 illustrates a memory device according to an embodiment; [0011]
FIG. 3 illustrates a memory circuit according to one embodiment; [0012]
FIG. 4 illustrates a memory device according to another embodiment; [0013]
FIG. 5 illustrates a memory device according to an embodiment; [0014]
FIG. 6 illustrates a memory circuit according to another embodiment; [0015]
FIGS. 7A and 7B illustrate a memory circuit according to one embodiment; [0016]
FIG. 8 illustrates a memory device according to another embodiment; [0018]
FIG. 9 illustrates a memory circuit according to another embodiment; [0019]
FIG. 10 illustrates a memory device according to another embodiment; [0020]
FIG. 11 illustrates a memory circuit according to another embodiment; [0021]
FIGS. 12A-12C are flowcharts illustrating methods of controlling graphene-based memory according to one embodiment; [0022]
FIG. 13 is a flowchart illustrating a method of controlling graphene-based memory according to another embodiment; [0026]
FIG. 14 illustrates the an insulation layer on a substrate and forming a back gate in the insulation layer; [0028]
FIG. 15 illustrates forming an insulation layer on the back gate and forming a lower graphene layer on the insulation layer; [0029]
FIG. 16 illustrates forming an insulating layer on the lower graphene layer and forming an upper graphene layer; [0030]
FIG. 17 illustrates forming an insulation layer on the upper graphene layer; [0031]
FIG. 18 illustrates forming electrodes in the insulation layers to contact the graphene layers; [0032]
FIG. 19 illustrates forming an opening to expose portions of the graphene layers; [0033]
FIG. 20 illustrates a method of fabricating a memory device according to another embodiment in which the lower graphene layer includes a source portion and a …
FIGS. 21-23 illustrate a method of fabricating a memory device according to another embodiment; [0035]
FIG. 22 illustrates forming electrodes in the insulation layers; [0037]
FIG. 23 illustrates forming an opening to expose portions of the graphene layers; and [0038]
FIG. 24 illustrates a computing system according to an embodiment of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Application Serial No: 13/595,6 14 In Reply to Office Action dated: LISTING OF CLAIMS 1. A method for representing data in a graphene-based memory device comprising: applying a first voltage to a back gate of a graphene-based memory device and a second voltage to a first graphene layer of the graphene-based memory device, the graphene-based memory device comprising: the first graphene layer and a second graphene layer; a first insulation layer located between the first and second graphene layers, the first insulation layer having an opening between the first and second graphene layers; and the back gate located on an opposite side of the second graphene layer from the first insulation layer, the first graphene layer configured to bend into the opening of the first insulation layer to contact the second graphene layer based on a first electrostatic force generated by the applying the first voltage to the back gate.
The method of claim 1, wherein the graphene-based memory device includes a bit line and an inverter connected to the first graphene layer, a read line connected to the second graphene layer, and a word line connected to the back gate, the bit line including an inverter, wherein applying the first voltage to the back gate and the second voltage to the first graphene layer includes applying a high voltage to each of the word line and the bit line.
The method of claim 1, further comprising: applying a third voltage to the second graphene layer and a fourth voltage to the first graphene layer; and detecting a current flowing through at least one of the first and second graphene layers to read a program state of the graphene-based memory device. Attorney Docket No. Y O R₉₂₀₁₂₀₄₆₅U S 3 Page 2 of 7 Application Serial No: 13/595,6 14 In Reply to Office Action dated:
The method of claim 1, further comprising: applying a third voltage to a top gate of the graphene-based memory device and a fourth voltage to the first graphene layer, the top gate located on an opposite side of the first graphene layer from the second graphene layer, the top gate configured to generate a second electrostatic force to bend the first graphene layer away from the second graphene layer based on the applying the third voltage to the top gate.
The method of claim 1, wherein the second graphene layer includes a source portion and a drain portion separated by a slit, the method further comprising: applying a third voltage to the drain portion of the second graphene layer and a fourth voltage to one or more of the first graphene layer or to the source portion of the second graphene layer; and detecting a current flowing through at least one of the first and second graphene layers to read a program state of the graphene-based memory device.
A method for representing data in a graphene-based memory device, comprising: generating an electrostatic force to bend a suspended portion of a first graphene layer into an opening in an insulation layer to contact an exposed portion of a second graphene layer.
The method of claim 9, wherein generating the electrostatic force includes applying a first voltage to a back gate located on an opposite side of the exposed portion of the second graphene layer from the suspended portion of the first graphene layer and applying a second voltage to the first graphene layer.
The method of claim 9, further comprising: Attorney Docket No. Y O R₉₂₀₁₂₀₄₆₅U S 3 Page 4 of 7 Application Serial No: 13/595,6 14 In Reply to Office Action dated: reading a data state represented by the graphene-based memory device by applying a first voltage to the second graphene layer and a second voltage to the first graphene layer and detecting a current in one or both of the first graphene layer and the second graphene layer.
The method of claim 9, wherein the exposed portion of the second graphene layer includes a slit separating a source portion of the second graphene layer from a drain portion of the second graphene layer, and generating the electrostatic force to bend the first graphene layer to contact the exposed portion of the second graphene layer includes bending the first graphene layer to bridge the slit and contact each of the source portion and the drain portion of the second graphene layer.
A method for representing data in a graphene-based memory circuit, comprising: applying a first voltage to a word line of a graphene-based memory circuit, the word line connected to a back gate of a graphene-based memory device, applying a second voltage to a bit line of the graphene-based memory circuit, the bit line connected to a first graphene layer of the graphene-based memory device, the graphene-based memory device comprising: the first graphene layer and a second graphene layer; a first insulation layer located between the first and second graphene layers, the first insulation layer having an opening between the first and second graphene layers; and the back gate located on an opposite side of the second graphene layer from the first insulation layer, the first graphene layer configured to bend into the opening of the first insulation layer to contact the second graphene layer based on a first electrostatic force generated by the applying the first voltage to the word line and the second voltage to the bit line. Attorney Docket No. Y O R₉₂₀₁₂₀₄₆₅U S 3 Page 5 of 7 Application Serial No: 13/595,6 14 In Reply to Office Action dated:
The method of claim 14, wherein bending the first graphene layer to contact the second graphene layer changes a data state represented by the graphene-based memory device from a first data state to a second data state, the method further comprising: changing the data state represented by the graphene-based memory device from the second data state to the first data state by generating an electrostatic force to bend the first graphene layer away from the second graphene layer by applying a third voltage to an erase line connected to a top gate located on an opposite side of the first graphene layer from the second graphene layer.
The method of claim 14, further comprising: reading a data state represented by the graphene-based memory device by applying a third voltage to a read line connected to the second graphene layer and a fourth voltage to the bit line and detecting a current in one or both of the read line and the bit line.
The method of claim 14, wherein the second graphene layer includes a slit separating a source portion of the second graphene layer from a drain portion of the second graphene layer, and bending the first graphene layer to contact the second graphene layer includes bending the first graphene layer to bridge the slit and contact of the second graphene layer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based non-volatile memory device
Materials described outside the worked examples.
first graphene layer
C
insulation layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
opening length in insulation layer | 1–15 | insulation layer |
insulation layer thickness | 3–15 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,724,402Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a memory device according to one embodiment of the present disclosure; [0010]
FIG. 2 illustrates a memory device according to an embodiment; [0011]
FIG. 3 illustrates a memory circuit according to one embodiment; [0012]
FIG. 4 illustrates a memory device according to another embodiment; [0013]
FIG. 5 illustrates a memory device according to an embodiment; [0014]
FIG. 6 illustrates a memory circuit according to another embodiment; [0015]
FIGS. 7A and 7B illustrate a memory circuit according to one embodiment; [0016]
FIG. 8 illustrates a memory device according to another embodiment; [0018]
FIG. 9 illustrates a memory circuit according to another embodiment; [0019]
FIG. 10 illustrates a memory device according to another embodiment; [0020]
FIG. 11 illustrates a memory circuit according to another embodiment; [0021]
FIGS. 12A-12C are flowcharts illustrating methods of controlling graphene-based memory according to one embodiment; [0022]
FIG. 13 is a flowchart illustrating a method of controlling graphene-based memory according to another embodiment; [0026]
FIG. 14 illustrates the an insulation layer on a substrate and forming a back gate in the insulation layer; [0028]
FIG. 15 illustrates forming an insulation layer on the back gate and forming a lower graphene layer on the insulation layer; [0029]
FIG. 16 illustrates forming an insulating layer on the lower graphene layer and forming an upper graphene layer; [0030]
FIG. 17 illustrates forming an insulation layer on the upper graphene layer; [0031]
FIG. 18 illustrates forming electrodes in the insulation layers to contact the graphene layers; [0032]
FIG. 19 illustrates forming an opening to expose portions of the graphene layers; [0033]
FIG. 20 illustrates a method of fabricating a memory device according to another embodiment in which the lower graphene layer includes a source portion and a …
FIGS. 21-23 illustrate a method of fabricating a memory device according to another embodiment; [0035]
FIG. 22 illustrates forming electrodes in the insulation layers; [0037]
FIG. 23 illustrates forming an opening to expose portions of the graphene layers; and [0038]
FIG. 24 illustrates a computing system according to an embodiment of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Application Serial No: 13/595,6 14 In Reply to Office Action dated: LISTING OF CLAIMS 1. A method for representing data in a graphene-based memory device comprising: applying a first voltage to a back gate of a graphene-based memory device and a second voltage to a first graphene layer of the graphene-based memory device, the graphene-based memory device comprising: the first graphene layer and a second graphene layer; a first insulation layer located between the first and second graphene layers, the first insulation layer having an opening between the first and second graphene layers; and the back gate located on an opposite side of the second graphene layer from the first insulation layer, the first graphene layer configured to bend into the opening of the first insulation layer to contact the second graphene layer based on a first electrostatic force generated by the applying the first voltage to the back gate.
The method of claim 1, wherein the graphene-based memory device includes a bit line and an inverter connected to the first graphene layer, a read line connected to the second graphene layer, and a word line connected to the back gate, the bit line including an inverter, wherein applying the first voltage to the back gate and the second voltage to the first graphene layer includes applying a high voltage to each of the word line and the bit line.
The method of claim 1, further comprising: applying a third voltage to the second graphene layer and a fourth voltage to the first graphene layer; and detecting a current flowing through at least one of the first and second graphene layers to read a program state of the graphene-based memory device. Attorney Docket No. Y O R₉₂₀₁₂₀₄₆₅U S 3 Page 2 of 7 Application Serial No: 13/595,6 14 In Reply to Office Action dated:
The method of claim 1, further comprising: applying a third voltage to a top gate of the graphene-based memory device and a fourth voltage to the first graphene layer, the top gate located on an opposite side of the first graphene layer from the second graphene layer, the top gate configured to generate a second electrostatic force to bend the first graphene layer away from the second graphene layer based on the applying the third voltage to the top gate.
The method of claim 1, wherein the second graphene layer includes a source portion and a drain portion separated by a slit, the method further comprising: applying a third voltage to the drain portion of the second graphene layer and a fourth voltage to one or more of the first graphene layer or to the source portion of the second graphene layer; and detecting a current flowing through at least one of the first and second graphene layers to read a program state of the graphene-based memory device.
A method for representing data in a graphene-based memory device, comprising: generating an electrostatic force to bend a suspended portion of a first graphene layer into an opening in an insulation layer to contact an exposed portion of a second graphene layer.
The method of claim 9, wherein generating the electrostatic force includes applying a first voltage to a back gate located on an opposite side of the exposed portion of the second graphene layer from the suspended portion of the first graphene layer and applying a second voltage to the first graphene layer.
The method of claim 9, further comprising: Attorney Docket No. Y O R₉₂₀₁₂₀₄₆₅U S 3 Page 4 of 7 Application Serial No: 13/595,6 14 In Reply to Office Action dated: reading a data state represented by the graphene-based memory device by applying a first voltage to the second graphene layer and a second voltage to the first graphene layer and detecting a current in one or both of the first graphene layer and the second graphene layer.
The method of claim 9, wherein the exposed portion of the second graphene layer includes a slit separating a source portion of the second graphene layer from a drain portion of the second graphene layer, and generating the electrostatic force to bend the first graphene layer to contact the exposed portion of the second graphene layer includes bending the first graphene layer to bridge the slit and contact each of the source portion and the drain portion of the second graphene layer.
A method for representing data in a graphene-based memory circuit, comprising: applying a first voltage to a word line of a graphene-based memory circuit, the word line connected to a back gate of a graphene-based memory device, applying a second voltage to a bit line of the graphene-based memory circuit, the bit line connected to a first graphene layer of the graphene-based memory device, the graphene-based memory device comprising: the first graphene layer and a second graphene layer; a first insulation layer located between the first and second graphene layers, the first insulation layer having an opening between the first and second graphene layers; and the back gate located on an opposite side of the second graphene layer from the first insulation layer, the first graphene layer configured to bend into the opening of the first insulation layer to contact the second graphene layer based on a first electrostatic force generated by the applying the first voltage to the word line and the second voltage to the bit line. Attorney Docket No. Y O R₉₂₀₁₂₀₄₆₅U S 3 Page 5 of 7 Application Serial No: 13/595,6 14 In Reply to Office Action dated:
The method of claim 14, wherein bending the first graphene layer to contact the second graphene layer changes a data state represented by the graphene-based memory device from a first data state to a second data state, the method further comprising: changing the data state represented by the graphene-based memory device from the second data state to the first data state by generating an electrostatic force to bend the first graphene layer away from the second graphene layer by applying a third voltage to an erase line connected to a top gate located on an opposite side of the first graphene layer from the second graphene layer.
The method of claim 14, further comprising: reading a data state represented by the graphene-based memory device by applying a third voltage to a read line connected to the second graphene layer and a fourth voltage to the bit line and detecting a current in one or both of the read line and the bit line.
The method of claim 14, wherein the second graphene layer includes a slit separating a source portion of the second graphene layer from a drain portion of the second graphene layer, and bending the first graphene layer to contact the second graphene layer includes bending the first graphene layer to bridge the slit and contact of the second graphene layer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based non-volatile memory device
Materials described outside the worked examples.
first graphene layer
C
insulation layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
opening length in insulation layer | 1–15 | insulation layer |
insulation layer thickness | 3–15 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,724,402Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a memory device according to one embodiment of the present disclosure; [0010]
FIG. 2 illustrates a memory device according to an embodiment; [0011]
FIG. 3 illustrates a memory circuit according to one embodiment; [0012]
FIG. 4 illustrates a memory device according to another embodiment; [0013]
FIG. 5 illustrates a memory device according to an embodiment; [0014]
FIG. 6 illustrates a memory circuit according to another embodiment; [0015]
FIGS. 7A and 7B illustrate a memory circuit according to one embodiment; [0016]
FIG. 8 illustrates a memory device according to another embodiment; [0018]
FIG. 9 illustrates a memory circuit according to another embodiment; [0019]
FIG. 10 illustrates a memory device according to another embodiment; [0020]
FIG. 11 illustrates a memory circuit according to another embodiment; [0021]
FIGS. 12A-12C are flowcharts illustrating methods of controlling graphene-based memory according to one embodiment; [0022]
FIG. 13 is a flowchart illustrating a method of controlling graphene-based memory according to another embodiment; [0026]
FIG. 14 illustrates the an insulation layer on a substrate and forming a back gate in the insulation layer; [0028]
FIG. 15 illustrates forming an insulation layer on the back gate and forming a lower graphene layer on the insulation layer; [0029]
FIG. 16 illustrates forming an insulating layer on the lower graphene layer and forming an upper graphene layer; [0030]
FIG. 17 illustrates forming an insulation layer on the upper graphene layer; [0031]
FIG. 18 illustrates forming electrodes in the insulation layers to contact the graphene layers; [0032]
FIG. 19 illustrates forming an opening to expose portions of the graphene layers; [0033]
FIG. 20 illustrates a method of fabricating a memory device according to another embodiment in which the lower graphene layer includes a source portion and a …
FIGS. 21-23 illustrate a method of fabricating a memory device according to another embodiment; [0035]
FIG. 22 illustrates forming electrodes in the insulation layers; [0037]
FIG. 23 illustrates forming an opening to expose portions of the graphene layers; and [0038]
FIG. 24 illustrates a computing system according to an embodiment of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Application Serial No: 13/595,6 14 In Reply to Office Action dated: LISTING OF CLAIMS 1. A method for representing data in a graphene-based memory device comprising: applying a first voltage to a back gate of a graphene-based memory device and a second voltage to a first graphene layer of the graphene-based memory device, the graphene-based memory device comprising: the first graphene layer and a second graphene layer; a first insulation layer located between the first and second graphene layers, the first insulation layer having an opening between the first and second graphene layers; and the back gate located on an opposite side of the second graphene layer from the first insulation layer, the first graphene layer configured to bend into the opening of the first insulation layer to contact the second graphene layer based on a first electrostatic force generated by the applying the first voltage to the back gate.
The method of claim 1, wherein the graphene-based memory device includes a bit line and an inverter connected to the first graphene layer, a read line connected to the second graphene layer, and a word line connected to the back gate, the bit line including an inverter, wherein applying the first voltage to the back gate and the second voltage to the first graphene layer includes applying a high voltage to each of the word line and the bit line.
The method of claim 1, further comprising: applying a third voltage to the second graphene layer and a fourth voltage to the first graphene layer; and detecting a current flowing through at least one of the first and second graphene layers to read a program state of the graphene-based memory device. Attorney Docket No. Y O R₉₂₀₁₂₀₄₆₅U S 3 Page 2 of 7 Application Serial No: 13/595,6 14 In Reply to Office Action dated:
The method of claim 1, further comprising: applying a third voltage to a top gate of the graphene-based memory device and a fourth voltage to the first graphene layer, the top gate located on an opposite side of the first graphene layer from the second graphene layer, the top gate configured to generate a second electrostatic force to bend the first graphene layer away from the second graphene layer based on the applying the third voltage to the top gate.
The method of claim 1, wherein the second graphene layer includes a source portion and a drain portion separated by a slit, the method further comprising: applying a third voltage to the drain portion of the second graphene layer and a fourth voltage to one or more of the first graphene layer or to the source portion of the second graphene layer; and detecting a current flowing through at least one of the first and second graphene layers to read a program state of the graphene-based memory device.
A method for representing data in a graphene-based memory device, comprising: generating an electrostatic force to bend a suspended portion of a first graphene layer into an opening in an insulation layer to contact an exposed portion of a second graphene layer.
The method of claim 9, wherein generating the electrostatic force includes applying a first voltage to a back gate located on an opposite side of the exposed portion of the second graphene layer from the suspended portion of the first graphene layer and applying a second voltage to the first graphene layer.
The method of claim 9, further comprising: Attorney Docket No. Y O R₉₂₀₁₂₀₄₆₅U S 3 Page 4 of 7 Application Serial No: 13/595,6 14 In Reply to Office Action dated: reading a data state represented by the graphene-based memory device by applying a first voltage to the second graphene layer and a second voltage to the first graphene layer and detecting a current in one or both of the first graphene layer and the second graphene layer.
The method of claim 9, wherein the exposed portion of the second graphene layer includes a slit separating a source portion of the second graphene layer from a drain portion of the second graphene layer, and generating the electrostatic force to bend the first graphene layer to contact the exposed portion of the second graphene layer includes bending the first graphene layer to bridge the slit and contact each of the source portion and the drain portion of the second graphene layer.
A method for representing data in a graphene-based memory circuit, comprising: applying a first voltage to a word line of a graphene-based memory circuit, the word line connected to a back gate of a graphene-based memory device, applying a second voltage to a bit line of the graphene-based memory circuit, the bit line connected to a first graphene layer of the graphene-based memory device, the graphene-based memory device comprising: the first graphene layer and a second graphene layer; a first insulation layer located between the first and second graphene layers, the first insulation layer having an opening between the first and second graphene layers; and the back gate located on an opposite side of the second graphene layer from the first insulation layer, the first graphene layer configured to bend into the opening of the first insulation layer to contact the second graphene layer based on a first electrostatic force generated by the applying the first voltage to the word line and the second voltage to the bit line. Attorney Docket No. Y O R₉₂₀₁₂₀₄₆₅U S 3 Page 5 of 7 Application Serial No: 13/595,6 14 In Reply to Office Action dated:
The method of claim 14, wherein bending the first graphene layer to contact the second graphene layer changes a data state represented by the graphene-based memory device from a first data state to a second data state, the method further comprising: changing the data state represented by the graphene-based memory device from the second data state to the first data state by generating an electrostatic force to bend the first graphene layer away from the second graphene layer by applying a third voltage to an erase line connected to a top gate located on an opposite side of the first graphene layer from the second graphene layer.
The method of claim 14, further comprising: reading a data state represented by the graphene-based memory device by applying a third voltage to a read line connected to the second graphene layer and a fourth voltage to the bit line and detecting a current in one or both of the read line and the bit line.
The method of claim 14, wherein the second graphene layer includes a slit separating a source portion of the second graphene layer from a drain portion of the second graphene layer, and bending the first graphene layer to contact the second graphene layer includes bending the first graphene layer to bridge the slit and contact of the second graphene layer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based non-volatile memory device
Materials described outside the worked examples.
first graphene layer
C
insulation layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
opening length in insulation layer | 1–15 | insulation layer |
insulation layer thickness | 3–15 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,724,402Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a memory device according to one embodiment of the present disclosure; [0010]
FIG. 2 illustrates a memory device according to an embodiment; [0011]
FIG. 3 illustrates a memory circuit according to one embodiment; [0012]
FIG. 4 illustrates a memory device according to another embodiment; [0013]
FIG. 5 illustrates a memory device according to an embodiment; [0014]
FIG. 6 illustrates a memory circuit according to another embodiment; [0015]
FIGS. 7A and 7B illustrate a memory circuit according to one embodiment; [0016]
FIG. 8 illustrates a memory device according to another embodiment; [0018]
FIG. 9 illustrates a memory circuit according to another embodiment; [0019]
FIG. 10 illustrates a memory device according to another embodiment; [0020]
FIG. 11 illustrates a memory circuit according to another embodiment; [0021]
FIGS. 12A-12C are flowcharts illustrating methods of controlling graphene-based memory according to one embodiment; [0022]
FIG. 13 is a flowchart illustrating a method of controlling graphene-based memory according to another embodiment; [0026]
FIG. 14 illustrates the an insulation layer on a substrate and forming a back gate in the insulation layer; [0028]
FIG. 15 illustrates forming an insulation layer on the back gate and forming a lower graphene layer on the insulation layer; [0029]
FIG. 16 illustrates forming an insulating layer on the lower graphene layer and forming an upper graphene layer; [0030]
FIG. 17 illustrates forming an insulation layer on the upper graphene layer; [0031]
FIG. 18 illustrates forming electrodes in the insulation layers to contact the graphene layers; [0032]
FIG. 19 illustrates forming an opening to expose portions of the graphene layers; [0033]
FIG. 20 illustrates a method of fabricating a memory device according to another embodiment in which the lower graphene layer includes a source portion and a …
FIGS. 21-23 illustrate a method of fabricating a memory device according to another embodiment; [0035]
FIG. 22 illustrates forming electrodes in the insulation layers; [0037]
FIG. 23 illustrates forming an opening to expose portions of the graphene layers; and [0038]
FIG. 24 illustrates a computing system according to an embodiment of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Application Serial No: 13/595,6 14 In Reply to Office Action dated: LISTING OF CLAIMS 1. A method for representing data in a graphene-based memory device comprising: applying a first voltage to a back gate of a graphene-based memory device and a second voltage to a first graphene layer of the graphene-based memory device, the graphene-based memory device comprising: the first graphene layer and a second graphene layer; a first insulation layer located between the first and second graphene layers, the first insulation layer having an opening between the first and second graphene layers; and the back gate located on an opposite side of the second graphene layer from the first insulation layer, the first graphene layer configured to bend into the opening of the first insulation layer to contact the second graphene layer based on a first electrostatic force generated by the applying the first voltage to the back gate.
The method of claim 1, wherein the graphene-based memory device includes a bit line and an inverter connected to the first graphene layer, a read line connected to the second graphene layer, and a word line connected to the back gate, the bit line including an inverter, wherein applying the first voltage to the back gate and the second voltage to the first graphene layer includes applying a high voltage to each of the word line and the bit line.
The method of claim 1, further comprising: applying a third voltage to the second graphene layer and a fourth voltage to the first graphene layer; and detecting a current flowing through at least one of the first and second graphene layers to read a program state of the graphene-based memory device. Attorney Docket No. Y O R₉₂₀₁₂₀₄₆₅U S 3 Page 2 of 7 Application Serial No: 13/595,6 14 In Reply to Office Action dated:
The method of claim 1, further comprising: applying a third voltage to a top gate of the graphene-based memory device and a fourth voltage to the first graphene layer, the top gate located on an opposite side of the first graphene layer from the second graphene layer, the top gate configured to generate a second electrostatic force to bend the first graphene layer away from the second graphene layer based on the applying the third voltage to the top gate.
The method of claim 1, wherein the second graphene layer includes a source portion and a drain portion separated by a slit, the method further comprising: applying a third voltage to the drain portion of the second graphene layer and a fourth voltage to one or more of the first graphene layer or to the source portion of the second graphene layer; and detecting a current flowing through at least one of the first and second graphene layers to read a program state of the graphene-based memory device.
A method for representing data in a graphene-based memory device, comprising: generating an electrostatic force to bend a suspended portion of a first graphene layer into an opening in an insulation layer to contact an exposed portion of a second graphene layer.
The method of claim 9, wherein generating the electrostatic force includes applying a first voltage to a back gate located on an opposite side of the exposed portion of the second graphene layer from the suspended portion of the first graphene layer and applying a second voltage to the first graphene layer.
The method of claim 9, further comprising: Attorney Docket No. Y O R₉₂₀₁₂₀₄₆₅U S 3 Page 4 of 7 Application Serial No: 13/595,6 14 In Reply to Office Action dated: reading a data state represented by the graphene-based memory device by applying a first voltage to the second graphene layer and a second voltage to the first graphene layer and detecting a current in one or both of the first graphene layer and the second graphene layer.
The method of claim 9, wherein the exposed portion of the second graphene layer includes a slit separating a source portion of the second graphene layer from a drain portion of the second graphene layer, and generating the electrostatic force to bend the first graphene layer to contact the exposed portion of the second graphene layer includes bending the first graphene layer to bridge the slit and contact each of the source portion and the drain portion of the second graphene layer.
A method for representing data in a graphene-based memory circuit, comprising: applying a first voltage to a word line of a graphene-based memory circuit, the word line connected to a back gate of a graphene-based memory device, applying a second voltage to a bit line of the graphene-based memory circuit, the bit line connected to a first graphene layer of the graphene-based memory device, the graphene-based memory device comprising: the first graphene layer and a second graphene layer; a first insulation layer located between the first and second graphene layers, the first insulation layer having an opening between the first and second graphene layers; and the back gate located on an opposite side of the second graphene layer from the first insulation layer, the first graphene layer configured to bend into the opening of the first insulation layer to contact the second graphene layer based on a first electrostatic force generated by the applying the first voltage to the word line and the second voltage to the bit line. Attorney Docket No. Y O R₉₂₀₁₂₀₄₆₅U S 3 Page 5 of 7 Application Serial No: 13/595,6 14 In Reply to Office Action dated:
The method of claim 14, wherein bending the first graphene layer to contact the second graphene layer changes a data state represented by the graphene-based memory device from a first data state to a second data state, the method further comprising: changing the data state represented by the graphene-based memory device from the second data state to the first data state by generating an electrostatic force to bend the first graphene layer away from the second graphene layer by applying a third voltage to an erase line connected to a top gate located on an opposite side of the first graphene layer from the second graphene layer.
The method of claim 14, further comprising: reading a data state represented by the graphene-based memory device by applying a third voltage to a read line connected to the second graphene layer and a fourth voltage to the bit line and detecting a current in one or both of the read line and the bit line.
The method of claim 14, wherein the second graphene layer includes a slit separating a source portion of the second graphene layer from a drain portion of the second graphene layer, and bending the first graphene layer to contact the second graphene layer includes bending the first graphene layer to bridge the slit and contact of the second graphene layer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based non-volatile memory device
Materials described outside the worked examples.
first graphene layer
C
insulation layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
opening length in insulation layer | 1–15 | insulation layer |
insulation layer thickness | 3–15 |
Related documents with shared materials, methods, properties, or citations.
back gate
silicon oxide
SiO₂
silicon nitride
Si₃N₄
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
highly doped poly-silicon
first graphene layer thickness in atom-layers | 1–20 | C |
second graphene layer thickness in atom-layers | 1–20 | C |
Thickness | 3–15 nm | — |
Thickness | 5–200 nm | — |
MEMORY DEVICE USING GRAPHENE AS CHARGE-TRAP LAYER AND METHOD OF OPERATING THE SAME
back gate
silicon oxide
SiO₂
silicon nitride
Si₃N₄
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
highly doped poly-silicon
first graphene layer thickness in atom-layers | 1–20 | C |
second graphene layer thickness in atom-layers | 1–20 | C |
Thickness | 3–15 nm | — |
Thickness | 5–200 nm | — |
MEMORY DEVICE USING GRAPHENE AS CHARGE-TRAP LAYER AND METHOD OF OPERATING THE SAME
back gate
silicon oxide
SiO₂
silicon nitride
Si₃N₄
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
highly doped poly-silicon
first graphene layer thickness in atom-layers | 1–20 | C |
second graphene layer thickness in atom-layers | 1–20 | C |
Thickness | 3–15 nm | — |
Thickness | 5–200 nm | — |
MEMORY DEVICE USING GRAPHENE AS CHARGE-TRAP LAYER AND METHOD OF OPERATING THE SAME
back gate
silicon oxide
SiO₂
silicon nitride
Si₃N₄
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
highly doped poly-silicon
first graphene layer thickness in atom-layers | 1–20 | C |
second graphene layer thickness in atom-layers | 1–20 | C |
Thickness | 3–15 nm | — |
Thickness | 5–200 nm | — |
MEMORY DEVICE USING GRAPHENE AS CHARGE-TRAP LAYER AND METHOD OF OPERATING THE SAME