Patent
US 8,785,912GRAPHENE ELECTRONIC DEVICE INCLUDING A PLURALITY OF GRAPHENE CHANNEL LAYERS
Hyun-jong Chung
US
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Patent
Atlas literature
Patent
US 8,785,912Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view showing a structure of a graphene electronic device according to example embodiments; [0013]
FIGS. 2 through 4 are graphs showing simulation results of a graphene electronic device having two graphene channel layers according to example embodiments and …
FIG. 3, a third graph G₃ shows an I-V characteristic curve of a conventional electronic device, and a fourth graph G 4 shows an I-V characteristic curve of a …
FIG. 4, a fifth graph G 5 shows the current gain of a conventional electronic device, and a sixth graph G 6 represents the current gain of a graphene electronic …
FIG. 5 is a schematic cross-sectional view showing a structure of a graphene electronic device according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
LI S TING O F CLAIMS 1. (C urrentl y Amended.) A graphene electronic device comprising: a gate electrode on a substrate; a first gate insulating film on the substio e to coverrg the gate electrode; a plurality of graphene channel la y ers on t he first gate insu l atin g film; a second gate insulating film betwee n th e plurality of the graphene channel layers; andb a source electrode andvdreleeresedire-i connecte d to bata-e edges of each of the p ur ality of the grapheme channel la wyers.; O. T₁₃ -4L.,.:.-.v Z crtt.3fl t OthE "to aunt -.i i 1'~~IQ fl 1lrA t UC)kSift 1-W 13\tS wherein t he plurality of the graphene c h ann e l layers includes a first graphene channel la y er on. the first gate insulating film and a second graphene channel layer on the second gate insulating f ilm, '-usco d ate ingjijog In i tt tiC1i: gt ~tr c cj le. eand each of the first graphene channel layer and the second graphen e channel lay e r has a width in a range of 1 nAn to 20 nm, and wherein the first grapheme cha n nel layer has a l e ngth greater than that of the second graphene cha n nel layer.
(Pre viou sl y Presented) T he graphene electronic device of claim 1, wherein the gate electrode is embedded in the substrate and an upper surface of the Page 2 Application No. 13/2 25, 988 Attorney Docket No. 255 7SI -001 6 58-US g ate electrode contacts the firs t gate ins uIlating f i lm. unknown
(Ciurrentl y Amended) The graphene electronic device of claim 1, wherein the so u rc e electrode acd-drekn-elestude-a--is formed on the first and second graphene channel layers to resperivel-contact beaihe yn edges of cuh of the first and second graphene channel layersan iswlidrcin, ecetocic.s joUY m.y m
The grapherie electronic device of claim 1, wherein the second gate insulating film is formed of a m aterial selected from the group consisting o1 silicon oxide, silicon nitride, hafnium oxide, a n d alu m inu m oxide.
(C ur ren tly Amended) The graphene e l ectronic aluminum oxide. de v ic e of claim 1, wherein the first c h annel layer are se p arate d from each other parallel to each other owi..a.e.th di.ecticog;of the device of claim 9.
, canceled
5. (Previously Presented) The graphene electronic device of claim i, wherein t he second gate insulati n g fil. has a thickness in a range from about 10 nrm to about 200 n m.
(Cancelled). canceled
(Cur rently Amend e d) A graphene electronic de vi ce comprising: an I nsulating layer coverin g a s u bstrate: a pl u rality of graphene channel layers on th e s u bs t rate a source electrode anxElO---ineistFed&- connected to tesredges of each of the plurality o f th e graphene chan n el la y ers: "': C.:,rciY.;;., +:C. h.: 1 (:t'K:h7 te !ZP3a 3 Page 3 Application No. 1 3/225, 988 Atto r ney D ocket No. 255 7S-00 1658-US a first g ate insulating film co v ering the plurali t y of the graphene channel layers between the source electrode an d the drain electrode; a second gate insulating film bet w een t h e pl u rality of the graphene cha n nel layers; and a gate electrode on the first gate insulating film, wherein the p l urality of graphene channel layers includes a first graphene channel layer o n. the second g ate i nsulating fil m and a second gra phene chb.annel layer on the i nsu l ating layer,.ti setda sj is 2l i!?C' 't'...
1 2. (C u rrently Amended) The graphene electronic device of claim 9., w herein t h e source electrode as:'--?.a--e.. ee-3. ms formed on the first and second graphene cha nn el layers t o respeetly-con t act -in;one edges of earn.
1 0. (Can ce lled). canceled
,. canceled
(Previously Pre sented) T he graphene electronic device o f cla i m 9, wherein the second. gate insula ti n g nlm is f or m ed of a material se l ected from the group co n sist i ng of silicon oxide, silic o n n i tride, hafnium oxide, and
(Curre ntly Amended) The gra..phene electronic graphene channel lay e r and the second graphene ja a diregtionve.;cew t)te substae and ver-ealy substrate.
Layer stacks claimed or described, ordered top of device to substrate.
back-gate graphene field-effect transistor with stacked graphene channel layers
Materials described outside the worked examples.
graphene
silicon oxide
SiO₂
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3, a third graph G₃ shows an I-V characteristic curve of a conventional electronic device, and a fourth graph G 4 shows an I-V characteristic curve of a …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
carrier mobility of graphene (wide channel, ~100 nm or above) | 100000 cm2V-1s-1 | graphene |
graphene channel layer width for semiconductor (band gap) characteristic | 1–20 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,785,912Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view showing a structure of a graphene electronic device according to example embodiments; [0013]
FIGS. 2 through 4 are graphs showing simulation results of a graphene electronic device having two graphene channel layers according to example embodiments and …
FIG. 3, a third graph G₃ shows an I-V characteristic curve of a conventional electronic device, and a fourth graph G 4 shows an I-V characteristic curve of a …
FIG. 4, a fifth graph G 5 shows the current gain of a conventional electronic device, and a sixth graph G 6 represents the current gain of a graphene electronic …
FIG. 5 is a schematic cross-sectional view showing a structure of a graphene electronic device according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
LI S TING O F CLAIMS 1. (C urrentl y Amended.) A graphene electronic device comprising: a gate electrode on a substrate; a first gate insulating film on the substio e to coverrg the gate electrode; a plurality of graphene channel la y ers on t he first gate insu l atin g film; a second gate insulating film betwee n th e plurality of the graphene channel layers; andb a source electrode andvdreleeresedire-i connecte d to bata-e edges of each of the p ur ality of the grapheme channel la wyers.; O. T₁₃ -4L.,.:.-.v Z crtt.3fl t OthE "to aunt -.i i 1'~~IQ fl 1lrA t UC)kSift 1-W 13\tS wherein t he plurality of the graphene c h ann e l layers includes a first graphene channel la y er on. the first gate insulating film and a second graphene channel layer on the second gate insulating f ilm, '-usco d ate ingjijog In i tt tiC1i: gt ~tr c cj le. eand each of the first graphene channel layer and the second graphen e channel lay e r has a width in a range of 1 nAn to 20 nm, and wherein the first grapheme cha n nel layer has a l e ngth greater than that of the second graphene cha n nel layer.
(Pre viou sl y Presented) T he graphene electronic device of claim 1, wherein the gate electrode is embedded in the substrate and an upper surface of the Page 2 Application No. 13/2 25, 988 Attorney Docket No. 255 7SI -001 6 58-US g ate electrode contacts the firs t gate ins uIlating f i lm. unknown
(Ciurrentl y Amended) The graphene electronic device of claim 1, wherein the so u rc e electrode acd-drekn-elestude-a--is formed on the first and second graphene channel layers to resperivel-contact beaihe yn edges of cuh of the first and second graphene channel layersan iswlidrcin, ecetocic.s joUY m.y m
The grapherie electronic device of claim 1, wherein the second gate insulating film is formed of a m aterial selected from the group consisting o1 silicon oxide, silicon nitride, hafnium oxide, a n d alu m inu m oxide.
(C ur ren tly Amended) The graphene e l ectronic aluminum oxide. de v ic e of claim 1, wherein the first c h annel layer are se p arate d from each other parallel to each other owi..a.e.th di.ecticog;of the device of claim 9.
, canceled
5. (Previously Presented) The graphene electronic device of claim i, wherein t he second gate insulati n g fil. has a thickness in a range from about 10 nrm to about 200 n m.
(Cancelled). canceled
(Cur rently Amend e d) A graphene electronic de vi ce comprising: an I nsulating layer coverin g a s u bstrate: a pl u rality of graphene channel layers on th e s u bs t rate a source electrode anxElO---ineistFed&- connected to tesredges of each of the plurality o f th e graphene chan n el la y ers: "': C.:,rciY.;;., +:C. h.: 1 (:t'K:h7 te !ZP3a 3 Page 3 Application No. 1 3/225, 988 Atto r ney D ocket No. 255 7S-00 1658-US a first g ate insulating film co v ering the plurali t y of the graphene channel layers between the source electrode an d the drain electrode; a second gate insulating film bet w een t h e pl u rality of the graphene cha n nel layers; and a gate electrode on the first gate insulating film, wherein the p l urality of graphene channel layers includes a first graphene channel layer o n. the second g ate i nsulating fil m and a second gra phene chb.annel layer on the i nsu l ating layer,.ti setda sj is 2l i!?C' 't'...
1 2. (C u rrently Amended) The graphene electronic device of claim 9., w herein t h e source electrode as:'--?.a--e.. ee-3. ms formed on the first and second graphene cha nn el layers t o respeetly-con t act -in;one edges of earn.
1 0. (Can ce lled). canceled
,. canceled
(Previously Pre sented) T he graphene electronic device o f cla i m 9, wherein the second. gate insula ti n g nlm is f or m ed of a material se l ected from the group co n sist i ng of silicon oxide, silic o n n i tride, hafnium oxide, and
(Curre ntly Amended) The gra..phene electronic graphene channel lay e r and the second graphene ja a diregtionve.;cew t)te substae and ver-ealy substrate.
Layer stacks claimed or described, ordered top of device to substrate.
back-gate graphene field-effect transistor with stacked graphene channel layers
Materials described outside the worked examples.
graphene
silicon oxide
SiO₂
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3, a third graph G₃ shows an I-V characteristic curve of a conventional electronic device, and a fourth graph G 4 shows an I-V characteristic curve of a …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
carrier mobility of graphene (wide channel, ~100 nm or above) | 100000 cm2V-1s-1 | graphene |
graphene channel layer width for semiconductor (band gap) characteristic | 1–20 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,785,912Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view showing a structure of a graphene electronic device according to example embodiments; [0013]
FIGS. 2 through 4 are graphs showing simulation results of a graphene electronic device having two graphene channel layers according to example embodiments and …
FIG. 3, a third graph G₃ shows an I-V characteristic curve of a conventional electronic device, and a fourth graph G 4 shows an I-V characteristic curve of a …
FIG. 4, a fifth graph G 5 shows the current gain of a conventional electronic device, and a sixth graph G 6 represents the current gain of a graphene electronic …
FIG. 5 is a schematic cross-sectional view showing a structure of a graphene electronic device according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
LI S TING O F CLAIMS 1. (C urrentl y Amended.) A graphene electronic device comprising: a gate electrode on a substrate; a first gate insulating film on the substio e to coverrg the gate electrode; a plurality of graphene channel la y ers on t he first gate insu l atin g film; a second gate insulating film betwee n th e plurality of the graphene channel layers; andb a source electrode andvdreleeresedire-i connecte d to bata-e edges of each of the p ur ality of the grapheme channel la wyers.; O. T₁₃ -4L.,.:.-.v Z crtt.3fl t OthE "to aunt -.i i 1'~~IQ fl 1lrA t UC)kSift 1-W 13\tS wherein t he plurality of the graphene c h ann e l layers includes a first graphene channel la y er on. the first gate insulating film and a second graphene channel layer on the second gate insulating f ilm, '-usco d ate ingjijog In i tt tiC1i: gt ~tr c cj le. eand each of the first graphene channel layer and the second graphen e channel lay e r has a width in a range of 1 nAn to 20 nm, and wherein the first grapheme cha n nel layer has a l e ngth greater than that of the second graphene cha n nel layer.
(Pre viou sl y Presented) T he graphene electronic device of claim 1, wherein the gate electrode is embedded in the substrate and an upper surface of the Page 2 Application No. 13/2 25, 988 Attorney Docket No. 255 7SI -001 6 58-US g ate electrode contacts the firs t gate ins uIlating f i lm. unknown
(Ciurrentl y Amended) The graphene electronic device of claim 1, wherein the so u rc e electrode acd-drekn-elestude-a--is formed on the first and second graphene channel layers to resperivel-contact beaihe yn edges of cuh of the first and second graphene channel layersan iswlidrcin, ecetocic.s joUY m.y m
The grapherie electronic device of claim 1, wherein the second gate insulating film is formed of a m aterial selected from the group consisting o1 silicon oxide, silicon nitride, hafnium oxide, a n d alu m inu m oxide.
(C ur ren tly Amended) The graphene e l ectronic aluminum oxide. de v ic e of claim 1, wherein the first c h annel layer are se p arate d from each other parallel to each other owi..a.e.th di.ecticog;of the device of claim 9.
, canceled
5. (Previously Presented) The graphene electronic device of claim i, wherein t he second gate insulati n g fil. has a thickness in a range from about 10 nrm to about 200 n m.
(Cancelled). canceled
(Cur rently Amend e d) A graphene electronic de vi ce comprising: an I nsulating layer coverin g a s u bstrate: a pl u rality of graphene channel layers on th e s u bs t rate a source electrode anxElO---ineistFed&- connected to tesredges of each of the plurality o f th e graphene chan n el la y ers: "': C.:,rciY.;;., +:C. h.: 1 (:t'K:h7 te !ZP3a 3 Page 3 Application No. 1 3/225, 988 Atto r ney D ocket No. 255 7S-00 1658-US a first g ate insulating film co v ering the plurali t y of the graphene channel layers between the source electrode an d the drain electrode; a second gate insulating film bet w een t h e pl u rality of the graphene cha n nel layers; and a gate electrode on the first gate insulating film, wherein the p l urality of graphene channel layers includes a first graphene channel layer o n. the second g ate i nsulating fil m and a second gra phene chb.annel layer on the i nsu l ating layer,.ti setda sj is 2l i!?C' 't'...
1 2. (C u rrently Amended) The graphene electronic device of claim 9., w herein t h e source electrode as:'--?.a--e.. ee-3. ms formed on the first and second graphene cha nn el layers t o respeetly-con t act -in;one edges of earn.
1 0. (Can ce lled). canceled
,. canceled
(Previously Pre sented) T he graphene electronic device o f cla i m 9, wherein the second. gate insula ti n g nlm is f or m ed of a material se l ected from the group co n sist i ng of silicon oxide, silic o n n i tride, hafnium oxide, and
(Curre ntly Amended) The gra..phene electronic graphene channel lay e r and the second graphene ja a diregtionve.;cew t)te substae and ver-ealy substrate.
Layer stacks claimed or described, ordered top of device to substrate.
back-gate graphene field-effect transistor with stacked graphene channel layers
Materials described outside the worked examples.
graphene
silicon oxide
SiO₂
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3, a third graph G₃ shows an I-V characteristic curve of a conventional electronic device, and a fourth graph G 4 shows an I-V characteristic curve of a …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
carrier mobility of graphene (wide channel, ~100 nm or above) | 100000 cm2V-1s-1 | graphene |
graphene channel layer width for semiconductor (band gap) characteristic | 1–20 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,785,912Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view showing a structure of a graphene electronic device according to example embodiments; [0013]
FIGS. 2 through 4 are graphs showing simulation results of a graphene electronic device having two graphene channel layers according to example embodiments and …
FIG. 3, a third graph G₃ shows an I-V characteristic curve of a conventional electronic device, and a fourth graph G 4 shows an I-V characteristic curve of a …
FIG. 4, a fifth graph G 5 shows the current gain of a conventional electronic device, and a sixth graph G 6 represents the current gain of a graphene electronic …
FIG. 5 is a schematic cross-sectional view showing a structure of a graphene electronic device according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
LI S TING O F CLAIMS 1. (C urrentl y Amended.) A graphene electronic device comprising: a gate electrode on a substrate; a first gate insulating film on the substio e to coverrg the gate electrode; a plurality of graphene channel la y ers on t he first gate insu l atin g film; a second gate insulating film betwee n th e plurality of the graphene channel layers; andb a source electrode andvdreleeresedire-i connecte d to bata-e edges of each of the p ur ality of the grapheme channel la wyers.; O. T₁₃ -4L.,.:.-.v Z crtt.3fl t OthE "to aunt -.i i 1'~~IQ fl 1lrA t UC)kSift 1-W 13\tS wherein t he plurality of the graphene c h ann e l layers includes a first graphene channel la y er on. the first gate insulating film and a second graphene channel layer on the second gate insulating f ilm, '-usco d ate ingjijog In i tt tiC1i: gt ~tr c cj le. eand each of the first graphene channel layer and the second graphen e channel lay e r has a width in a range of 1 nAn to 20 nm, and wherein the first grapheme cha n nel layer has a l e ngth greater than that of the second graphene cha n nel layer.
(Pre viou sl y Presented) T he graphene electronic device of claim 1, wherein the gate electrode is embedded in the substrate and an upper surface of the Page 2 Application No. 13/2 25, 988 Attorney Docket No. 255 7SI -001 6 58-US g ate electrode contacts the firs t gate ins uIlating f i lm. unknown
(Ciurrentl y Amended) The graphene electronic device of claim 1, wherein the so u rc e electrode acd-drekn-elestude-a--is formed on the first and second graphene channel layers to resperivel-contact beaihe yn edges of cuh of the first and second graphene channel layersan iswlidrcin, ecetocic.s joUY m.y m
The grapherie electronic device of claim 1, wherein the second gate insulating film is formed of a m aterial selected from the group consisting o1 silicon oxide, silicon nitride, hafnium oxide, a n d alu m inu m oxide.
(C ur ren tly Amended) The graphene e l ectronic aluminum oxide. de v ic e of claim 1, wherein the first c h annel layer are se p arate d from each other parallel to each other owi..a.e.th di.ecticog;of the device of claim 9.
, canceled
5. (Previously Presented) The graphene electronic device of claim i, wherein t he second gate insulati n g fil. has a thickness in a range from about 10 nrm to about 200 n m.
(Cancelled). canceled
(Cur rently Amend e d) A graphene electronic de vi ce comprising: an I nsulating layer coverin g a s u bstrate: a pl u rality of graphene channel layers on th e s u bs t rate a source electrode anxElO---ineistFed&- connected to tesredges of each of the plurality o f th e graphene chan n el la y ers: "': C.:,rciY.;;., +:C. h.: 1 (:t'K:h7 te !ZP3a 3 Page 3 Application No. 1 3/225, 988 Atto r ney D ocket No. 255 7S-00 1658-US a first g ate insulating film co v ering the plurali t y of the graphene channel layers between the source electrode an d the drain electrode; a second gate insulating film bet w een t h e pl u rality of the graphene cha n nel layers; and a gate electrode on the first gate insulating film, wherein the p l urality of graphene channel layers includes a first graphene channel layer o n. the second g ate i nsulating fil m and a second gra phene chb.annel layer on the i nsu l ating layer,.ti setda sj is 2l i!?C' 't'...
1 2. (C u rrently Amended) The graphene electronic device of claim 9., w herein t h e source electrode as:'--?.a--e.. ee-3. ms formed on the first and second graphene cha nn el layers t o respeetly-con t act -in;one edges of earn.
1 0. (Can ce lled). canceled
,. canceled
(Previously Pre sented) T he graphene electronic device o f cla i m 9, wherein the second. gate insula ti n g nlm is f or m ed of a material se l ected from the group co n sist i ng of silicon oxide, silic o n n i tride, hafnium oxide, and
(Curre ntly Amended) The gra..phene electronic graphene channel lay e r and the second graphene ja a diregtionve.;cew t)te substae and ver-ealy substrate.
Layer stacks claimed or described, ordered top of device to substrate.
back-gate graphene field-effect transistor with stacked graphene channel layers
Materials described outside the worked examples.
graphene
silicon oxide
SiO₂
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3, a third graph G₃ shows an I-V characteristic curve of a conventional electronic device, and a fourth graph G 4 shows an I-V characteristic curve of a …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
carrier mobility of graphene (wide channel, ~100 nm or above) | 100000 cm2V-1s-1 | graphene |
graphene channel layer width for semiconductor (band gap) characteristic | 1–20 nm |
Related documents with shared materials, methods, properties, or citations.
top-gate graphene field-effect transistor with stacked graphene channel layers
silicon nitride
Si₃N₄
hafnium oxide
HfO₂
aluminum oxide
Al₂O₃
aluminum
Al
Thickness | 10–200 nm | — |
top-gate graphene field-effect transistor with stacked graphene channel layers
silicon nitride
Si₃N₄
hafnium oxide
HfO₂
aluminum oxide
Al₂O₃
aluminum
Al
Thickness | 10–200 nm | — |
top-gate graphene field-effect transistor with stacked graphene channel layers
silicon nitride
Si₃N₄
hafnium oxide
HfO₂
aluminum oxide
Al₂O₃
aluminum
Al
Thickness | 10–200 nm | — |
top-gate graphene field-effect transistor with stacked graphene channel layers
silicon nitride
Si₃N₄
hafnium oxide
HfO₂
aluminum oxide
Al₂O₃
aluminum
Al
Thickness | 10–200 nm | — |