Patent
US 8,803,132SELF-ALIGNED DOUBLE-GATE GRAPHENE TRANSISTOR
Damon B. Farmer
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,803,132Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates an initial production stage of an exemplary graphene field effect transistor of the present invention in which a graphene sheet is placed on a substrate;
Figure 2 shows a first contact and a second contact formed on a substrate in a second production stage of the exemplary graphene field effect transistor;
Figure 3 illustrates a substrate etching stage;
Figure 4 illustrates a coating stage in which a spacer material is deposited;
Figure 5 shows a high-k gate dielectric deposition stage;
Figure 6 illustrates a conductive gate deposition stage for building a dual gate transistor structure;
Figure 7 shows an exemplary graphene field-effect transistor made using the exemplary methods disclosed herein;
Figure 8 shows an alternative embodiment of a graphene field-effect transistor made using the exemplary methods disclosed herein;
Figure 9 shows a top view of a graphene sheet having exemplary slots for allowing molecules to pass through the graphene sheet; and
Figure 10 shows a flowchart illustrating an exemplary method of producing the exemplary graphene field effect transistor disclosed herein.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconducting device, comprising: a graphene sheet formed on a substrate; a first contact coupled to the graphene sheet and a second contact coupled to the graphene sheet and separated from the first contact by a gap; at least one slot formed in the graphene sheet having a width that allows an etchant to pass through the graphene sheet; and a recess formed in the substrate beneath the graphene sheet via etchant passing through the graphene sheet.
(Cu rr ently Amended) The semiconducting device of claim 1, f-w the * t wherein the graphene sheet forms a graphene bridge th at spans the gap between the first contact and the second contact.
The semiconducting device of claim 1, wherein the first contact and the second contact provide a self-aligned gate structure of the semiconducting device.
The semiconducting device of claim 1, wherein the recess further comprises an anisotropically etched recess.
A transistor, comprising: a graphene sheet disposed directly on a substrate; two ene or more contacts formed on the graphene sheet to define a gap between the t wo ene or more contacts;-and at least one slot in the graphene sheet having a width that allows an etchant to pass through the graphene sheet in the gap; and a gate material in the gap defined by the one or more contacts, wherein the gate material fills a recess in the gap.
(Cu rr ently Amended) The transistor of claim 9, wherein the graphene sheet forms further-cmprising a graphene bridge spanning the gap between the one or more contacts.
The transistor of claim 9, wherein the one or more contacts provide a self-aligned gate structure of the transistor.
A self-aligned graphene transistor, comprising: a graphene sheet disposed on a substrate of the graphene transistor; a source contact on the substrate over the graphene sheet; a drain contact on the substrate over the graphene sheet, wherein the drain contact is separated from the source contact by a gap; at least one slot in the graphene sheet having a width that allows an etchant to pass through the graphene sheet; and a gate region in the gap that includes a recess formed by a passing the etchant through the graphene sheet to remove a portion of the substrate in the gap.
(Cu rr ently Amended) The self-aligned graphene transistor of claim 16, wherein the graphene sheet forms further-comprisng a graphene bridge that spans the gap between the source contact and the drain contact.
The self-aligned graphene transistor of claim anisotropic etching of the substrate in the gap. of the graphene bridge between the graphene 16, wherein the gate region is defined by YOR₉₂₀₁₂₀₈₂₃US₂ 4
Layer stacks claimed or described, ordered top of device to substrate.
semiconducting device with graphene bridge and self-aligned gate
transistor with graphene bridge and dual gate
Materials described outside the worked examples.
graphene sheet
substrate
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 illustrates an initial production stage of an exemplary graphene field effect transistor of the present invention in which a graphene sheet is placed on a substrate;
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,803,132Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates an initial production stage of an exemplary graphene field effect transistor of the present invention in which a graphene sheet is placed on a substrate;
Figure 2 shows a first contact and a second contact formed on a substrate in a second production stage of the exemplary graphene field effect transistor;
Figure 3 illustrates a substrate etching stage;
Figure 4 illustrates a coating stage in which a spacer material is deposited;
Figure 5 shows a high-k gate dielectric deposition stage;
Figure 6 illustrates a conductive gate deposition stage for building a dual gate transistor structure;
Figure 7 shows an exemplary graphene field-effect transistor made using the exemplary methods disclosed herein;
Figure 8 shows an alternative embodiment of a graphene field-effect transistor made using the exemplary methods disclosed herein;
Figure 9 shows a top view of a graphene sheet having exemplary slots for allowing molecules to pass through the graphene sheet; and
Figure 10 shows a flowchart illustrating an exemplary method of producing the exemplary graphene field effect transistor disclosed herein.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconducting device, comprising: a graphene sheet formed on a substrate; a first contact coupled to the graphene sheet and a second contact coupled to the graphene sheet and separated from the first contact by a gap; at least one slot formed in the graphene sheet having a width that allows an etchant to pass through the graphene sheet; and a recess formed in the substrate beneath the graphene sheet via etchant passing through the graphene sheet.
(Cu rr ently Amended) The semiconducting device of claim 1, f-w the * t wherein the graphene sheet forms a graphene bridge th at spans the gap between the first contact and the second contact.
The semiconducting device of claim 1, wherein the first contact and the second contact provide a self-aligned gate structure of the semiconducting device.
The semiconducting device of claim 1, wherein the recess further comprises an anisotropically etched recess.
A transistor, comprising: a graphene sheet disposed directly on a substrate; two ene or more contacts formed on the graphene sheet to define a gap between the t wo ene or more contacts;-and at least one slot in the graphene sheet having a width that allows an etchant to pass through the graphene sheet in the gap; and a gate material in the gap defined by the one or more contacts, wherein the gate material fills a recess in the gap.
(Cu rr ently Amended) The transistor of claim 9, wherein the graphene sheet forms further-cmprising a graphene bridge spanning the gap between the one or more contacts.
The transistor of claim 9, wherein the one or more contacts provide a self-aligned gate structure of the transistor.
A self-aligned graphene transistor, comprising: a graphene sheet disposed on a substrate of the graphene transistor; a source contact on the substrate over the graphene sheet; a drain contact on the substrate over the graphene sheet, wherein the drain contact is separated from the source contact by a gap; at least one slot in the graphene sheet having a width that allows an etchant to pass through the graphene sheet; and a gate region in the gap that includes a recess formed by a passing the etchant through the graphene sheet to remove a portion of the substrate in the gap.
(Cu rr ently Amended) The self-aligned graphene transistor of claim 16, wherein the graphene sheet forms further-comprisng a graphene bridge that spans the gap between the source contact and the drain contact.
The self-aligned graphene transistor of claim anisotropic etching of the substrate in the gap. of the graphene bridge between the graphene 16, wherein the gate region is defined by YOR₉₂₀₁₂₀₈₂₃US₂ 4
Layer stacks claimed or described, ordered top of device to substrate.
semiconducting device with graphene bridge and self-aligned gate
transistor with graphene bridge and dual gate
Materials described outside the worked examples.
graphene sheet
substrate
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 illustrates an initial production stage of an exemplary graphene field effect transistor of the present invention in which a graphene sheet is placed on a substrate;
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,803,132Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates an initial production stage of an exemplary graphene field effect transistor of the present invention in which a graphene sheet is placed on a substrate;
Figure 2 shows a first contact and a second contact formed on a substrate in a second production stage of the exemplary graphene field effect transistor;
Figure 3 illustrates a substrate etching stage;
Figure 4 illustrates a coating stage in which a spacer material is deposited;
Figure 5 shows a high-k gate dielectric deposition stage;
Figure 6 illustrates a conductive gate deposition stage for building a dual gate transistor structure;
Figure 7 shows an exemplary graphene field-effect transistor made using the exemplary methods disclosed herein;
Figure 8 shows an alternative embodiment of a graphene field-effect transistor made using the exemplary methods disclosed herein;
Figure 9 shows a top view of a graphene sheet having exemplary slots for allowing molecules to pass through the graphene sheet; and
Figure 10 shows a flowchart illustrating an exemplary method of producing the exemplary graphene field effect transistor disclosed herein.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconducting device, comprising: a graphene sheet formed on a substrate; a first contact coupled to the graphene sheet and a second contact coupled to the graphene sheet and separated from the first contact by a gap; at least one slot formed in the graphene sheet having a width that allows an etchant to pass through the graphene sheet; and a recess formed in the substrate beneath the graphene sheet via etchant passing through the graphene sheet.
(Cu rr ently Amended) The semiconducting device of claim 1, f-w the * t wherein the graphene sheet forms a graphene bridge th at spans the gap between the first contact and the second contact.
The semiconducting device of claim 1, wherein the first contact and the second contact provide a self-aligned gate structure of the semiconducting device.
The semiconducting device of claim 1, wherein the recess further comprises an anisotropically etched recess.
A transistor, comprising: a graphene sheet disposed directly on a substrate; two ene or more contacts formed on the graphene sheet to define a gap between the t wo ene or more contacts;-and at least one slot in the graphene sheet having a width that allows an etchant to pass through the graphene sheet in the gap; and a gate material in the gap defined by the one or more contacts, wherein the gate material fills a recess in the gap.
(Cu rr ently Amended) The transistor of claim 9, wherein the graphene sheet forms further-cmprising a graphene bridge spanning the gap between the one or more contacts.
The transistor of claim 9, wherein the one or more contacts provide a self-aligned gate structure of the transistor.
A self-aligned graphene transistor, comprising: a graphene sheet disposed on a substrate of the graphene transistor; a source contact on the substrate over the graphene sheet; a drain contact on the substrate over the graphene sheet, wherein the drain contact is separated from the source contact by a gap; at least one slot in the graphene sheet having a width that allows an etchant to pass through the graphene sheet; and a gate region in the gap that includes a recess formed by a passing the etchant through the graphene sheet to remove a portion of the substrate in the gap.
(Cu rr ently Amended) The self-aligned graphene transistor of claim 16, wherein the graphene sheet forms further-comprisng a graphene bridge that spans the gap between the source contact and the drain contact.
The self-aligned graphene transistor of claim anisotropic etching of the substrate in the gap. of the graphene bridge between the graphene 16, wherein the gate region is defined by YOR₉₂₀₁₂₀₈₂₃US₂ 4
Layer stacks claimed or described, ordered top of device to substrate.
semiconducting device with graphene bridge and self-aligned gate
transistor with graphene bridge and dual gate
Materials described outside the worked examples.
graphene sheet
substrate
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 illustrates an initial production stage of an exemplary graphene field effect transistor of the present invention in which a graphene sheet is placed on a substrate;
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,803,132Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates an initial production stage of an exemplary graphene field effect transistor of the present invention in which a graphene sheet is placed on a substrate;
Figure 2 shows a first contact and a second contact formed on a substrate in a second production stage of the exemplary graphene field effect transistor;
Figure 3 illustrates a substrate etching stage;
Figure 4 illustrates a coating stage in which a spacer material is deposited;
Figure 5 shows a high-k gate dielectric deposition stage;
Figure 6 illustrates a conductive gate deposition stage for building a dual gate transistor structure;
Figure 7 shows an exemplary graphene field-effect transistor made using the exemplary methods disclosed herein;
Figure 8 shows an alternative embodiment of a graphene field-effect transistor made using the exemplary methods disclosed herein;
Figure 9 shows a top view of a graphene sheet having exemplary slots for allowing molecules to pass through the graphene sheet; and
Figure 10 shows a flowchart illustrating an exemplary method of producing the exemplary graphene field effect transistor disclosed herein.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconducting device, comprising: a graphene sheet formed on a substrate; a first contact coupled to the graphene sheet and a second contact coupled to the graphene sheet and separated from the first contact by a gap; at least one slot formed in the graphene sheet having a width that allows an etchant to pass through the graphene sheet; and a recess formed in the substrate beneath the graphene sheet via etchant passing through the graphene sheet.
(Cu rr ently Amended) The semiconducting device of claim 1, f-w the * t wherein the graphene sheet forms a graphene bridge th at spans the gap between the first contact and the second contact.
The semiconducting device of claim 1, wherein the first contact and the second contact provide a self-aligned gate structure of the semiconducting device.
The semiconducting device of claim 1, wherein the recess further comprises an anisotropically etched recess.
A transistor, comprising: a graphene sheet disposed directly on a substrate; two ene or more contacts formed on the graphene sheet to define a gap between the t wo ene or more contacts;-and at least one slot in the graphene sheet having a width that allows an etchant to pass through the graphene sheet in the gap; and a gate material in the gap defined by the one or more contacts, wherein the gate material fills a recess in the gap.
(Cu rr ently Amended) The transistor of claim 9, wherein the graphene sheet forms further-cmprising a graphene bridge spanning the gap between the one or more contacts.
The transistor of claim 9, wherein the one or more contacts provide a self-aligned gate structure of the transistor.
A self-aligned graphene transistor, comprising: a graphene sheet disposed on a substrate of the graphene transistor; a source contact on the substrate over the graphene sheet; a drain contact on the substrate over the graphene sheet, wherein the drain contact is separated from the source contact by a gap; at least one slot in the graphene sheet having a width that allows an etchant to pass through the graphene sheet; and a gate region in the gap that includes a recess formed by a passing the etchant through the graphene sheet to remove a portion of the substrate in the gap.
(Cu rr ently Amended) The self-aligned graphene transistor of claim 16, wherein the graphene sheet forms further-comprisng a graphene bridge that spans the gap between the source contact and the drain contact.
The self-aligned graphene transistor of claim anisotropic etching of the substrate in the gap. of the graphene bridge between the graphene 16, wherein the gate region is defined by YOR₉₂₀₁₂₀₈₂₃US₂ 4
Layer stacks claimed or described, ordered top of device to substrate.
semiconducting device with graphene bridge and self-aligned gate
transistor with graphene bridge and dual gate
Materials described outside the worked examples.
graphene sheet
substrate
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 illustrates an initial production stage of an exemplary graphene field effect transistor of the present invention in which a graphene sheet is placed on a substrate;
Related documents with shared materials, methods, properties, or citations.
self-aligned graphene transistor
dual-gate graphene field-effect transistor (GFET) on SOI
silicon-on-insulator (SOI) substrate with silicon layer on buried oxide (BOX)
silicon substrate
Si
buried oxide (BOX) layer
SiO₂
gate material
gate metal (palladium or tungsten)
high-k dielectric material
HfO₂
Al₂O₃
spacer material (low-k dielectric)
SiCOH spacer
palladium contact
Pd
Figure 2 shows a first contact and a second contact formed on a substrate in a second production stage of the exemplary graphene field effect transistor;
Figure 6 illustrates a conductive gate deposition stage for building a dual gate transistor structure;
Figure 7 shows an exemplary graphene field-effect transistor made using the exemplary methods disclosed herein;
Figure 8 shows an alternative embodiment of a graphene field-effect transistor made using the exemplary methods disclosed herein;
Figure 10 shows a flowchart illustrating an exemplary method of producing the exemplary graphene field effect transistor disclosed herein.
self-aligned graphene transistor
dual-gate graphene field-effect transistor (GFET) on SOI
silicon-on-insulator (SOI) substrate with silicon layer on buried oxide (BOX)
silicon substrate
Si
buried oxide (BOX) layer
SiO₂
gate material
gate metal (palladium or tungsten)
high-k dielectric material
HfO₂
Al₂O₃
spacer material (low-k dielectric)
SiCOH spacer
palladium contact
Pd
Figure 2 shows a first contact and a second contact formed on a substrate in a second production stage of the exemplary graphene field effect transistor;
Figure 6 illustrates a conductive gate deposition stage for building a dual gate transistor structure;
Figure 7 shows an exemplary graphene field-effect transistor made using the exemplary methods disclosed herein;
Figure 8 shows an alternative embodiment of a graphene field-effect transistor made using the exemplary methods disclosed herein;
Figure 10 shows a flowchart illustrating an exemplary method of producing the exemplary graphene field effect transistor disclosed herein.
self-aligned graphene transistor
dual-gate graphene field-effect transistor (GFET) on SOI
silicon-on-insulator (SOI) substrate with silicon layer on buried oxide (BOX)
silicon substrate
Si
buried oxide (BOX) layer
SiO₂
gate material
gate metal (palladium or tungsten)
high-k dielectric material
HfO₂
Al₂O₃
spacer material (low-k dielectric)
SiCOH spacer
palladium contact
Pd
Figure 2 shows a first contact and a second contact formed on a substrate in a second production stage of the exemplary graphene field effect transistor;
Figure 6 illustrates a conductive gate deposition stage for building a dual gate transistor structure;
Figure 7 shows an exemplary graphene field-effect transistor made using the exemplary methods disclosed herein;
Figure 8 shows an alternative embodiment of a graphene field-effect transistor made using the exemplary methods disclosed herein;
Figure 10 shows a flowchart illustrating an exemplary method of producing the exemplary graphene field effect transistor disclosed herein.
self-aligned graphene transistor
dual-gate graphene field-effect transistor (GFET) on SOI
silicon-on-insulator (SOI) substrate with silicon layer on buried oxide (BOX)
silicon substrate
Si
buried oxide (BOX) layer
SiO₂
gate material
gate metal (palladium or tungsten)
high-k dielectric material
HfO₂
Al₂O₃
spacer material (low-k dielectric)
SiCOH spacer
palladium contact
Pd
Figure 2 shows a first contact and a second contact formed on a substrate in a second production stage of the exemplary graphene field effect transistor;
Figure 6 illustrates a conductive gate deposition stage for building a dual gate transistor structure;
Figure 7 shows an exemplary graphene field-effect transistor made using the exemplary methods disclosed herein;
Figure 8 shows an alternative embodiment of a graphene field-effect transistor made using the exemplary methods disclosed herein;
Figure 10 shows a flowchart illustrating an exemplary method of producing the exemplary graphene field effect transistor disclosed herein.