Patent
US 8,742,478GRAPHENE TRANSISTOR HAVING AIR GAP, HYBRID TRANSISTOR HAVING THE SAME, AND METHODS OF FABRICATING THE SAME
Hyun-jong CHUNG
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,742,478Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a graphene transistor according to an example embodiment; [0028]
FIG. 2 is a plan view showing the disposition of electrodes of the graphene transistor of
FIG. 3 is a schematic cross-sectional view of a graphene transistor according to another example embodiment; [0030]
FIG. 4 is a plan view showing the arrangement of electrodes of the graphene transistor of
FIG. 5 is a schematic cross-sectional view of a hybrid transistor including a graphene transistor, according to an example embodiment; [0032]
FIG. 6 is a plan view showing the arrangement of electrodes of the graphene transistor of
FIGS. 7A through 7F are cross-sectional views sequentially showing a method of fabricating a hybrid transistor, according to an example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene transistor comprising: a gate electrode on a substrate; a gate insulating layer on the gate electrode, the g ate in sulating layer hav in g a substantially flat shape; a graphene channel fixedly disposed on the gate insulating l ayer; a source electrode and a drain electrode on the graphene channel, the source electrode and drain electrode be in g separate from each other; and a cover that covers upper surfaces of the source electrode and the dra in electrode and forms an air gap above the graphene channel between the source electrode and the drain electrode.
(Onginal) The graphene transistor of claim 1, wherein a length of the graphene channel between the source electrode and the drain electrode is m a range of about 10 nm to about 100 nm.
The graphene transistor of claim 1, wherein the air gap has a height Page 2 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869671.2.23.135.2265.231.svg 0.32 7.473 Graph Black and white in a range of about 20 nm to about 200 nm.
The graphene transistor of claim 1, wherein the graphene channel is formed of one to five graphene layers.
(O ngin al) The graphene transistor of cla im 1, wherein the cover is formed of a SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869670.23.269.2673.1332.2743.svg 0.233 3.543 Graph Black and white
The graphene transistor of cla in 1, where m the gate insulat in g layer is formed of hexagonal boron nitn de.
The graphene transistor of claim 5, wherein the gate in sulating layer has a t hi ckness in a range of about 0.5 nm to about 30 nm.
The-graphene-trancictor of clam, A graphene transistor comprising: a gate electrode on a substrate; a gate insulat ng layer on the g ate electrode; a gr aphene channel on the gate insulat m g la v er; a source electrode and a drain electrode on the graphene channel, the source electrode and dram electrode being separate from each other; and a cover that covers upper surfaces of the source electrode and the drain electrode and forms an air g ap above the graphene channel between the source electrode and the dra mn electrode, where in the source electrode and the drain electrode are on opposite sides of the graphene channel and include a plurality of interdigitated source and drain finger electrodes, and the gate electrode in cludes a plurality of gate finger electrodes disposed to cover a gap between two neighboring in terdigitated source and drain finger electrodes. Page 3 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869672.2.24.133.2264.229.svg 0.32 7.467 Graph Black and white
A hybrid transistor comprising: a metal-oxide-semiconductor (MOS) transistor on a substrate; [[and]] a graphene transistor disposed above the MOS transistor, the graphene transistor including, a gate electrode on a first interlayer insulating layer, the first interlayer insulating layer covenn g the MOS transistor, a g ate insulating la y er on the gate electrode, a graphene channel on the gate insulatin g la yer, a source electrode and a drain electrode on the graphene channel, the source electrode and the drain electrode being separate from each other, and a cover that covers upper surfaces of the source electrode and the drain electrode and forms an air gap on the graphene channel between the source electrode and the drain electrode. currently amended
canceled
The hybrid transistor of claim [[1 0]] 9, where mn a length of the graphene channel between the source electrode and the drain electrode is in a range of about 10 nm to about 100 nm.
The hybnd transistor of claim [[10]] 9, wherein the cover is formed of a porous polymer or a porous insulat in g material.
The hybnd transistor of claim [[10]]9, where in the air gap has a height m a range of about 20 nm to about 200 n m. Page 4 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869673.2.12.132.2259.229.svg 0.323 7.49 Graph Black and white
The hybrid transistor of claim [[10]] 9, wherein the gate insulating layer is formed of hexagonal boron nitride.
(Ong m al) The hyb n d transistor of claim 14, wherein the gate insulating layer has a thickness in a range of about 0.5 nm to about 30 nm.
The hybrid transistor of claim [[10]] 9, where m the graphene channel is formed of one to five graphene layers.
The hybrid transistor of claim [[10]] 9, wherein the source electrode and the drain electrode are on opposite sides of the graphene channel and include a plura li ty of interdigitated source and drain finger electrodes, and the gate electrode includes a plura li ty of gate finger electrodes disposed to cover a gap between two neighboring interdigitated source and drain finger electrodes.
A method of fabricat in g a hybrid transistor, the method compris ing: form in g a metal-oxide-se mi conductor (MOS) transistor on a substrate; forming a first interlayer insulating layer cove n ng the MOS transistor on the substrate; for mi ng first metals connected to a source region and a drain region of the MOS transistor, and form in g a gate electrode on the first interlayer in sulating layer; sequentially forming a gate insulat m g layer and a graphene channel on the gate electrode; form in g second metals connected to the first metals on the first in terlayer insulating layer, and form in g a source electrode and a drain electrode on the graphene channel, the source electrode and the drain electrode being separate from each other; Page 5 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869674.2.16.135.2261.231.svg 0.32 7.483 Graph Black and white filling a space between the source electrode and the drain electrode with a polymer; for mn g a cover that covers the polymer on the source electrode and the drain electrode; and forming an air gap between the graphene channel and the cover by removing the polymer.
The method of claim 18, wherein the length of the graphene channel between the source electrode and the dra in electrode is in a range of about 10 nm to about 100 nm.
(O n ginal) The method of claim 18, wherein the cover is formed of a porous polymer or a porous insulating material.
The method of claim 18, wherein the air gap has a height in a range of about 20 nm to about 200 nm.
The method of claim 18, wherein the gate insulat in g layer is formed of a hexagonal boron nit n de.
The method of claim 18, wherein the graphene channel is formed of one to five graphene layers. Page 6 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869675.2.23.133.2266.230.svg 0.323 7.477 Graph Black and white
(Onginal) The method of claim 18, wherein the forming of the source electrode and the drain electrode includes forming the source electrode and the drain electrode on opposite sides of the graphene channel and forming a plurality of interdigitated source and drain finger electrodes, and the forming of the gate electrode includes forming a plurality of gate finger electrodes disposed to cover a gap between two neighboring interdigitated source and drain finger electrodes. *** END CLAIM LISTING *** Page 7
(O ngin al) The method of cla um 22, wherein the gate insulat m g layer has a thickness in a range of about 0.5 nm to about 30 nm.
Layer stacks claimed or described, ordered top of device to substrate.
graphene transistor with air gap (flat gate insulator)
Materials described outside the worked examples.
graphene
C
hexagonal boron nitride
h-BN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic cross-sectional view of a graphene transistor according to an example embodiment; [0028]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–300 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,742,478Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a graphene transistor according to an example embodiment; [0028]
FIG. 2 is a plan view showing the disposition of electrodes of the graphene transistor of
FIG. 3 is a schematic cross-sectional view of a graphene transistor according to another example embodiment; [0030]
FIG. 4 is a plan view showing the arrangement of electrodes of the graphene transistor of
FIG. 5 is a schematic cross-sectional view of a hybrid transistor including a graphene transistor, according to an example embodiment; [0032]
FIG. 6 is a plan view showing the arrangement of electrodes of the graphene transistor of
FIGS. 7A through 7F are cross-sectional views sequentially showing a method of fabricating a hybrid transistor, according to an example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene transistor comprising: a gate electrode on a substrate; a gate insulating layer on the gate electrode, the g ate in sulating layer hav in g a substantially flat shape; a graphene channel fixedly disposed on the gate insulating l ayer; a source electrode and a drain electrode on the graphene channel, the source electrode and drain electrode be in g separate from each other; and a cover that covers upper surfaces of the source electrode and the dra in electrode and forms an air gap above the graphene channel between the source electrode and the drain electrode.
(Onginal) The graphene transistor of claim 1, wherein a length of the graphene channel between the source electrode and the drain electrode is m a range of about 10 nm to about 100 nm.
The graphene transistor of claim 1, wherein the air gap has a height Page 2 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869671.2.23.135.2265.231.svg 0.32 7.473 Graph Black and white in a range of about 20 nm to about 200 nm.
The graphene transistor of claim 1, wherein the graphene channel is formed of one to five graphene layers.
(O ngin al) The graphene transistor of cla im 1, wherein the cover is formed of a SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869670.23.269.2673.1332.2743.svg 0.233 3.543 Graph Black and white
The graphene transistor of cla in 1, where m the gate insulat in g layer is formed of hexagonal boron nitn de.
The graphene transistor of claim 5, wherein the gate in sulating layer has a t hi ckness in a range of about 0.5 nm to about 30 nm.
The-graphene-trancictor of clam, A graphene transistor comprising: a gate electrode on a substrate; a gate insulat ng layer on the g ate electrode; a gr aphene channel on the gate insulat m g la v er; a source electrode and a drain electrode on the graphene channel, the source electrode and dram electrode being separate from each other; and a cover that covers upper surfaces of the source electrode and the drain electrode and forms an air g ap above the graphene channel between the source electrode and the dra mn electrode, where in the source electrode and the drain electrode are on opposite sides of the graphene channel and include a plurality of interdigitated source and drain finger electrodes, and the gate electrode in cludes a plurality of gate finger electrodes disposed to cover a gap between two neighboring in terdigitated source and drain finger electrodes. Page 3 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869672.2.24.133.2264.229.svg 0.32 7.467 Graph Black and white
A hybrid transistor comprising: a metal-oxide-semiconductor (MOS) transistor on a substrate; [[and]] a graphene transistor disposed above the MOS transistor, the graphene transistor including, a gate electrode on a first interlayer insulating layer, the first interlayer insulating layer covenn g the MOS transistor, a g ate insulating la y er on the gate electrode, a graphene channel on the gate insulatin g la yer, a source electrode and a drain electrode on the graphene channel, the source electrode and the drain electrode being separate from each other, and a cover that covers upper surfaces of the source electrode and the drain electrode and forms an air gap on the graphene channel between the source electrode and the drain electrode. currently amended
canceled
The hybrid transistor of claim [[1 0]] 9, where mn a length of the graphene channel between the source electrode and the drain electrode is in a range of about 10 nm to about 100 nm.
The hybnd transistor of claim [[10]] 9, wherein the cover is formed of a porous polymer or a porous insulat in g material.
The hybnd transistor of claim [[10]]9, where in the air gap has a height m a range of about 20 nm to about 200 n m. Page 4 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869673.2.12.132.2259.229.svg 0.323 7.49 Graph Black and white
The hybrid transistor of claim [[10]] 9, wherein the gate insulating layer is formed of hexagonal boron nitride.
(Ong m al) The hyb n d transistor of claim 14, wherein the gate insulating layer has a thickness in a range of about 0.5 nm to about 30 nm.
The hybrid transistor of claim [[10]] 9, where m the graphene channel is formed of one to five graphene layers.
The hybrid transistor of claim [[10]] 9, wherein the source electrode and the drain electrode are on opposite sides of the graphene channel and include a plura li ty of interdigitated source and drain finger electrodes, and the gate electrode includes a plura li ty of gate finger electrodes disposed to cover a gap between two neighboring interdigitated source and drain finger electrodes.
A method of fabricat in g a hybrid transistor, the method compris ing: form in g a metal-oxide-se mi conductor (MOS) transistor on a substrate; forming a first interlayer insulating layer cove n ng the MOS transistor on the substrate; for mi ng first metals connected to a source region and a drain region of the MOS transistor, and form in g a gate electrode on the first interlayer in sulating layer; sequentially forming a gate insulat m g layer and a graphene channel on the gate electrode; form in g second metals connected to the first metals on the first in terlayer insulating layer, and form in g a source electrode and a drain electrode on the graphene channel, the source electrode and the drain electrode being separate from each other; Page 5 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869674.2.16.135.2261.231.svg 0.32 7.483 Graph Black and white filling a space between the source electrode and the drain electrode with a polymer; for mn g a cover that covers the polymer on the source electrode and the drain electrode; and forming an air gap between the graphene channel and the cover by removing the polymer.
The method of claim 18, wherein the length of the graphene channel between the source electrode and the dra in electrode is in a range of about 10 nm to about 100 nm.
(O n ginal) The method of claim 18, wherein the cover is formed of a porous polymer or a porous insulating material.
The method of claim 18, wherein the air gap has a height in a range of about 20 nm to about 200 nm.
The method of claim 18, wherein the gate insulat in g layer is formed of a hexagonal boron nit n de.
The method of claim 18, wherein the graphene channel is formed of one to five graphene layers. Page 6 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869675.2.23.133.2266.230.svg 0.323 7.477 Graph Black and white
(Onginal) The method of claim 18, wherein the forming of the source electrode and the drain electrode includes forming the source electrode and the drain electrode on opposite sides of the graphene channel and forming a plurality of interdigitated source and drain finger electrodes, and the forming of the gate electrode includes forming a plurality of gate finger electrodes disposed to cover a gap between two neighboring interdigitated source and drain finger electrodes. *** END CLAIM LISTING *** Page 7
(O ngin al) The method of cla um 22, wherein the gate insulat m g layer has a thickness in a range of about 0.5 nm to about 30 nm.
Layer stacks claimed or described, ordered top of device to substrate.
graphene transistor with air gap (flat gate insulator)
Materials described outside the worked examples.
graphene
C
hexagonal boron nitride
h-BN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic cross-sectional view of a graphene transistor according to an example embodiment; [0028]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–300 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,742,478Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a graphene transistor according to an example embodiment; [0028]
FIG. 2 is a plan view showing the disposition of electrodes of the graphene transistor of
FIG. 3 is a schematic cross-sectional view of a graphene transistor according to another example embodiment; [0030]
FIG. 4 is a plan view showing the arrangement of electrodes of the graphene transistor of
FIG. 5 is a schematic cross-sectional view of a hybrid transistor including a graphene transistor, according to an example embodiment; [0032]
FIG. 6 is a plan view showing the arrangement of electrodes of the graphene transistor of
FIGS. 7A through 7F are cross-sectional views sequentially showing a method of fabricating a hybrid transistor, according to an example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene transistor comprising: a gate electrode on a substrate; a gate insulating layer on the gate electrode, the g ate in sulating layer hav in g a substantially flat shape; a graphene channel fixedly disposed on the gate insulating l ayer; a source electrode and a drain electrode on the graphene channel, the source electrode and drain electrode be in g separate from each other; and a cover that covers upper surfaces of the source electrode and the dra in electrode and forms an air gap above the graphene channel between the source electrode and the drain electrode.
(Onginal) The graphene transistor of claim 1, wherein a length of the graphene channel between the source electrode and the drain electrode is m a range of about 10 nm to about 100 nm.
The graphene transistor of claim 1, wherein the air gap has a height Page 2 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869671.2.23.135.2265.231.svg 0.32 7.473 Graph Black and white in a range of about 20 nm to about 200 nm.
The graphene transistor of claim 1, wherein the graphene channel is formed of one to five graphene layers.
(O ngin al) The graphene transistor of cla im 1, wherein the cover is formed of a SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869670.23.269.2673.1332.2743.svg 0.233 3.543 Graph Black and white
The graphene transistor of cla in 1, where m the gate insulat in g layer is formed of hexagonal boron nitn de.
The graphene transistor of claim 5, wherein the gate in sulating layer has a t hi ckness in a range of about 0.5 nm to about 30 nm.
The-graphene-trancictor of clam, A graphene transistor comprising: a gate electrode on a substrate; a gate insulat ng layer on the g ate electrode; a gr aphene channel on the gate insulat m g la v er; a source electrode and a drain electrode on the graphene channel, the source electrode and dram electrode being separate from each other; and a cover that covers upper surfaces of the source electrode and the drain electrode and forms an air g ap above the graphene channel between the source electrode and the dra mn electrode, where in the source electrode and the drain electrode are on opposite sides of the graphene channel and include a plurality of interdigitated source and drain finger electrodes, and the gate electrode in cludes a plurality of gate finger electrodes disposed to cover a gap between two neighboring in terdigitated source and drain finger electrodes. Page 3 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869672.2.24.133.2264.229.svg 0.32 7.467 Graph Black and white
A hybrid transistor comprising: a metal-oxide-semiconductor (MOS) transistor on a substrate; [[and]] a graphene transistor disposed above the MOS transistor, the graphene transistor including, a gate electrode on a first interlayer insulating layer, the first interlayer insulating layer covenn g the MOS transistor, a g ate insulating la y er on the gate electrode, a graphene channel on the gate insulatin g la yer, a source electrode and a drain electrode on the graphene channel, the source electrode and the drain electrode being separate from each other, and a cover that covers upper surfaces of the source electrode and the drain electrode and forms an air gap on the graphene channel between the source electrode and the drain electrode. currently amended
canceled
The hybrid transistor of claim [[1 0]] 9, where mn a length of the graphene channel between the source electrode and the drain electrode is in a range of about 10 nm to about 100 nm.
The hybnd transistor of claim [[10]] 9, wherein the cover is formed of a porous polymer or a porous insulat in g material.
The hybnd transistor of claim [[10]]9, where in the air gap has a height m a range of about 20 nm to about 200 n m. Page 4 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869673.2.12.132.2259.229.svg 0.323 7.49 Graph Black and white
The hybrid transistor of claim [[10]] 9, wherein the gate insulating layer is formed of hexagonal boron nitride.
(Ong m al) The hyb n d transistor of claim 14, wherein the gate insulating layer has a thickness in a range of about 0.5 nm to about 30 nm.
The hybrid transistor of claim [[10]] 9, where m the graphene channel is formed of one to five graphene layers.
The hybrid transistor of claim [[10]] 9, wherein the source electrode and the drain electrode are on opposite sides of the graphene channel and include a plura li ty of interdigitated source and drain finger electrodes, and the gate electrode includes a plura li ty of gate finger electrodes disposed to cover a gap between two neighboring interdigitated source and drain finger electrodes.
A method of fabricat in g a hybrid transistor, the method compris ing: form in g a metal-oxide-se mi conductor (MOS) transistor on a substrate; forming a first interlayer insulating layer cove n ng the MOS transistor on the substrate; for mi ng first metals connected to a source region and a drain region of the MOS transistor, and form in g a gate electrode on the first interlayer in sulating layer; sequentially forming a gate insulat m g layer and a graphene channel on the gate electrode; form in g second metals connected to the first metals on the first in terlayer insulating layer, and form in g a source electrode and a drain electrode on the graphene channel, the source electrode and the drain electrode being separate from each other; Page 5 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869674.2.16.135.2261.231.svg 0.32 7.483 Graph Black and white filling a space between the source electrode and the drain electrode with a polymer; for mn g a cover that covers the polymer on the source electrode and the drain electrode; and forming an air gap between the graphene channel and the cover by removing the polymer.
The method of claim 18, wherein the length of the graphene channel between the source electrode and the dra in electrode is in a range of about 10 nm to about 100 nm.
(O n ginal) The method of claim 18, wherein the cover is formed of a porous polymer or a porous insulating material.
The method of claim 18, wherein the air gap has a height in a range of about 20 nm to about 200 nm.
The method of claim 18, wherein the gate insulat in g layer is formed of a hexagonal boron nit n de.
The method of claim 18, wherein the graphene channel is formed of one to five graphene layers. Page 6 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869675.2.23.133.2266.230.svg 0.323 7.477 Graph Black and white
(Onginal) The method of claim 18, wherein the forming of the source electrode and the drain electrode includes forming the source electrode and the drain electrode on opposite sides of the graphene channel and forming a plurality of interdigitated source and drain finger electrodes, and the forming of the gate electrode includes forming a plurality of gate finger electrodes disposed to cover a gap between two neighboring interdigitated source and drain finger electrodes. *** END CLAIM LISTING *** Page 7
(O ngin al) The method of cla um 22, wherein the gate insulat m g layer has a thickness in a range of about 0.5 nm to about 30 nm.
Layer stacks claimed or described, ordered top of device to substrate.
graphene transistor with air gap (flat gate insulator)
Materials described outside the worked examples.
graphene
C
hexagonal boron nitride
h-BN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic cross-sectional view of a graphene transistor according to an example embodiment; [0028]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–300 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,742,478Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a graphene transistor according to an example embodiment; [0028]
FIG. 2 is a plan view showing the disposition of electrodes of the graphene transistor of
FIG. 3 is a schematic cross-sectional view of a graphene transistor according to another example embodiment; [0030]
FIG. 4 is a plan view showing the arrangement of electrodes of the graphene transistor of
FIG. 5 is a schematic cross-sectional view of a hybrid transistor including a graphene transistor, according to an example embodiment; [0032]
FIG. 6 is a plan view showing the arrangement of electrodes of the graphene transistor of
FIGS. 7A through 7F are cross-sectional views sequentially showing a method of fabricating a hybrid transistor, according to an example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene transistor comprising: a gate electrode on a substrate; a gate insulating layer on the gate electrode, the g ate in sulating layer hav in g a substantially flat shape; a graphene channel fixedly disposed on the gate insulating l ayer; a source electrode and a drain electrode on the graphene channel, the source electrode and drain electrode be in g separate from each other; and a cover that covers upper surfaces of the source electrode and the dra in electrode and forms an air gap above the graphene channel between the source electrode and the drain electrode.
(Onginal) The graphene transistor of claim 1, wherein a length of the graphene channel between the source electrode and the drain electrode is m a range of about 10 nm to about 100 nm.
The graphene transistor of claim 1, wherein the air gap has a height Page 2 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869671.2.23.135.2265.231.svg 0.32 7.473 Graph Black and white in a range of about 20 nm to about 200 nm.
The graphene transistor of claim 1, wherein the graphene channel is formed of one to five graphene layers.
(O ngin al) The graphene transistor of cla im 1, wherein the cover is formed of a SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869670.23.269.2673.1332.2743.svg 0.233 3.543 Graph Black and white
The graphene transistor of cla in 1, where m the gate insulat in g layer is formed of hexagonal boron nitn de.
The graphene transistor of claim 5, wherein the gate in sulating layer has a t hi ckness in a range of about 0.5 nm to about 30 nm.
The-graphene-trancictor of clam, A graphene transistor comprising: a gate electrode on a substrate; a gate insulat ng layer on the g ate electrode; a gr aphene channel on the gate insulat m g la v er; a source electrode and a drain electrode on the graphene channel, the source electrode and dram electrode being separate from each other; and a cover that covers upper surfaces of the source electrode and the drain electrode and forms an air g ap above the graphene channel between the source electrode and the dra mn electrode, where in the source electrode and the drain electrode are on opposite sides of the graphene channel and include a plurality of interdigitated source and drain finger electrodes, and the gate electrode in cludes a plurality of gate finger electrodes disposed to cover a gap between two neighboring in terdigitated source and drain finger electrodes. Page 3 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869672.2.24.133.2264.229.svg 0.32 7.467 Graph Black and white
A hybrid transistor comprising: a metal-oxide-semiconductor (MOS) transistor on a substrate; [[and]] a graphene transistor disposed above the MOS transistor, the graphene transistor including, a gate electrode on a first interlayer insulating layer, the first interlayer insulating layer covenn g the MOS transistor, a g ate insulating la y er on the gate electrode, a graphene channel on the gate insulatin g la yer, a source electrode and a drain electrode on the graphene channel, the source electrode and the drain electrode being separate from each other, and a cover that covers upper surfaces of the source electrode and the drain electrode and forms an air gap on the graphene channel between the source electrode and the drain electrode. currently amended
canceled
The hybrid transistor of claim [[1 0]] 9, where mn a length of the graphene channel between the source electrode and the drain electrode is in a range of about 10 nm to about 100 nm.
The hybnd transistor of claim [[10]] 9, wherein the cover is formed of a porous polymer or a porous insulat in g material.
The hybnd transistor of claim [[10]]9, where in the air gap has a height m a range of about 20 nm to about 200 n m. Page 4 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869673.2.12.132.2259.229.svg 0.323 7.49 Graph Black and white
The hybrid transistor of claim [[10]] 9, wherein the gate insulating layer is formed of hexagonal boron nitride.
(Ong m al) The hyb n d transistor of claim 14, wherein the gate insulating layer has a thickness in a range of about 0.5 nm to about 30 nm.
The hybrid transistor of claim [[10]] 9, where m the graphene channel is formed of one to five graphene layers.
The hybrid transistor of claim [[10]] 9, wherein the source electrode and the drain electrode are on opposite sides of the graphene channel and include a plura li ty of interdigitated source and drain finger electrodes, and the gate electrode includes a plura li ty of gate finger electrodes disposed to cover a gap between two neighboring interdigitated source and drain finger electrodes.
A method of fabricat in g a hybrid transistor, the method compris ing: form in g a metal-oxide-se mi conductor (MOS) transistor on a substrate; forming a first interlayer insulating layer cove n ng the MOS transistor on the substrate; for mi ng first metals connected to a source region and a drain region of the MOS transistor, and form in g a gate electrode on the first interlayer in sulating layer; sequentially forming a gate insulat m g layer and a graphene channel on the gate electrode; form in g second metals connected to the first metals on the first in terlayer insulating layer, and form in g a source electrode and a drain electrode on the graphene channel, the source electrode and the drain electrode being separate from each other; Page 5 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869674.2.16.135.2261.231.svg 0.32 7.483 Graph Black and white filling a space between the source electrode and the drain electrode with a polymer; for mn g a cover that covers the polymer on the source electrode and the drain electrode; and forming an air gap between the graphene channel and the cover by removing the polymer.
The method of claim 18, wherein the length of the graphene channel between the source electrode and the dra in electrode is in a range of about 10 nm to about 100 nm.
(O n ginal) The method of claim 18, wherein the cover is formed of a porous polymer or a porous insulating material.
The method of claim 18, wherein the air gap has a height in a range of about 20 nm to about 200 nm.
The method of claim 18, wherein the gate insulat in g layer is formed of a hexagonal boron nit n de.
The method of claim 18, wherein the graphene channel is formed of one to five graphene layers. Page 6 SVG 13667097.12-05-2013.HP₉U₁₆GPPXXIFW4.CLM8869675.2.23.133.2266.230.svg 0.323 7.477 Graph Black and white
(Onginal) The method of claim 18, wherein the forming of the source electrode and the drain electrode includes forming the source electrode and the drain electrode on opposite sides of the graphene channel and forming a plurality of interdigitated source and drain finger electrodes, and the forming of the gate electrode includes forming a plurality of gate finger electrodes disposed to cover a gap between two neighboring interdigitated source and drain finger electrodes. *** END CLAIM LISTING *** Page 7
(O ngin al) The method of cla um 22, wherein the gate insulat m g layer has a thickness in a range of about 0.5 nm to about 30 nm.
Layer stacks claimed or described, ordered top of device to substrate.
graphene transistor with air gap (flat gate insulator)
Materials described outside the worked examples.
graphene
C
hexagonal boron nitride
h-BN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic cross-sectional view of a graphene transistor according to an example embodiment; [0028]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–300 nm | — |
Thickness |
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graphene transistor with interdigitated source/drain and gate finger electrodes
hybrid transistor (MOS + graphene transistor stacked)
hybrid transistor with interdigitated source/drain and gate finger electrodes
porous polymer or porous insulating material
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silicon oxide
SiO₂
silicon
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FIG. 2 is a plan view showing the disposition of electrodes of the graphene transistor of
FIG. 3 is a schematic cross-sectional view of a graphene transistor according to another example embodiment; [0030]
FIG. 4 is a plan view showing the arrangement of electrodes of the graphene transistor of
FIG. 5 is a schematic cross-sectional view of a hybrid transistor including a graphene transistor, according to an example embodiment; [0032]
FIG. 6 is a plan view showing the arrangement of electrodes of the graphene transistor of
FIGS. 7A through 7F are cross-sectional views sequentially showing a method of fabricating a hybrid transistor, according to an example embodiment.
| — |
Thickness | 20–200 nm | — |
Thickness | ≤ 30 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≥ 30 nm | — |
Thickness | ≥ 1 nm | — |
Thickness | 0.5–30 nm | — |
graphene transistor with interdigitated source/drain and gate finger electrodes
hybrid transistor (MOS + graphene transistor stacked)
hybrid transistor with interdigitated source/drain and gate finger electrodes
porous polymer or porous insulating material
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silicon oxide
SiO₂
silicon
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FIG. 2 is a plan view showing the disposition of electrodes of the graphene transistor of
FIG. 3 is a schematic cross-sectional view of a graphene transistor according to another example embodiment; [0030]
FIG. 4 is a plan view showing the arrangement of electrodes of the graphene transistor of
FIG. 5 is a schematic cross-sectional view of a hybrid transistor including a graphene transistor, according to an example embodiment; [0032]
FIG. 6 is a plan view showing the arrangement of electrodes of the graphene transistor of
FIGS. 7A through 7F are cross-sectional views sequentially showing a method of fabricating a hybrid transistor, according to an example embodiment.
| — |
Thickness | 20–200 nm | — |
Thickness | ≤ 30 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≥ 30 nm | — |
Thickness | ≥ 1 nm | — |
Thickness | 0.5–30 nm | — |
graphene transistor with interdigitated source/drain and gate finger electrodes
hybrid transistor (MOS + graphene transistor stacked)
hybrid transistor with interdigitated source/drain and gate finger electrodes
porous polymer or porous insulating material
polymer (sacrificial)
silicon oxide
SiO₂
silicon
Si
FIG. 2 is a plan view showing the disposition of electrodes of the graphene transistor of
FIG. 3 is a schematic cross-sectional view of a graphene transistor according to another example embodiment; [0030]
FIG. 4 is a plan view showing the arrangement of electrodes of the graphene transistor of
FIG. 5 is a schematic cross-sectional view of a hybrid transistor including a graphene transistor, according to an example embodiment; [0032]
FIG. 6 is a plan view showing the arrangement of electrodes of the graphene transistor of
FIGS. 7A through 7F are cross-sectional views sequentially showing a method of fabricating a hybrid transistor, according to an example embodiment.
| — |
Thickness | 20–200 nm | — |
Thickness | ≤ 30 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≥ 30 nm | — |
Thickness | ≥ 1 nm | — |
Thickness | 0.5–30 nm | — |
graphene transistor with interdigitated source/drain and gate finger electrodes
hybrid transistor (MOS + graphene transistor stacked)
hybrid transistor with interdigitated source/drain and gate finger electrodes
porous polymer or porous insulating material
polymer (sacrificial)
silicon oxide
SiO₂
silicon
Si
FIG. 2 is a plan view showing the disposition of electrodes of the graphene transistor of
FIG. 3 is a schematic cross-sectional view of a graphene transistor according to another example embodiment; [0030]
FIG. 4 is a plan view showing the arrangement of electrodes of the graphene transistor of
FIG. 5 is a schematic cross-sectional view of a hybrid transistor including a graphene transistor, according to an example embodiment; [0032]
FIG. 6 is a plan view showing the arrangement of electrodes of the graphene transistor of
FIGS. 7A through 7F are cross-sectional views sequentially showing a method of fabricating a hybrid transistor, according to an example embodiment.
| — |
Thickness | 20–200 nm | — |
Thickness | ≤ 30 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≥ 30 nm | — |
Thickness | ≥ 1 nm | — |
Thickness | 0.5–30 nm | — |