Patent
US 9,318,556GRAPHENE TRANSISTOR HAVING TUNABLE BARRIER
Jin-hong PARK
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,318,556Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a graphene transistor having a tunable barrier according to example embodiments; [0020]
FIG. 2 is an energy band diagram of an n-type graphene transistor without an insulating thin film according to example embodiments; [0021]
FIGS. 3A and 3B are energy band diagrams for explaining an operation of the n-type graphene transistor of
FIG. 4 is an energy band diagram of a p-type graphene transistor without an insulating thin film according to example embodiments; [0023]
FIGS. 5A and 5B are energy band diagrams for explaining an operation of the p-type graphene transistor of
FIG. 6 is a schematic cross-sectional view of a graphene transistor having a tunable barrier according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene transistor having a tunable barrier comprising: a semiconductor substrate; an insulating thin film on the semiconductor substrate; a graphene layer on the insulating thin film; a first electrode connected to an end of the graphene layer; a second electrode, separate from an other end of the graphene layer, directly contacting the semiconductor substrate; a gate insulating layer covering at least a portion of the graphene layer; and a gate electrode on the gate insulating layer, and an insulating layer between the graphene layer and the insulating thin film at a location corresponding to the first electrode; wherein an energy barrier is between the semiconductor substrate and the graphene layer.
The graphene transistor of claim 1, wherein the insulating thin film has a thickness in a range of about 1 nm to about 4 nm.
The graphene transistor of claim 1, wherein the insulating thin film includes at least one of A₁₂ 0 3, Hf O 2, Ti O 2, and Si₃N4.
The graphene transistor of claim 1, wherein the semiconductor substrate includes at least one of silicon, germanium, silicon-germanium, a group I II-V Page 2 Application No. 14/328,339 Attorney Docket No. 2557 SI -002182-US semiconductor, and a group I I -VI semiconductor.
The graphene transistor of claim 1, wherein a distance between the graphene layer and the second electrode is in a range of about 1 n m to about 30 n m.
The graphene transistor of claim 1, wherein the graphene layer includes between 1 layer and 4 layers of graphene.
The graphene transistor of claim 1, wherein the graphene layer is separate from the second electrode.
canceled
The graphene transistor of c la im 1, wherein the graphene transistor is a unipolar transistor having a same polarity as a polarity of an impurity of the semiconductor substrate.
The graphene transistor of c la im 1, wherein the energy barrier varies according to a gate voltage applied to the gate electrode.
A graphene transistor having a tunable ba rri er comprising: a back gate substrate; a gate insulating layer on the back gate substrate; a graphene layer on the gate insulating layer; a first electrode on a first region of the graphene layer; and a semiconductor layer, an insulating thin film and a second electrode stacked on a second region of the graphene layer, the second region of the graphene layer being distinct from the first region of the graphene layer; wherein an energy ba rri er is between the semiconductor layer and the graphene Page 3 Application No. 14/328,339 Attorney Docket No. 2557S I -002182-US layer.
The graphene transistor of claim 10, wherein the insulating thin film has a thickness in a range of about 1 nm to about 4 nm.
The graphene transistor of claim 10, wherein the insulating thin film includes at least one of A₁₂ 0 3, Hf O 2, Ti O 2, and Si₃N4.
The graphene transistor of claim 10, wherein the semiconductor layer includes at least one of silicon, germanium, silicon-germanium, a group I II-V semiconductor, and a group I I -VI semiconductor.
The graphene transistor of claim 10, wherein the semiconductor layer has a thickness in a range of about 1 nm to about 10 nm.
The graphene transistor of claim 10, wherein the graphene transistor is a unipolar transistor having a same polarity as a polarity of an impurity of the semiconductor layer.
The graphene transistor of claim 10, wherein the energy barrier varies according to a gate voltage applied to the gate electrode.
The graphene transistor of claim 10, wherein the graphene layer Page 4 Application No. 14/328,339 Attorney Docket No. 2557S I -002182-US includes between 1 layer and 4 layers of graphene. *** END CLAIM LISTING *** Page
Layer stacks claimed or described, ordered top of device to substrate.
graphene transistor having tunable barrier (substrate-based)
graphene transistor having tunable barrier (back-gate, top semiconductor layer)
Materials described outside the worked examples.
graphene
insulating thin film
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic cross-sectional view of a graphene transistor having a tunable barrier according to example embodiments; [0020]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–30 nm | — |
Thickness | 1–4 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,318,556Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a graphene transistor having a tunable barrier according to example embodiments; [0020]
FIG. 2 is an energy band diagram of an n-type graphene transistor without an insulating thin film according to example embodiments; [0021]
FIGS. 3A and 3B are energy band diagrams for explaining an operation of the n-type graphene transistor of
FIG. 4 is an energy band diagram of a p-type graphene transistor without an insulating thin film according to example embodiments; [0023]
FIGS. 5A and 5B are energy band diagrams for explaining an operation of the p-type graphene transistor of
FIG. 6 is a schematic cross-sectional view of a graphene transistor having a tunable barrier according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene transistor having a tunable barrier comprising: a semiconductor substrate; an insulating thin film on the semiconductor substrate; a graphene layer on the insulating thin film; a first electrode connected to an end of the graphene layer; a second electrode, separate from an other end of the graphene layer, directly contacting the semiconductor substrate; a gate insulating layer covering at least a portion of the graphene layer; and a gate electrode on the gate insulating layer, and an insulating layer between the graphene layer and the insulating thin film at a location corresponding to the first electrode; wherein an energy barrier is between the semiconductor substrate and the graphene layer.
The graphene transistor of claim 1, wherein the insulating thin film has a thickness in a range of about 1 nm to about 4 nm.
The graphene transistor of claim 1, wherein the insulating thin film includes at least one of A₁₂ 0 3, Hf O 2, Ti O 2, and Si₃N4.
The graphene transistor of claim 1, wherein the semiconductor substrate includes at least one of silicon, germanium, silicon-germanium, a group I II-V Page 2 Application No. 14/328,339 Attorney Docket No. 2557 SI -002182-US semiconductor, and a group I I -VI semiconductor.
The graphene transistor of claim 1, wherein a distance between the graphene layer and the second electrode is in a range of about 1 n m to about 30 n m.
The graphene transistor of claim 1, wherein the graphene layer includes between 1 layer and 4 layers of graphene.
The graphene transistor of claim 1, wherein the graphene layer is separate from the second electrode.
canceled
The graphene transistor of c la im 1, wherein the graphene transistor is a unipolar transistor having a same polarity as a polarity of an impurity of the semiconductor substrate.
The graphene transistor of c la im 1, wherein the energy barrier varies according to a gate voltage applied to the gate electrode.
A graphene transistor having a tunable ba rri er comprising: a back gate substrate; a gate insulating layer on the back gate substrate; a graphene layer on the gate insulating layer; a first electrode on a first region of the graphene layer; and a semiconductor layer, an insulating thin film and a second electrode stacked on a second region of the graphene layer, the second region of the graphene layer being distinct from the first region of the graphene layer; wherein an energy ba rri er is between the semiconductor layer and the graphene Page 3 Application No. 14/328,339 Attorney Docket No. 2557S I -002182-US layer.
The graphene transistor of claim 10, wherein the insulating thin film has a thickness in a range of about 1 nm to about 4 nm.
The graphene transistor of claim 10, wherein the insulating thin film includes at least one of A₁₂ 0 3, Hf O 2, Ti O 2, and Si₃N4.
The graphene transistor of claim 10, wherein the semiconductor layer includes at least one of silicon, germanium, silicon-germanium, a group I II-V semiconductor, and a group I I -VI semiconductor.
The graphene transistor of claim 10, wherein the semiconductor layer has a thickness in a range of about 1 nm to about 10 nm.
The graphene transistor of claim 10, wherein the graphene transistor is a unipolar transistor having a same polarity as a polarity of an impurity of the semiconductor layer.
The graphene transistor of claim 10, wherein the energy barrier varies according to a gate voltage applied to the gate electrode.
The graphene transistor of claim 10, wherein the graphene layer Page 4 Application No. 14/328,339 Attorney Docket No. 2557S I -002182-US includes between 1 layer and 4 layers of graphene. *** END CLAIM LISTING *** Page
Layer stacks claimed or described, ordered top of device to substrate.
graphene transistor having tunable barrier (substrate-based)
graphene transistor having tunable barrier (back-gate, top semiconductor layer)
Materials described outside the worked examples.
graphene
insulating thin film
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic cross-sectional view of a graphene transistor having a tunable barrier according to example embodiments; [0020]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–30 nm | — |
Thickness | 1–4 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,318,556Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a graphene transistor having a tunable barrier according to example embodiments; [0020]
FIG. 2 is an energy band diagram of an n-type graphene transistor without an insulating thin film according to example embodiments; [0021]
FIGS. 3A and 3B are energy band diagrams for explaining an operation of the n-type graphene transistor of
FIG. 4 is an energy band diagram of a p-type graphene transistor without an insulating thin film according to example embodiments; [0023]
FIGS. 5A and 5B are energy band diagrams for explaining an operation of the p-type graphene transistor of
FIG. 6 is a schematic cross-sectional view of a graphene transistor having a tunable barrier according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene transistor having a tunable barrier comprising: a semiconductor substrate; an insulating thin film on the semiconductor substrate; a graphene layer on the insulating thin film; a first electrode connected to an end of the graphene layer; a second electrode, separate from an other end of the graphene layer, directly contacting the semiconductor substrate; a gate insulating layer covering at least a portion of the graphene layer; and a gate electrode on the gate insulating layer, and an insulating layer between the graphene layer and the insulating thin film at a location corresponding to the first electrode; wherein an energy barrier is between the semiconductor substrate and the graphene layer.
The graphene transistor of claim 1, wherein the insulating thin film has a thickness in a range of about 1 nm to about 4 nm.
The graphene transistor of claim 1, wherein the insulating thin film includes at least one of A₁₂ 0 3, Hf O 2, Ti O 2, and Si₃N4.
The graphene transistor of claim 1, wherein the semiconductor substrate includes at least one of silicon, germanium, silicon-germanium, a group I II-V Page 2 Application No. 14/328,339 Attorney Docket No. 2557 SI -002182-US semiconductor, and a group I I -VI semiconductor.
The graphene transistor of claim 1, wherein a distance between the graphene layer and the second electrode is in a range of about 1 n m to about 30 n m.
The graphene transistor of claim 1, wherein the graphene layer includes between 1 layer and 4 layers of graphene.
The graphene transistor of claim 1, wherein the graphene layer is separate from the second electrode.
canceled
The graphene transistor of c la im 1, wherein the graphene transistor is a unipolar transistor having a same polarity as a polarity of an impurity of the semiconductor substrate.
The graphene transistor of c la im 1, wherein the energy barrier varies according to a gate voltage applied to the gate electrode.
A graphene transistor having a tunable ba rri er comprising: a back gate substrate; a gate insulating layer on the back gate substrate; a graphene layer on the gate insulating layer; a first electrode on a first region of the graphene layer; and a semiconductor layer, an insulating thin film and a second electrode stacked on a second region of the graphene layer, the second region of the graphene layer being distinct from the first region of the graphene layer; wherein an energy ba rri er is between the semiconductor layer and the graphene Page 3 Application No. 14/328,339 Attorney Docket No. 2557S I -002182-US layer.
The graphene transistor of claim 10, wherein the insulating thin film has a thickness in a range of about 1 nm to about 4 nm.
The graphene transistor of claim 10, wherein the insulating thin film includes at least one of A₁₂ 0 3, Hf O 2, Ti O 2, and Si₃N4.
The graphene transistor of claim 10, wherein the semiconductor layer includes at least one of silicon, germanium, silicon-germanium, a group I II-V semiconductor, and a group I I -VI semiconductor.
The graphene transistor of claim 10, wherein the semiconductor layer has a thickness in a range of about 1 nm to about 10 nm.
The graphene transistor of claim 10, wherein the graphene transistor is a unipolar transistor having a same polarity as a polarity of an impurity of the semiconductor layer.
The graphene transistor of claim 10, wherein the energy barrier varies according to a gate voltage applied to the gate electrode.
The graphene transistor of claim 10, wherein the graphene layer Page 4 Application No. 14/328,339 Attorney Docket No. 2557S I -002182-US includes between 1 layer and 4 layers of graphene. *** END CLAIM LISTING *** Page
Layer stacks claimed or described, ordered top of device to substrate.
graphene transistor having tunable barrier (substrate-based)
graphene transistor having tunable barrier (back-gate, top semiconductor layer)
Materials described outside the worked examples.
graphene
insulating thin film
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic cross-sectional view of a graphene transistor having a tunable barrier according to example embodiments; [0020]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–30 nm | — |
Thickness | 1–4 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,318,556Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a graphene transistor having a tunable barrier according to example embodiments; [0020]
FIG. 2 is an energy band diagram of an n-type graphene transistor without an insulating thin film according to example embodiments; [0021]
FIGS. 3A and 3B are energy band diagrams for explaining an operation of the n-type graphene transistor of
FIG. 4 is an energy band diagram of a p-type graphene transistor without an insulating thin film according to example embodiments; [0023]
FIGS. 5A and 5B are energy band diagrams for explaining an operation of the p-type graphene transistor of
FIG. 6 is a schematic cross-sectional view of a graphene transistor having a tunable barrier according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene transistor having a tunable barrier comprising: a semiconductor substrate; an insulating thin film on the semiconductor substrate; a graphene layer on the insulating thin film; a first electrode connected to an end of the graphene layer; a second electrode, separate from an other end of the graphene layer, directly contacting the semiconductor substrate; a gate insulating layer covering at least a portion of the graphene layer; and a gate electrode on the gate insulating layer, and an insulating layer between the graphene layer and the insulating thin film at a location corresponding to the first electrode; wherein an energy barrier is between the semiconductor substrate and the graphene layer.
The graphene transistor of claim 1, wherein the insulating thin film has a thickness in a range of about 1 nm to about 4 nm.
The graphene transistor of claim 1, wherein the insulating thin film includes at least one of A₁₂ 0 3, Hf O 2, Ti O 2, and Si₃N4.
The graphene transistor of claim 1, wherein the semiconductor substrate includes at least one of silicon, germanium, silicon-germanium, a group I II-V Page 2 Application No. 14/328,339 Attorney Docket No. 2557 SI -002182-US semiconductor, and a group I I -VI semiconductor.
The graphene transistor of claim 1, wherein a distance between the graphene layer and the second electrode is in a range of about 1 n m to about 30 n m.
The graphene transistor of claim 1, wherein the graphene layer includes between 1 layer and 4 layers of graphene.
The graphene transistor of claim 1, wherein the graphene layer is separate from the second electrode.
canceled
The graphene transistor of c la im 1, wherein the graphene transistor is a unipolar transistor having a same polarity as a polarity of an impurity of the semiconductor substrate.
The graphene transistor of c la im 1, wherein the energy barrier varies according to a gate voltage applied to the gate electrode.
A graphene transistor having a tunable ba rri er comprising: a back gate substrate; a gate insulating layer on the back gate substrate; a graphene layer on the gate insulating layer; a first electrode on a first region of the graphene layer; and a semiconductor layer, an insulating thin film and a second electrode stacked on a second region of the graphene layer, the second region of the graphene layer being distinct from the first region of the graphene layer; wherein an energy ba rri er is between the semiconductor layer and the graphene Page 3 Application No. 14/328,339 Attorney Docket No. 2557S I -002182-US layer.
The graphene transistor of claim 10, wherein the insulating thin film has a thickness in a range of about 1 nm to about 4 nm.
The graphene transistor of claim 10, wherein the insulating thin film includes at least one of A₁₂ 0 3, Hf O 2, Ti O 2, and Si₃N4.
The graphene transistor of claim 10, wherein the semiconductor layer includes at least one of silicon, germanium, silicon-germanium, a group I II-V semiconductor, and a group I I -VI semiconductor.
The graphene transistor of claim 10, wherein the semiconductor layer has a thickness in a range of about 1 nm to about 10 nm.
The graphene transistor of claim 10, wherein the graphene transistor is a unipolar transistor having a same polarity as a polarity of an impurity of the semiconductor layer.
The graphene transistor of claim 10, wherein the energy barrier varies according to a gate voltage applied to the gate electrode.
The graphene transistor of claim 10, wherein the graphene layer Page 4 Application No. 14/328,339 Attorney Docket No. 2557S I -002182-US includes between 1 layer and 4 layers of graphene. *** END CLAIM LISTING *** Page
Layer stacks claimed or described, ordered top of device to substrate.
graphene transistor having tunable barrier (substrate-based)
graphene transistor having tunable barrier (back-gate, top semiconductor layer)
Materials described outside the worked examples.
graphene
insulating thin film
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic cross-sectional view of a graphene transistor having a tunable barrier according to example embodiments; [0020]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–30 nm | — |
Thickness | 1–4 nm |
Related documents with shared materials, methods, properties, or citations.
Al₂O₃
HfO₂
TiO₂
Si₃N₄
semiconductor substrate
semiconductor layer
FIG. 2 is an energy band diagram of an n-type graphene transistor without an insulating thin film according to example embodiments; [0021]
FIGS. 3A and 3B are energy band diagrams for explaining an operation of the n-type graphene transistor of
FIG. 4 is an energy band diagram of a p-type graphene transistor without an insulating thin film according to example embodiments; [0023]
FIGS. 5A and 5B are energy band diagrams for explaining an operation of the p-type graphene transistor of
FIG. 6 is a schematic cross-sectional view of a graphene transistor having a tunable barrier according to example embodiments.
| — |
Thickness | 1–10 nm | — |
Thickness | ≥ 4 nm | — |
Al₂O₃
HfO₂
TiO₂
Si₃N₄
semiconductor substrate
semiconductor layer
FIG. 2 is an energy band diagram of an n-type graphene transistor without an insulating thin film according to example embodiments; [0021]
FIGS. 3A and 3B are energy band diagrams for explaining an operation of the n-type graphene transistor of
FIG. 4 is an energy band diagram of a p-type graphene transistor without an insulating thin film according to example embodiments; [0023]
FIGS. 5A and 5B are energy band diagrams for explaining an operation of the p-type graphene transistor of
FIG. 6 is a schematic cross-sectional view of a graphene transistor having a tunable barrier according to example embodiments.
| — |
Thickness | 1–10 nm | — |
Thickness | ≥ 4 nm | — |
Al₂O₃
HfO₂
TiO₂
Si₃N₄
semiconductor substrate
semiconductor layer
FIG. 2 is an energy band diagram of an n-type graphene transistor without an insulating thin film according to example embodiments; [0021]
FIGS. 3A and 3B are energy band diagrams for explaining an operation of the n-type graphene transistor of
FIG. 4 is an energy band diagram of a p-type graphene transistor without an insulating thin film according to example embodiments; [0023]
FIGS. 5A and 5B are energy band diagrams for explaining an operation of the p-type graphene transistor of
FIG. 6 is a schematic cross-sectional view of a graphene transistor having a tunable barrier according to example embodiments.
| — |
Thickness | 1–10 nm | — |
Thickness | ≥ 4 nm | — |
Al₂O₃
HfO₂
TiO₂
Si₃N₄
semiconductor substrate
semiconductor layer
FIG. 2 is an energy band diagram of an n-type graphene transistor without an insulating thin film according to example embodiments; [0021]
FIGS. 3A and 3B are energy band diagrams for explaining an operation of the n-type graphene transistor of
FIG. 4 is an energy band diagram of a p-type graphene transistor without an insulating thin film according to example embodiments; [0023]
FIGS. 5A and 5B are energy band diagrams for explaining an operation of the p-type graphene transistor of
FIG. 6 is a schematic cross-sectional view of a graphene transistor having a tunable barrier according to example embodiments.
| — |
Thickness | 1–10 nm | — |
Thickness | ≥ 4 nm | — |