Patent
US 9,368,599GRAPHENE/NANOSTRUCTURE FET WITH SELF-ALIGNED CONTACT AND GATE
Josephine Chang
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,368,599Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an embodiment of a method of fabricating a graphene/nanostructure FET with a self-aligned contact and gate. [0014] Fig. 2A illustrates an …
FIG. 2B illustrates a top view of an embodiment of a deposited channel material comprising nanostructures on a substrate. [0016]
FIG. 3 illustrates an embodiment of the device of
FIG. 4 illustrates an embodiment of the device of
FIG. 5 illustrates an embodiment of the device of
FIG. 6 illustrates an embodiment of the device of
FIG. 7 illustrates an embodiment of the device of
FIG. 8 illustrates an embodiment of the device of
FIG. 9B illustrates a top view of an embodiment of a graphene/nanostructure FET with a self-aligned contact and gate comprising a nanostructure channel …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a field effect transistor (FET), the method comprising: depositing a channel material on an insulator layer of a substrate, the insulator layer having a substantially unifo rm thickness across a semiconductor layer of the substrate, the channel material comprises a plurality of carbon nanotubes configured in a nonparallel arrangement; forming a gate over a first portion of the carbon nanotube channel material; forming spacers, having substantially vertical sidewalls, on and in contact with a second portion of the carbon nanotube channel material adjacent to the gate, the second portion of the carbon nanotube channel material including undoped carbon nanotube channel material; depositing a layer of contact material over the carbon nanotube channel material, gate, spacers, the substantially vertical sidewalls of the spacers, and the insulator layer of the substrate, such that a portion of the layer of contact material conforms to, and is in contact with the substantially vertical sidewalls of the spacers; depositing a layer of dielectric material over the layer of contact material, the layer of dielectric material being deposited using a directional deposition process that deposits the layer of dielectric material on substantially horizontal portions of the contact material without depositing the dielectric material on substantially vertical portions of the contact material partially defined by the substantially vertical sidewalls of the spacers; removing a portion of the layer of dielectric material and a portion of the layer of contact material to expose the gate; recessing a portion of the layer of contact material located adjacent to the spacers to exp ose at least a p ortion of a sidewall of the s p acers; removing the dielectric material; and patterning the layer of contact material to form a self-aligned contact for the FET, the self-aligned contact being disposed directly on a source region and a drain region of the FET, the source region and the drain region comprising any portion of the carbon nanotube channel material not covered by the gate or the spacers, wherein the patterning comprises removing any portion of the layer of contact material that is not in contact with the FET regions of the substrate such that a sidewall end portion of the carbon nanotube channel material is covered by the remaining portion of the layer of contact material.
The method of claim 1, wherein the spacers comprise one of a nitride and an oxide.
The method of claim 1, wherein the substrate insulator layer comprises an oxide layer over a silicon layer, and the channel material is deposited on the oxide layer.
The method of claim 1, wherein the contact material comprises one of a carbon and silicon.
The method of claim 1, wherein the dielectric material comprises a material selected such that the contact material may be removed without removing the dielectric material.
The method of claim 1, wherein the dielectric material comprises high density plasma oxide, and the contact material comprises carbon.
The method of claim 1, wherein removing a portion of the dielectric material and a portion of the contact material to expose the top of the gate comprises chemical mechanical polishing (CMP).
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Layer stacks claimed or described, ordered top of device to substrate.
carbon nanotube field-effect transistor with self-aligned contact and gate
Materials described outside the worked examples.
carbon nanotubes
carbon
C
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an embodiment of a method of fabricating a graphene/nanostructure FET with a self-aligned contact and gate. [0014] Fig. 2A illustrates an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 200000 cm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,368,599Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an embodiment of a method of fabricating a graphene/nanostructure FET with a self-aligned contact and gate. [0014] Fig. 2A illustrates an …
FIG. 2B illustrates a top view of an embodiment of a deposited channel material comprising nanostructures on a substrate. [0016]
FIG. 3 illustrates an embodiment of the device of
FIG. 4 illustrates an embodiment of the device of
FIG. 5 illustrates an embodiment of the device of
FIG. 6 illustrates an embodiment of the device of
FIG. 7 illustrates an embodiment of the device of
FIG. 8 illustrates an embodiment of the device of
FIG. 9B illustrates a top view of an embodiment of a graphene/nanostructure FET with a self-aligned contact and gate comprising a nanostructure channel …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a field effect transistor (FET), the method comprising: depositing a channel material on an insulator layer of a substrate, the insulator layer having a substantially unifo rm thickness across a semiconductor layer of the substrate, the channel material comprises a plurality of carbon nanotubes configured in a nonparallel arrangement; forming a gate over a first portion of the carbon nanotube channel material; forming spacers, having substantially vertical sidewalls, on and in contact with a second portion of the carbon nanotube channel material adjacent to the gate, the second portion of the carbon nanotube channel material including undoped carbon nanotube channel material; depositing a layer of contact material over the carbon nanotube channel material, gate, spacers, the substantially vertical sidewalls of the spacers, and the insulator layer of the substrate, such that a portion of the layer of contact material conforms to, and is in contact with the substantially vertical sidewalls of the spacers; depositing a layer of dielectric material over the layer of contact material, the layer of dielectric material being deposited using a directional deposition process that deposits the layer of dielectric material on substantially horizontal portions of the contact material without depositing the dielectric material on substantially vertical portions of the contact material partially defined by the substantially vertical sidewalls of the spacers; removing a portion of the layer of dielectric material and a portion of the layer of contact material to expose the gate; recessing a portion of the layer of contact material located adjacent to the spacers to exp ose at least a p ortion of a sidewall of the s p acers; removing the dielectric material; and patterning the layer of contact material to form a self-aligned contact for the FET, the self-aligned contact being disposed directly on a source region and a drain region of the FET, the source region and the drain region comprising any portion of the carbon nanotube channel material not covered by the gate or the spacers, wherein the patterning comprises removing any portion of the layer of contact material that is not in contact with the FET regions of the substrate such that a sidewall end portion of the carbon nanotube channel material is covered by the remaining portion of the layer of contact material.
The method of claim 1, wherein the spacers comprise one of a nitride and an oxide.
The method of claim 1, wherein the substrate insulator layer comprises an oxide layer over a silicon layer, and the channel material is deposited on the oxide layer.
The method of claim 1, wherein the contact material comprises one of a carbon and silicon.
The method of claim 1, wherein the dielectric material comprises a material selected such that the contact material may be removed without removing the dielectric material.
The method of claim 1, wherein the dielectric material comprises high density plasma oxide, and the contact material comprises carbon.
The method of claim 1, wherein removing a portion of the dielectric material and a portion of the contact material to expose the top of the gate comprises chemical mechanical polishing (CMP).
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Layer stacks claimed or described, ordered top of device to substrate.
carbon nanotube field-effect transistor with self-aligned contact and gate
Materials described outside the worked examples.
carbon nanotubes
carbon
C
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an embodiment of a method of fabricating a graphene/nanostructure FET with a self-aligned contact and gate. [0014] Fig. 2A illustrates an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 200000 cm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,368,599Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an embodiment of a method of fabricating a graphene/nanostructure FET with a self-aligned contact and gate. [0014] Fig. 2A illustrates an …
FIG. 2B illustrates a top view of an embodiment of a deposited channel material comprising nanostructures on a substrate. [0016]
FIG. 3 illustrates an embodiment of the device of
FIG. 4 illustrates an embodiment of the device of
FIG. 5 illustrates an embodiment of the device of
FIG. 6 illustrates an embodiment of the device of
FIG. 7 illustrates an embodiment of the device of
FIG. 8 illustrates an embodiment of the device of
FIG. 9B illustrates a top view of an embodiment of a graphene/nanostructure FET with a self-aligned contact and gate comprising a nanostructure channel …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a field effect transistor (FET), the method comprising: depositing a channel material on an insulator layer of a substrate, the insulator layer having a substantially unifo rm thickness across a semiconductor layer of the substrate, the channel material comprises a plurality of carbon nanotubes configured in a nonparallel arrangement; forming a gate over a first portion of the carbon nanotube channel material; forming spacers, having substantially vertical sidewalls, on and in contact with a second portion of the carbon nanotube channel material adjacent to the gate, the second portion of the carbon nanotube channel material including undoped carbon nanotube channel material; depositing a layer of contact material over the carbon nanotube channel material, gate, spacers, the substantially vertical sidewalls of the spacers, and the insulator layer of the substrate, such that a portion of the layer of contact material conforms to, and is in contact with the substantially vertical sidewalls of the spacers; depositing a layer of dielectric material over the layer of contact material, the layer of dielectric material being deposited using a directional deposition process that deposits the layer of dielectric material on substantially horizontal portions of the contact material without depositing the dielectric material on substantially vertical portions of the contact material partially defined by the substantially vertical sidewalls of the spacers; removing a portion of the layer of dielectric material and a portion of the layer of contact material to expose the gate; recessing a portion of the layer of contact material located adjacent to the spacers to exp ose at least a p ortion of a sidewall of the s p acers; removing the dielectric material; and patterning the layer of contact material to form a self-aligned contact for the FET, the self-aligned contact being disposed directly on a source region and a drain region of the FET, the source region and the drain region comprising any portion of the carbon nanotube channel material not covered by the gate or the spacers, wherein the patterning comprises removing any portion of the layer of contact material that is not in contact with the FET regions of the substrate such that a sidewall end portion of the carbon nanotube channel material is covered by the remaining portion of the layer of contact material.
The method of claim 1, wherein the spacers comprise one of a nitride and an oxide.
The method of claim 1, wherein the substrate insulator layer comprises an oxide layer over a silicon layer, and the channel material is deposited on the oxide layer.
The method of claim 1, wherein the contact material comprises one of a carbon and silicon.
The method of claim 1, wherein the dielectric material comprises a material selected such that the contact material may be removed without removing the dielectric material.
The method of claim 1, wherein the dielectric material comprises high density plasma oxide, and the contact material comprises carbon.
The method of claim 1, wherein removing a portion of the dielectric material and a portion of the contact material to expose the top of the gate comprises chemical mechanical polishing (CMP).
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Layer stacks claimed or described, ordered top of device to substrate.
carbon nanotube field-effect transistor with self-aligned contact and gate
Materials described outside the worked examples.
carbon nanotubes
carbon
C
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an embodiment of a method of fabricating a graphene/nanostructure FET with a self-aligned contact and gate. [0014] Fig. 2A illustrates an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 200000 cm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,368,599Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an embodiment of a method of fabricating a graphene/nanostructure FET with a self-aligned contact and gate. [0014] Fig. 2A illustrates an …
FIG. 2B illustrates a top view of an embodiment of a deposited channel material comprising nanostructures on a substrate. [0016]
FIG. 3 illustrates an embodiment of the device of
FIG. 4 illustrates an embodiment of the device of
FIG. 5 illustrates an embodiment of the device of
FIG. 6 illustrates an embodiment of the device of
FIG. 7 illustrates an embodiment of the device of
FIG. 8 illustrates an embodiment of the device of
FIG. 9B illustrates a top view of an embodiment of a graphene/nanostructure FET with a self-aligned contact and gate comprising a nanostructure channel …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a field effect transistor (FET), the method comprising: depositing a channel material on an insulator layer of a substrate, the insulator layer having a substantially unifo rm thickness across a semiconductor layer of the substrate, the channel material comprises a plurality of carbon nanotubes configured in a nonparallel arrangement; forming a gate over a first portion of the carbon nanotube channel material; forming spacers, having substantially vertical sidewalls, on and in contact with a second portion of the carbon nanotube channel material adjacent to the gate, the second portion of the carbon nanotube channel material including undoped carbon nanotube channel material; depositing a layer of contact material over the carbon nanotube channel material, gate, spacers, the substantially vertical sidewalls of the spacers, and the insulator layer of the substrate, such that a portion of the layer of contact material conforms to, and is in contact with the substantially vertical sidewalls of the spacers; depositing a layer of dielectric material over the layer of contact material, the layer of dielectric material being deposited using a directional deposition process that deposits the layer of dielectric material on substantially horizontal portions of the contact material without depositing the dielectric material on substantially vertical portions of the contact material partially defined by the substantially vertical sidewalls of the spacers; removing a portion of the layer of dielectric material and a portion of the layer of contact material to expose the gate; recessing a portion of the layer of contact material located adjacent to the spacers to exp ose at least a p ortion of a sidewall of the s p acers; removing the dielectric material; and patterning the layer of contact material to form a self-aligned contact for the FET, the self-aligned contact being disposed directly on a source region and a drain region of the FET, the source region and the drain region comprising any portion of the carbon nanotube channel material not covered by the gate or the spacers, wherein the patterning comprises removing any portion of the layer of contact material that is not in contact with the FET regions of the substrate such that a sidewall end portion of the carbon nanotube channel material is covered by the remaining portion of the layer of contact material.
The method of claim 1, wherein the spacers comprise one of a nitride and an oxide.
The method of claim 1, wherein the substrate insulator layer comprises an oxide layer over a silicon layer, and the channel material is deposited on the oxide layer.
The method of claim 1, wherein the contact material comprises one of a carbon and silicon.
The method of claim 1, wherein the dielectric material comprises a material selected such that the contact material may be removed without removing the dielectric material.
The method of claim 1, wherein the dielectric material comprises high density plasma oxide, and the contact material comprises carbon.
The method of claim 1, wherein removing a portion of the dielectric material and a portion of the contact material to expose the top of the gate comprises chemical mechanical polishing (CMP).
canceled
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canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
carbon nanotube field-effect transistor with self-aligned contact and gate
Materials described outside the worked examples.
carbon nanotubes
carbon
C
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an embodiment of a method of fabricating a graphene/nanostructure FET with a self-aligned contact and gate. [0014] Fig. 2A illustrates an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 200000 cm | — |
Related documents with shared materials, methods, properties, or citations.
dielectric material
insulator layer
nitride
oxide
oxide layer
silicon
Si
metal carbide
metal silicide
metal layer
high density plasma oxide
graphene
semiconductor nanowires
hafnium oxide
HfO₂
titanium nitride
TiN
tungsten
W
silicon nitride
SiN
silicon oxide
SiO₂
FIG. 9B illustrates a top view of an embodiment of a graphene/nanostructure FET with a self-aligned contact and gate comprising a nanostructure channel …
dielectric material
insulator layer
nitride
oxide
oxide layer
silicon
Si
metal carbide
metal silicide
metal layer
high density plasma oxide
graphene
semiconductor nanowires
hafnium oxide
HfO₂
titanium nitride
TiN
tungsten
W
silicon nitride
SiN
silicon oxide
SiO₂
FIG. 9B illustrates a top view of an embodiment of a graphene/nanostructure FET with a self-aligned contact and gate comprising a nanostructure channel …
dielectric material
insulator layer
nitride
oxide
oxide layer
silicon
Si
metal carbide
metal silicide
metal layer
high density plasma oxide
graphene
semiconductor nanowires
hafnium oxide
HfO₂
titanium nitride
TiN
tungsten
W
silicon nitride
SiN
silicon oxide
SiO₂
FIG. 9B illustrates a top view of an embodiment of a graphene/nanostructure FET with a self-aligned contact and gate comprising a nanostructure channel …
dielectric material
insulator layer
nitride
oxide
oxide layer
silicon
Si
metal carbide
metal silicide
metal layer
high density plasma oxide
graphene
semiconductor nanowires
hafnium oxide
HfO₂
titanium nitride
TiN
tungsten
W
silicon nitride
SiN
silicon oxide
SiO₂
FIG. 9B illustrates a top view of an embodiment of a graphene/nanostructure FET with a self-aligned contact and gate comprising a nanostructure channel …