Patent
US 8,987,780GRAPHENE CAPPED HEMT DEVICE
John H. Zhang
US
Copyright © 2026 Matter42. All rights reserved.
Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a side view of a conventional high electron mobility transistor (HEMT) device, including graphs of energy levels and electron concentrations associated with a generic heterostructure, according to the prior art. 4
Figure 2A is a pictorial view of a model of the molecular structure of a graphene crystalline sheet, according to the prior art.
Figure 2B shows a series of prior art bar graphs comparing mechanical, electrical, and thermal properties of graphene with those of other 5 materials.
Figure 3 is a cross-sectional view of a flawed AIGaN/GaN HEMT device that exhibits cracking under high-frequency operation, according to the prior art.
Figure 4 is a cross section of a prior art AIGaN/GaN HEMT device 10 that includes a multi-layer cap to reduce the cracks shown in
Figure 5 is a high-level flow diagram summarizing a processing sequence for fabricating a graphene capped HEMT device as described herein, according to two alternative embodiments. 15
Figure 6A is a process flow diagram showing a detailed sequence of processing steps that can be used to form a film stack for the graphene-capped HEMT as described herein, according to an exemplary embodiment.
Figure 6B is a cross-sectional view of the film stack formed by the processing steps shown in
Figure 6 C is a pictorial view of molecular structure of a hexagonal boron nitride (h-BN) crystalline film, according to the prior art.
Figure 7A is a process flow diagram showing a sequence of process steps that can be used to fabricate a graphene-capped HEMT as described herein, according to an exemplary embodiment. 25
Figures 7B-7D are cross-sectional views illustrating fabrication of the transistor graphene-capped HEMT in accordance with the exemplary process flow shown in
Figure 8A is a process flow diagram showing a sequence of process steps that can be used to form metal source, drain, and gate contacts of a 5 graphene-capped HEMT device as described herein, according to an exemplary embodiment.
Figures 8B-8 C are cross-sectional views illustrating fabrication of the metal source, drain, and gate contacts of a graphene-capped HEMT device in 5 accordance with the exemplary process flow shown in
Figure 9 is a cross-sectional view of a completed graphene-capped HEMT device as described herein, according to an exemplary embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A high electron mobility transistor (HEM T), comprising: a substrate; a heterostructure formed by top and bottom compound semiconductor layers sequentially deposited over the substrate; a first graphene layer formed below the bottom compound semiconductor layer; a second graphene layer formed above the top compound semiconductor layer; source and drain contacts electrically coupled to the top compound semiconductor layer; and a metal gate that modifies energy bands within the heterostructure in response to a voltage applied to the gate.
The HEMT of claim 1, further comprising one or more adhesion layers in contact with the first or second graphene layers.
The HEMT of claim 1 wherein the substrate includes silicon covered with silicon dioxide. 2 SVG 13907752.04-24-2014.HUEIN₈RNPXXIFW3.CLM16785934.1.300.155.1423.250.svg 0.317 3.743 Graph Black and white
The HEM T of claim 1 wherein the substrate includes silicon covered with silicon carbide.
The HEM T of claim 1 wherein the heterostructure includes one or more of GaN, A I N, InP, AlGaN, GaAs, AlGaAs, InGaN, InGaP, InA l As, InGaAs, AlGaSb, Al Sb, or InAs.
The HEM T of claim 1 wherein the metal gate includes one or more of Ni, Ti, Pt, Al, Au, Cu, Ag, W, or combinations thereof.
The HEMT of claim 1 wherein the metal gate includes a liner material made of titanium or titanium nitride (TiN).
The HEMT of claim 1 wherein a switching speed of the HEMT exceeds 200 GHz. 11-22
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene capped high electron mobility transistor (HEMT)
Materials described outside the worked examples.
graphene (first layer)
graphene (second layer)
compound semiconductor
adhesion layer
hexagonal boron nitride
h-BN
silicon
Si
silicon dioxide
SiO₂
silicon carbide
SiC
gallium nitride
GaN
aluminum nitride
AlN
indium phosphide
InP
aluminum gallium nitride
AlGaN
gallium arsenide
GaAs
aluminum gallium arsenide
AlGaAs
indium gallium nitride
InGaN
indium gallium phosphide
InGaP
indium aluminum arsenide
InAlAs
indium gallium arsenide
InGaAs
aluminum gallium antimonide
AlGaSb
aluminum antimonide
AlSb
indium arsenide
InAs
metal gate material (Ni, Ti, Pt, Al, Au, Cu, Ag, W)
titanium
Ti
titanium nitride
TiN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a side view of a conventional high electron mobility transistor (HEMT) device, including graphs of energy levels and electron concentrations associated with a generic heterostructure, according to the prior art. 4
Figure 2B shows a series of prior art bar graphs comparing mechanical, electrical, and thermal properties of graphene with those of other 5 materials.
Figures 7B-7D are cross-sectional views illustrating fabrication of the transistor graphene-capped HEMT in accordance with the exemplary process flow shown in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
HEMT switching speed | >200 GHz | — |
Thickness | 1–8 nm | — |
Related documents with shared materials, methods, properties, or citations.
SELF-ALIGNED DOUBLE-GATE GRAPHENE TRANSISTOR
METHODS FOR N-TYPE DOPING OF GRAPHENE, AND N-TYPE-DOPED GRAPHENE COMPOSITIONS
INCORPORATION OF FUNCTIONALIZING MOLECULES IN NANO-PATTERNED EPITAXIAL GRAPHENE ELECTRONICS
SOURCE/DRAIN TECHNOLOGY FOR THE CARBON NANO-TUBE/GRAPHENE CMOS WITH A SINGLE SELF-ALIGNED METAL SILICIDE PROCESS
GRAPHENE FET WITH GRAPHITIC INTERFACE LAYER AT CONTACTS
METHOD TO MODIFY THE CONDUCTIVITY OF GRAPHENE
GRAPHENE FIELD EFFECT TRANSISTOR
Graphene/Nanostructure FET with Self-Aligned Contact and Gate
ACTIVATION OF GRAPHENE BUFFER LAYERS ON SILICON CARBIDE BY ULTRA LOW TEMPERATURE OXIDATION
Graphene-Based Solid State Devices Capable of Emitting Electromagnetic Radiation and Improvements Thereof
METHODS FOR INTEGRATING LEAD AND GRAPHENE GROWTH AND DEVICES FORMED THEREFROM
Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a side view of a conventional high electron mobility transistor (HEMT) device, including graphs of energy levels and electron concentrations associated with a generic heterostructure, according to the prior art. 4
Figure 2A is a pictorial view of a model of the molecular structure of a graphene crystalline sheet, according to the prior art.
Figure 2B shows a series of prior art bar graphs comparing mechanical, electrical, and thermal properties of graphene with those of other 5 materials.
Figure 3 is a cross-sectional view of a flawed AIGaN/GaN HEMT device that exhibits cracking under high-frequency operation, according to the prior art.
Figure 4 is a cross section of a prior art AIGaN/GaN HEMT device 10 that includes a multi-layer cap to reduce the cracks shown in
Figure 5 is a high-level flow diagram summarizing a processing sequence for fabricating a graphene capped HEMT device as described herein, according to two alternative embodiments. 15
Figure 6A is a process flow diagram showing a detailed sequence of processing steps that can be used to form a film stack for the graphene-capped HEMT as described herein, according to an exemplary embodiment.
Figure 6B is a cross-sectional view of the film stack formed by the processing steps shown in
Figure 6 C is a pictorial view of molecular structure of a hexagonal boron nitride (h-BN) crystalline film, according to the prior art.
Figure 7A is a process flow diagram showing a sequence of process steps that can be used to fabricate a graphene-capped HEMT as described herein, according to an exemplary embodiment. 25
Figures 7B-7D are cross-sectional views illustrating fabrication of the transistor graphene-capped HEMT in accordance with the exemplary process flow shown in
Figure 8A is a process flow diagram showing a sequence of process steps that can be used to form metal source, drain, and gate contacts of a 5 graphene-capped HEMT device as described herein, according to an exemplary embodiment.
Figures 8B-8 C are cross-sectional views illustrating fabrication of the metal source, drain, and gate contacts of a graphene-capped HEMT device in 5 accordance with the exemplary process flow shown in
Figure 9 is a cross-sectional view of a completed graphene-capped HEMT device as described herein, according to an exemplary embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A high electron mobility transistor (HEM T), comprising: a substrate; a heterostructure formed by top and bottom compound semiconductor layers sequentially deposited over the substrate; a first graphene layer formed below the bottom compound semiconductor layer; a second graphene layer formed above the top compound semiconductor layer; source and drain contacts electrically coupled to the top compound semiconductor layer; and a metal gate that modifies energy bands within the heterostructure in response to a voltage applied to the gate.
The HEMT of claim 1, further comprising one or more adhesion layers in contact with the first or second graphene layers.
The HEMT of claim 1 wherein the substrate includes silicon covered with silicon dioxide. 2 SVG 13907752.04-24-2014.HUEIN₈RNPXXIFW3.CLM16785934.1.300.155.1423.250.svg 0.317 3.743 Graph Black and white
The HEM T of claim 1 wherein the substrate includes silicon covered with silicon carbide.
The HEM T of claim 1 wherein the heterostructure includes one or more of GaN, A I N, InP, AlGaN, GaAs, AlGaAs, InGaN, InGaP, InA l As, InGaAs, AlGaSb, Al Sb, or InAs.
The HEM T of claim 1 wherein the metal gate includes one or more of Ni, Ti, Pt, Al, Au, Cu, Ag, W, or combinations thereof.
The HEMT of claim 1 wherein the metal gate includes a liner material made of titanium or titanium nitride (TiN).
The HEMT of claim 1 wherein a switching speed of the HEMT exceeds 200 GHz. 11-22
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene capped high electron mobility transistor (HEMT)
Materials described outside the worked examples.
graphene (first layer)
graphene (second layer)
compound semiconductor
adhesion layer
hexagonal boron nitride
h-BN
silicon
Si
silicon dioxide
SiO₂
silicon carbide
SiC
gallium nitride
GaN
aluminum nitride
AlN
indium phosphide
InP
aluminum gallium nitride
AlGaN
gallium arsenide
GaAs
aluminum gallium arsenide
AlGaAs
indium gallium nitride
InGaN
indium gallium phosphide
InGaP
indium aluminum arsenide
InAlAs
indium gallium arsenide
InGaAs
aluminum gallium antimonide
AlGaSb
aluminum antimonide
AlSb
indium arsenide
InAs
metal gate material (Ni, Ti, Pt, Al, Au, Cu, Ag, W)
titanium
Ti
titanium nitride
TiN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a side view of a conventional high electron mobility transistor (HEMT) device, including graphs of energy levels and electron concentrations associated with a generic heterostructure, according to the prior art. 4
Figure 2B shows a series of prior art bar graphs comparing mechanical, electrical, and thermal properties of graphene with those of other 5 materials.
Figures 7B-7D are cross-sectional views illustrating fabrication of the transistor graphene-capped HEMT in accordance with the exemplary process flow shown in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
HEMT switching speed | >200 GHz | — |
Thickness | 1–8 nm | — |
Related documents with shared materials, methods, properties, or citations.
SELF-ALIGNED DOUBLE-GATE GRAPHENE TRANSISTOR
METHODS FOR N-TYPE DOPING OF GRAPHENE, AND N-TYPE-DOPED GRAPHENE COMPOSITIONS
INCORPORATION OF FUNCTIONALIZING MOLECULES IN NANO-PATTERNED EPITAXIAL GRAPHENE ELECTRONICS
SOURCE/DRAIN TECHNOLOGY FOR THE CARBON NANO-TUBE/GRAPHENE CMOS WITH A SINGLE SELF-ALIGNED METAL SILICIDE PROCESS
GRAPHENE FET WITH GRAPHITIC INTERFACE LAYER AT CONTACTS
METHOD TO MODIFY THE CONDUCTIVITY OF GRAPHENE
GRAPHENE FIELD EFFECT TRANSISTOR
Graphene/Nanostructure FET with Self-Aligned Contact and Gate
ACTIVATION OF GRAPHENE BUFFER LAYERS ON SILICON CARBIDE BY ULTRA LOW TEMPERATURE OXIDATION
Graphene-Based Solid State Devices Capable of Emitting Electromagnetic Radiation and Improvements Thereof
METHODS FOR INTEGRATING LEAD AND GRAPHENE GROWTH AND DEVICES FORMED THEREFROM
Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a side view of a conventional high electron mobility transistor (HEMT) device, including graphs of energy levels and electron concentrations associated with a generic heterostructure, according to the prior art. 4
Figure 2A is a pictorial view of a model of the molecular structure of a graphene crystalline sheet, according to the prior art.
Figure 2B shows a series of prior art bar graphs comparing mechanical, electrical, and thermal properties of graphene with those of other 5 materials.
Figure 3 is a cross-sectional view of a flawed AIGaN/GaN HEMT device that exhibits cracking under high-frequency operation, according to the prior art.
Figure 4 is a cross section of a prior art AIGaN/GaN HEMT device 10 that includes a multi-layer cap to reduce the cracks shown in
Figure 5 is a high-level flow diagram summarizing a processing sequence for fabricating a graphene capped HEMT device as described herein, according to two alternative embodiments. 15
Figure 6A is a process flow diagram showing a detailed sequence of processing steps that can be used to form a film stack for the graphene-capped HEMT as described herein, according to an exemplary embodiment.
Figure 6B is a cross-sectional view of the film stack formed by the processing steps shown in
Figure 6 C is a pictorial view of molecular structure of a hexagonal boron nitride (h-BN) crystalline film, according to the prior art.
Figure 7A is a process flow diagram showing a sequence of process steps that can be used to fabricate a graphene-capped HEMT as described herein, according to an exemplary embodiment. 25
Figures 7B-7D are cross-sectional views illustrating fabrication of the transistor graphene-capped HEMT in accordance with the exemplary process flow shown in
Figure 8A is a process flow diagram showing a sequence of process steps that can be used to form metal source, drain, and gate contacts of a 5 graphene-capped HEMT device as described herein, according to an exemplary embodiment.
Figures 8B-8 C are cross-sectional views illustrating fabrication of the metal source, drain, and gate contacts of a graphene-capped HEMT device in 5 accordance with the exemplary process flow shown in
Figure 9 is a cross-sectional view of a completed graphene-capped HEMT device as described herein, according to an exemplary embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A high electron mobility transistor (HEM T), comprising: a substrate; a heterostructure formed by top and bottom compound semiconductor layers sequentially deposited over the substrate; a first graphene layer formed below the bottom compound semiconductor layer; a second graphene layer formed above the top compound semiconductor layer; source and drain contacts electrically coupled to the top compound semiconductor layer; and a metal gate that modifies energy bands within the heterostructure in response to a voltage applied to the gate.
The HEMT of claim 1, further comprising one or more adhesion layers in contact with the first or second graphene layers.
The HEMT of claim 1 wherein the substrate includes silicon covered with silicon dioxide. 2 SVG 13907752.04-24-2014.HUEIN₈RNPXXIFW3.CLM16785934.1.300.155.1423.250.svg 0.317 3.743 Graph Black and white
The HEM T of claim 1 wherein the substrate includes silicon covered with silicon carbide.
The HEM T of claim 1 wherein the heterostructure includes one or more of GaN, A I N, InP, AlGaN, GaAs, AlGaAs, InGaN, InGaP, InA l As, InGaAs, AlGaSb, Al Sb, or InAs.
The HEM T of claim 1 wherein the metal gate includes one or more of Ni, Ti, Pt, Al, Au, Cu, Ag, W, or combinations thereof.
The HEMT of claim 1 wherein the metal gate includes a liner material made of titanium or titanium nitride (TiN).
The HEMT of claim 1 wherein a switching speed of the HEMT exceeds 200 GHz. 11-22
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene capped high electron mobility transistor (HEMT)
Materials described outside the worked examples.
graphene (first layer)
graphene (second layer)
compound semiconductor
adhesion layer
hexagonal boron nitride
h-BN
silicon
Si
silicon dioxide
SiO₂
silicon carbide
SiC
gallium nitride
GaN
aluminum nitride
AlN
indium phosphide
InP
aluminum gallium nitride
AlGaN
gallium arsenide
GaAs
aluminum gallium arsenide
AlGaAs
indium gallium nitride
InGaN
indium gallium phosphide
InGaP
indium aluminum arsenide
InAlAs
indium gallium arsenide
InGaAs
aluminum gallium antimonide
AlGaSb
aluminum antimonide
AlSb
indium arsenide
InAs
metal gate material (Ni, Ti, Pt, Al, Au, Cu, Ag, W)
titanium
Ti
titanium nitride
TiN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a side view of a conventional high electron mobility transistor (HEMT) device, including graphs of energy levels and electron concentrations associated with a generic heterostructure, according to the prior art. 4
Figure 2B shows a series of prior art bar graphs comparing mechanical, electrical, and thermal properties of graphene with those of other 5 materials.
Figures 7B-7D are cross-sectional views illustrating fabrication of the transistor graphene-capped HEMT in accordance with the exemplary process flow shown in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
HEMT switching speed | >200 GHz | — |
Thickness | 1–8 nm | — |
Related documents with shared materials, methods, properties, or citations.
SELF-ALIGNED DOUBLE-GATE GRAPHENE TRANSISTOR
METHODS FOR N-TYPE DOPING OF GRAPHENE, AND N-TYPE-DOPED GRAPHENE COMPOSITIONS
INCORPORATION OF FUNCTIONALIZING MOLECULES IN NANO-PATTERNED EPITAXIAL GRAPHENE ELECTRONICS
SOURCE/DRAIN TECHNOLOGY FOR THE CARBON NANO-TUBE/GRAPHENE CMOS WITH A SINGLE SELF-ALIGNED METAL SILICIDE PROCESS
GRAPHENE FET WITH GRAPHITIC INTERFACE LAYER AT CONTACTS
METHOD TO MODIFY THE CONDUCTIVITY OF GRAPHENE
GRAPHENE FIELD EFFECT TRANSISTOR
Graphene/Nanostructure FET with Self-Aligned Contact and Gate
ACTIVATION OF GRAPHENE BUFFER LAYERS ON SILICON CARBIDE BY ULTRA LOW TEMPERATURE OXIDATION
Graphene-Based Solid State Devices Capable of Emitting Electromagnetic Radiation and Improvements Thereof
METHODS FOR INTEGRATING LEAD AND GRAPHENE GROWTH AND DEVICES FORMED THEREFROM
Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a side view of a conventional high electron mobility transistor (HEMT) device, including graphs of energy levels and electron concentrations associated with a generic heterostructure, according to the prior art. 4
Figure 2A is a pictorial view of a model of the molecular structure of a graphene crystalline sheet, according to the prior art.
Figure 2B shows a series of prior art bar graphs comparing mechanical, electrical, and thermal properties of graphene with those of other 5 materials.
Figure 3 is a cross-sectional view of a flawed AIGaN/GaN HEMT device that exhibits cracking under high-frequency operation, according to the prior art.
Figure 4 is a cross section of a prior art AIGaN/GaN HEMT device 10 that includes a multi-layer cap to reduce the cracks shown in
Figure 5 is a high-level flow diagram summarizing a processing sequence for fabricating a graphene capped HEMT device as described herein, according to two alternative embodiments. 15
Figure 6A is a process flow diagram showing a detailed sequence of processing steps that can be used to form a film stack for the graphene-capped HEMT as described herein, according to an exemplary embodiment.
Figure 6B is a cross-sectional view of the film stack formed by the processing steps shown in
Figure 6 C is a pictorial view of molecular structure of a hexagonal boron nitride (h-BN) crystalline film, according to the prior art.
Figure 7A is a process flow diagram showing a sequence of process steps that can be used to fabricate a graphene-capped HEMT as described herein, according to an exemplary embodiment. 25
Figures 7B-7D are cross-sectional views illustrating fabrication of the transistor graphene-capped HEMT in accordance with the exemplary process flow shown in
Figure 8A is a process flow diagram showing a sequence of process steps that can be used to form metal source, drain, and gate contacts of a 5 graphene-capped HEMT device as described herein, according to an exemplary embodiment.
Figures 8B-8 C are cross-sectional views illustrating fabrication of the metal source, drain, and gate contacts of a graphene-capped HEMT device in 5 accordance with the exemplary process flow shown in
Figure 9 is a cross-sectional view of a completed graphene-capped HEMT device as described herein, according to an exemplary embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A high electron mobility transistor (HEM T), comprising: a substrate; a heterostructure formed by top and bottom compound semiconductor layers sequentially deposited over the substrate; a first graphene layer formed below the bottom compound semiconductor layer; a second graphene layer formed above the top compound semiconductor layer; source and drain contacts electrically coupled to the top compound semiconductor layer; and a metal gate that modifies energy bands within the heterostructure in response to a voltage applied to the gate.
The HEMT of claim 1, further comprising one or more adhesion layers in contact with the first or second graphene layers.
The HEMT of claim 1 wherein the substrate includes silicon covered with silicon dioxide. 2 SVG 13907752.04-24-2014.HUEIN₈RNPXXIFW3.CLM16785934.1.300.155.1423.250.svg 0.317 3.743 Graph Black and white
The HEM T of claim 1 wherein the substrate includes silicon covered with silicon carbide.
The HEM T of claim 1 wherein the heterostructure includes one or more of GaN, A I N, InP, AlGaN, GaAs, AlGaAs, InGaN, InGaP, InA l As, InGaAs, AlGaSb, Al Sb, or InAs.
The HEM T of claim 1 wherein the metal gate includes one or more of Ni, Ti, Pt, Al, Au, Cu, Ag, W, or combinations thereof.
The HEMT of claim 1 wherein the metal gate includes a liner material made of titanium or titanium nitride (TiN).
The HEMT of claim 1 wherein a switching speed of the HEMT exceeds 200 GHz. 11-22
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene capped high electron mobility transistor (HEMT)
Materials described outside the worked examples.
graphene (first layer)
graphene (second layer)
compound semiconductor
adhesion layer
hexagonal boron nitride
h-BN
silicon
Si
silicon dioxide
SiO₂
silicon carbide
SiC
gallium nitride
GaN
aluminum nitride
AlN
indium phosphide
InP
aluminum gallium nitride
AlGaN
gallium arsenide
GaAs
aluminum gallium arsenide
AlGaAs
indium gallium nitride
InGaN
indium gallium phosphide
InGaP
indium aluminum arsenide
InAlAs
indium gallium arsenide
InGaAs
aluminum gallium antimonide
AlGaSb
aluminum antimonide
AlSb
indium arsenide
InAs
metal gate material (Ni, Ti, Pt, Al, Au, Cu, Ag, W)
titanium
Ti
titanium nitride
TiN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a side view of a conventional high electron mobility transistor (HEMT) device, including graphs of energy levels and electron concentrations associated with a generic heterostructure, according to the prior art. 4
Figure 2B shows a series of prior art bar graphs comparing mechanical, electrical, and thermal properties of graphene with those of other 5 materials.
Figures 7B-7D are cross-sectional views illustrating fabrication of the transistor graphene-capped HEMT in accordance with the exemplary process flow shown in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
HEMT switching speed | >200 GHz | — |
Thickness | 1–8 nm | — |
Related documents with shared materials, methods, properties, or citations.
SELF-ALIGNED DOUBLE-GATE GRAPHENE TRANSISTOR
METHODS FOR N-TYPE DOPING OF GRAPHENE, AND N-TYPE-DOPED GRAPHENE COMPOSITIONS
INCORPORATION OF FUNCTIONALIZING MOLECULES IN NANO-PATTERNED EPITAXIAL GRAPHENE ELECTRONICS
SOURCE/DRAIN TECHNOLOGY FOR THE CARBON NANO-TUBE/GRAPHENE CMOS WITH A SINGLE SELF-ALIGNED METAL SILICIDE PROCESS
GRAPHENE FET WITH GRAPHITIC INTERFACE LAYER AT CONTACTS
METHOD TO MODIFY THE CONDUCTIVITY OF GRAPHENE
GRAPHENE FIELD EFFECT TRANSISTOR
Graphene/Nanostructure FET with Self-Aligned Contact and Gate
ACTIVATION OF GRAPHENE BUFFER LAYERS ON SILICON CARBIDE BY ULTRA LOW TEMPERATURE OXIDATION
Graphene-Based Solid State Devices Capable of Emitting Electromagnetic Radiation and Improvements Thereof
METHODS FOR INTEGRATING LEAD AND GRAPHENE GROWTH AND DEVICES FORMED THEREFROM