Patent
US 8,785,911GRAPHENE OR CARBON NANOTUBE DEVICES WITH LOCALIZED BOTTOM GATES AND GATE DIELECTRIC
Zhihong Chen
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,785,911Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-6 illustrate one exemplary embodiment wherein a localized gate dielectric is formed by oxidation (e.g., thermal oxidation). In this particular example, …
FIG. 2 is a cross-sectional diagram illustrating a trench 202 having been patterned in insulator 104. According to an exemplary embodiment, the local bottom …
FIG. 3.
FIG. 4.
FIG. 5.
FIG. 6.
FIG. 7 is a cross-sectional diagram illustrating an alternative embodiment wherein a gate material and a gate dielectric have been deposited into a trench and …
FIG. 8.
FIG. 9. More generally, one may employ a multilayer gate dielectric wherein at least one layer thereof (in this case gate dielectric 704) is selectively …
FIG. 10B is a cross-sectional diagram illustrating a layer of graphene or carbon nanotubes having been formed over at least a portion of the gate dielectric of
FIG. 11.
FIG. 12B is a cross-sectional diagram illustrating an alternative embodiment wherein cavities have been formed extending through the SOI layer, through the BOX …
FIG. 13B is a cross- sectional diagram illustrating cavities 1204 (the deeper cavities) having been filled with a dielectric 1304. The same dielectric may be …
FIG. 14A. According to an exemplary embodiment, gate YO R₉₂₀₁₀₀₄₁₄US₁ 19 dielectric 1406 is an insulating oxide, such as Si O 2 and gate dielectric 1408 is a …
FIG. 15C is a cross-sectional diagram illustrating a layer of graphene or carbon nanotubes having been formed over at least a portion of the multilayer …
FIG. 16 is a cross-sectional diagram illustrating an exemplary layered stack gate configuration according to an embodiment of the present invention. Detailed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device, comprising: a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.
The device of claim 1, wherein the carbon-based nanostructure material comprises a graphene or carbon nanotube layer.
The device of claim 1, wherein the insulator comprises silicon dioxide.
The device of claim 1, wherein the local bottom gate comprises a conductive material selected from the group consisting of doped polycrystalline silicon, doped single-crystal silicon, at least one metal and a layered stack of conductive materials.
The device of claim 1, wherein the local gate dielectric comprises a material selected from the group consisting of an insulating oxide, an insulating nitride, an YO R₉₂₀₁ 0 0414US₁ 24 insulating oxynitride, and combinations comprising at least one of the foregoing materials in a layered configuration.
The device of claim 1, further comprising: a blanket gate dielectric on the local gate dielectric and at least a portion of the insulator.
A method of fabricating a transistor device, comprising the steps of: providing a substrate having an insulator thereon; forming a local bottom gate in a trench in the insulator; forming a local gate dielectric on the bottom gate; forming a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and forming conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.
The method of claim 10, further comprising the step of: etching the trench in the insulator through a patterned resist layer.
YO R₉₂₀₁₀₀₄₁₄US₁ 25 13. The method of claim 10, wherein the step of forming the local gate dielectric on the bottom gate comprises the step of: oxidizing an upper portion of the bottom gate to form an oxide dielectric.
The method of claim 10, further comprising the step of: forming a blanket gate dielectric on the local gate dielectric and at least a portion of the insulator.
A method of fabricating a transistor device, comprising the steps o f: providing a wafer having a layer of electrically conductive material on an insulating layer; forming cavities in the wafer to isolate one or more portions of the conductive material, wherein an isolated portion of the conductive material serves as a local bottom gate of the device; filling the cavities with a dielectric; forming a gate dielectric on the bottom gate; forming a carbon-based nanostructure material over at least a portion of the gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and forming conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.
YO R₉₂₀₁₀₀₄₁₄US₁ 26 17. The method of claim 16, wherein the layer of conductive material comprises a single crystal semiconductor-on-insulator layer and the insulating layer comprises a buried oxide.
The method of claim 16, wherein the layer of conductive material comprises doped polycrystalline silicon.
The method of claim 16, wherein the cavities extend into the insulating layer.
The method of claim 16, wherein the cavities extend through the insulating layer.
The method of claim 16, wherein the gate dielectric formed on the bottom gate is local to the bottom gate.
The method of claim 16, wherein the step of forming the gate dielectric on the bottom gate comprises the step of: blanket depositing a gate dielectric material on the bottom gate and on at least a portion of the dielectric filling the cavities.
The method of claim 16, wherein the step of forming the gate dielectric on the bottom gate comprises the steps of: forming a local gate dielectric on the bottom gate; and forming a blanket gate dielectric on the local gate dielectric and at least a portion of the dielectric filling the cavities.
The method of claim 16, wherein the step of forming the gate dielectric on the bottom gate comprises the step of: oxidizing an upper portion of the bottom gate to form an oxide dielectric.
Layer stacks claimed or described, ordered top of device to substrate.
transistor device with local bottom gate and carbon-based nanostructure channel
Materials described outside the worked examples.
carbon-based nanostructure material
local gate dielectric
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-6 illustrate one exemplary embodiment wherein a localized gate dielectric is formed by oxidation (e.g., thermal oxidation). In this particular example, …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,785,911Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-6 illustrate one exemplary embodiment wherein a localized gate dielectric is formed by oxidation (e.g., thermal oxidation). In this particular example, …
FIG. 2 is a cross-sectional diagram illustrating a trench 202 having been patterned in insulator 104. According to an exemplary embodiment, the local bottom …
FIG. 3.
FIG. 4.
FIG. 5.
FIG. 6.
FIG. 7 is a cross-sectional diagram illustrating an alternative embodiment wherein a gate material and a gate dielectric have been deposited into a trench and …
FIG. 8.
FIG. 9. More generally, one may employ a multilayer gate dielectric wherein at least one layer thereof (in this case gate dielectric 704) is selectively …
FIG. 10B is a cross-sectional diagram illustrating a layer of graphene or carbon nanotubes having been formed over at least a portion of the gate dielectric of
FIG. 11.
FIG. 12B is a cross-sectional diagram illustrating an alternative embodiment wherein cavities have been formed extending through the SOI layer, through the BOX …
FIG. 13B is a cross- sectional diagram illustrating cavities 1204 (the deeper cavities) having been filled with a dielectric 1304. The same dielectric may be …
FIG. 14A. According to an exemplary embodiment, gate YO R₉₂₀₁₀₀₄₁₄US₁ 19 dielectric 1406 is an insulating oxide, such as Si O 2 and gate dielectric 1408 is a …
FIG. 15C is a cross-sectional diagram illustrating a layer of graphene or carbon nanotubes having been formed over at least a portion of the multilayer …
FIG. 16 is a cross-sectional diagram illustrating an exemplary layered stack gate configuration according to an embodiment of the present invention. Detailed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device, comprising: a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.
The device of claim 1, wherein the carbon-based nanostructure material comprises a graphene or carbon nanotube layer.
The device of claim 1, wherein the insulator comprises silicon dioxide.
The device of claim 1, wherein the local bottom gate comprises a conductive material selected from the group consisting of doped polycrystalline silicon, doped single-crystal silicon, at least one metal and a layered stack of conductive materials.
The device of claim 1, wherein the local gate dielectric comprises a material selected from the group consisting of an insulating oxide, an insulating nitride, an YO R₉₂₀₁ 0 0414US₁ 24 insulating oxynitride, and combinations comprising at least one of the foregoing materials in a layered configuration.
The device of claim 1, further comprising: a blanket gate dielectric on the local gate dielectric and at least a portion of the insulator.
A method of fabricating a transistor device, comprising the steps of: providing a substrate having an insulator thereon; forming a local bottom gate in a trench in the insulator; forming a local gate dielectric on the bottom gate; forming a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and forming conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.
The method of claim 10, further comprising the step of: etching the trench in the insulator through a patterned resist layer.
YO R₉₂₀₁₀₀₄₁₄US₁ 25 13. The method of claim 10, wherein the step of forming the local gate dielectric on the bottom gate comprises the step of: oxidizing an upper portion of the bottom gate to form an oxide dielectric.
The method of claim 10, further comprising the step of: forming a blanket gate dielectric on the local gate dielectric and at least a portion of the insulator.
A method of fabricating a transistor device, comprising the steps o f: providing a wafer having a layer of electrically conductive material on an insulating layer; forming cavities in the wafer to isolate one or more portions of the conductive material, wherein an isolated portion of the conductive material serves as a local bottom gate of the device; filling the cavities with a dielectric; forming a gate dielectric on the bottom gate; forming a carbon-based nanostructure material over at least a portion of the gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and forming conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.
YO R₉₂₀₁₀₀₄₁₄US₁ 26 17. The method of claim 16, wherein the layer of conductive material comprises a single crystal semiconductor-on-insulator layer and the insulating layer comprises a buried oxide.
The method of claim 16, wherein the layer of conductive material comprises doped polycrystalline silicon.
The method of claim 16, wherein the cavities extend into the insulating layer.
The method of claim 16, wherein the cavities extend through the insulating layer.
The method of claim 16, wherein the gate dielectric formed on the bottom gate is local to the bottom gate.
The method of claim 16, wherein the step of forming the gate dielectric on the bottom gate comprises the step of: blanket depositing a gate dielectric material on the bottom gate and on at least a portion of the dielectric filling the cavities.
The method of claim 16, wherein the step of forming the gate dielectric on the bottom gate comprises the steps of: forming a local gate dielectric on the bottom gate; and forming a blanket gate dielectric on the local gate dielectric and at least a portion of the dielectric filling the cavities.
The method of claim 16, wherein the step of forming the gate dielectric on the bottom gate comprises the step of: oxidizing an upper portion of the bottom gate to form an oxide dielectric.
Layer stacks claimed or described, ordered top of device to substrate.
transistor device with local bottom gate and carbon-based nanostructure channel
Materials described outside the worked examples.
carbon-based nanostructure material
local gate dielectric
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-6 illustrate one exemplary embodiment wherein a localized gate dielectric is formed by oxidation (e.g., thermal oxidation). In this particular example, …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,785,911Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-6 illustrate one exemplary embodiment wherein a localized gate dielectric is formed by oxidation (e.g., thermal oxidation). In this particular example, …
FIG. 2 is a cross-sectional diagram illustrating a trench 202 having been patterned in insulator 104. According to an exemplary embodiment, the local bottom …
FIG. 3.
FIG. 4.
FIG. 5.
FIG. 6.
FIG. 7 is a cross-sectional diagram illustrating an alternative embodiment wherein a gate material and a gate dielectric have been deposited into a trench and …
FIG. 8.
FIG. 9. More generally, one may employ a multilayer gate dielectric wherein at least one layer thereof (in this case gate dielectric 704) is selectively …
FIG. 10B is a cross-sectional diagram illustrating a layer of graphene or carbon nanotubes having been formed over at least a portion of the gate dielectric of
FIG. 11.
FIG. 12B is a cross-sectional diagram illustrating an alternative embodiment wherein cavities have been formed extending through the SOI layer, through the BOX …
FIG. 13B is a cross- sectional diagram illustrating cavities 1204 (the deeper cavities) having been filled with a dielectric 1304. The same dielectric may be …
FIG. 14A. According to an exemplary embodiment, gate YO R₉₂₀₁₀₀₄₁₄US₁ 19 dielectric 1406 is an insulating oxide, such as Si O 2 and gate dielectric 1408 is a …
FIG. 15C is a cross-sectional diagram illustrating a layer of graphene or carbon nanotubes having been formed over at least a portion of the multilayer …
FIG. 16 is a cross-sectional diagram illustrating an exemplary layered stack gate configuration according to an embodiment of the present invention. Detailed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device, comprising: a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.
The device of claim 1, wherein the carbon-based nanostructure material comprises a graphene or carbon nanotube layer.
The device of claim 1, wherein the insulator comprises silicon dioxide.
The device of claim 1, wherein the local bottom gate comprises a conductive material selected from the group consisting of doped polycrystalline silicon, doped single-crystal silicon, at least one metal and a layered stack of conductive materials.
The device of claim 1, wherein the local gate dielectric comprises a material selected from the group consisting of an insulating oxide, an insulating nitride, an YO R₉₂₀₁ 0 0414US₁ 24 insulating oxynitride, and combinations comprising at least one of the foregoing materials in a layered configuration.
The device of claim 1, further comprising: a blanket gate dielectric on the local gate dielectric and at least a portion of the insulator.
A method of fabricating a transistor device, comprising the steps of: providing a substrate having an insulator thereon; forming a local bottom gate in a trench in the insulator; forming a local gate dielectric on the bottom gate; forming a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and forming conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.
The method of claim 10, further comprising the step of: etching the trench in the insulator through a patterned resist layer.
YO R₉₂₀₁₀₀₄₁₄US₁ 25 13. The method of claim 10, wherein the step of forming the local gate dielectric on the bottom gate comprises the step of: oxidizing an upper portion of the bottom gate to form an oxide dielectric.
The method of claim 10, further comprising the step of: forming a blanket gate dielectric on the local gate dielectric and at least a portion of the insulator.
A method of fabricating a transistor device, comprising the steps o f: providing a wafer having a layer of electrically conductive material on an insulating layer; forming cavities in the wafer to isolate one or more portions of the conductive material, wherein an isolated portion of the conductive material serves as a local bottom gate of the device; filling the cavities with a dielectric; forming a gate dielectric on the bottom gate; forming a carbon-based nanostructure material over at least a portion of the gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and forming conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.
YO R₉₂₀₁₀₀₄₁₄US₁ 26 17. The method of claim 16, wherein the layer of conductive material comprises a single crystal semiconductor-on-insulator layer and the insulating layer comprises a buried oxide.
The method of claim 16, wherein the layer of conductive material comprises doped polycrystalline silicon.
The method of claim 16, wherein the cavities extend into the insulating layer.
The method of claim 16, wherein the cavities extend through the insulating layer.
The method of claim 16, wherein the gate dielectric formed on the bottom gate is local to the bottom gate.
The method of claim 16, wherein the step of forming the gate dielectric on the bottom gate comprises the step of: blanket depositing a gate dielectric material on the bottom gate and on at least a portion of the dielectric filling the cavities.
The method of claim 16, wherein the step of forming the gate dielectric on the bottom gate comprises the steps of: forming a local gate dielectric on the bottom gate; and forming a blanket gate dielectric on the local gate dielectric and at least a portion of the dielectric filling the cavities.
The method of claim 16, wherein the step of forming the gate dielectric on the bottom gate comprises the step of: oxidizing an upper portion of the bottom gate to form an oxide dielectric.
Layer stacks claimed or described, ordered top of device to substrate.
transistor device with local bottom gate and carbon-based nanostructure channel
Materials described outside the worked examples.
carbon-based nanostructure material
local gate dielectric
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-6 illustrate one exemplary embodiment wherein a localized gate dielectric is formed by oxidation (e.g., thermal oxidation). In this particular example, …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,785,911Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-6 illustrate one exemplary embodiment wherein a localized gate dielectric is formed by oxidation (e.g., thermal oxidation). In this particular example, …
FIG. 2 is a cross-sectional diagram illustrating a trench 202 having been patterned in insulator 104. According to an exemplary embodiment, the local bottom …
FIG. 3.
FIG. 4.
FIG. 5.
FIG. 6.
FIG. 7 is a cross-sectional diagram illustrating an alternative embodiment wherein a gate material and a gate dielectric have been deposited into a trench and …
FIG. 8.
FIG. 9. More generally, one may employ a multilayer gate dielectric wherein at least one layer thereof (in this case gate dielectric 704) is selectively …
FIG. 10B is a cross-sectional diagram illustrating a layer of graphene or carbon nanotubes having been formed over at least a portion of the gate dielectric of
FIG. 11.
FIG. 12B is a cross-sectional diagram illustrating an alternative embodiment wherein cavities have been formed extending through the SOI layer, through the BOX …
FIG. 13B is a cross- sectional diagram illustrating cavities 1204 (the deeper cavities) having been filled with a dielectric 1304. The same dielectric may be …
FIG. 14A. According to an exemplary embodiment, gate YO R₉₂₀₁₀₀₄₁₄US₁ 19 dielectric 1406 is an insulating oxide, such as Si O 2 and gate dielectric 1408 is a …
FIG. 15C is a cross-sectional diagram illustrating a layer of graphene or carbon nanotubes having been formed over at least a portion of the multilayer …
FIG. 16 is a cross-sectional diagram illustrating an exemplary layered stack gate configuration according to an embodiment of the present invention. Detailed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device, comprising: a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.
The device of claim 1, wherein the carbon-based nanostructure material comprises a graphene or carbon nanotube layer.
The device of claim 1, wherein the insulator comprises silicon dioxide.
The device of claim 1, wherein the local bottom gate comprises a conductive material selected from the group consisting of doped polycrystalline silicon, doped single-crystal silicon, at least one metal and a layered stack of conductive materials.
The device of claim 1, wherein the local gate dielectric comprises a material selected from the group consisting of an insulating oxide, an insulating nitride, an YO R₉₂₀₁ 0 0414US₁ 24 insulating oxynitride, and combinations comprising at least one of the foregoing materials in a layered configuration.
The device of claim 1, further comprising: a blanket gate dielectric on the local gate dielectric and at least a portion of the insulator.
A method of fabricating a transistor device, comprising the steps of: providing a substrate having an insulator thereon; forming a local bottom gate in a trench in the insulator; forming a local gate dielectric on the bottom gate; forming a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and forming conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.
The method of claim 10, further comprising the step of: etching the trench in the insulator through a patterned resist layer.
YO R₉₂₀₁₀₀₄₁₄US₁ 25 13. The method of claim 10, wherein the step of forming the local gate dielectric on the bottom gate comprises the step of: oxidizing an upper portion of the bottom gate to form an oxide dielectric.
The method of claim 10, further comprising the step of: forming a blanket gate dielectric on the local gate dielectric and at least a portion of the insulator.
A method of fabricating a transistor device, comprising the steps o f: providing a wafer having a layer of electrically conductive material on an insulating layer; forming cavities in the wafer to isolate one or more portions of the conductive material, wherein an isolated portion of the conductive material serves as a local bottom gate of the device; filling the cavities with a dielectric; forming a gate dielectric on the bottom gate; forming a carbon-based nanostructure material over at least a portion of the gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and forming conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.
YO R₉₂₀₁₀₀₄₁₄US₁ 26 17. The method of claim 16, wherein the layer of conductive material comprises a single crystal semiconductor-on-insulator layer and the insulating layer comprises a buried oxide.
The method of claim 16, wherein the layer of conductive material comprises doped polycrystalline silicon.
The method of claim 16, wherein the cavities extend into the insulating layer.
The method of claim 16, wherein the cavities extend through the insulating layer.
The method of claim 16, wherein the gate dielectric formed on the bottom gate is local to the bottom gate.
The method of claim 16, wherein the step of forming the gate dielectric on the bottom gate comprises the step of: blanket depositing a gate dielectric material on the bottom gate and on at least a portion of the dielectric filling the cavities.
The method of claim 16, wherein the step of forming the gate dielectric on the bottom gate comprises the steps of: forming a local gate dielectric on the bottom gate; and forming a blanket gate dielectric on the local gate dielectric and at least a portion of the dielectric filling the cavities.
The method of claim 16, wherein the step of forming the gate dielectric on the bottom gate comprises the step of: oxidizing an upper portion of the bottom gate to form an oxide dielectric.
Layer stacks claimed or described, ordered top of device to substrate.
transistor device with local bottom gate and carbon-based nanostructure channel
Materials described outside the worked examples.
carbon-based nanostructure material
local gate dielectric
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-6 illustrate one exemplary embodiment wherein a localized gate dielectric is formed by oxidation (e.g., thermal oxidation). In this particular example, …
Related documents with shared materials, methods, properties, or citations.
insulator
graphene
carbon nanotube
silicon dioxide
SiO₂
doped polycrystalline silicon
doped single-crystal silicon
layered stack of conductive materials
palladium
Pd
titanium oxide
TiO₂
metal oxide
single crystal semiconductor-on-insulator layer
FIG. 3.
FIG. 7 is a cross-sectional diagram illustrating an alternative embodiment wherein a gate material and a gate dielectric have been deposited into a trench and …
FIG. 11.
GRAPHENE TRANSISTORS WITH SELF-ALIGNED GATES
insulator
graphene
carbon nanotube
silicon dioxide
SiO₂
doped polycrystalline silicon
doped single-crystal silicon
layered stack of conductive materials
palladium
Pd
titanium oxide
TiO₂
metal oxide
single crystal semiconductor-on-insulator layer
FIG. 3.
FIG. 7 is a cross-sectional diagram illustrating an alternative embodiment wherein a gate material and a gate dielectric have been deposited into a trench and …
FIG. 11.
GRAPHENE TRANSISTORS WITH SELF-ALIGNED GATES
insulator
graphene
carbon nanotube
silicon dioxide
SiO₂
doped polycrystalline silicon
doped single-crystal silicon
layered stack of conductive materials
palladium
Pd
titanium oxide
TiO₂
metal oxide
single crystal semiconductor-on-insulator layer
FIG. 3.
FIG. 7 is a cross-sectional diagram illustrating an alternative embodiment wherein a gate material and a gate dielectric have been deposited into a trench and …
FIG. 11.
GRAPHENE TRANSISTORS WITH SELF-ALIGNED GATES
insulator
graphene
carbon nanotube
silicon dioxide
SiO₂
doped polycrystalline silicon
doped single-crystal silicon
layered stack of conductive materials
palladium
Pd
titanium oxide
TiO₂
metal oxide
single crystal semiconductor-on-insulator layer
FIG. 3.
FIG. 7 is a cross-sectional diagram illustrating an alternative embodiment wherein a gate material and a gate dielectric have been deposited into a trench and …
FIG. 11.
GRAPHENE TRANSISTORS WITH SELF-ALIGNED GATES