Patent
US 9,064,776Graphene- and/or carbon nanotube-based radiation-hard transistor devices and fabrication thereof
Yu-Ming Lin
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,064,776Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a three-dimensional diagram illustrating a carbon-based material having been formed (i.e., deposited or grown) on a radiation-hardened calcium …
FIG. 2, contacts 202 are formed on the portions of the carbon-based material that serve as the source and drain regions of the transistor. According to an …
FIG. 3, a layer of a gate dielectric 302 is then deposited over exposed portions of carbon-based material 104 including the portion of carbon-based material …
FIG. 4, a top-gate contact 402 is formed on gate dielectric 302 over the portion of carbon-based material 104 that serves as the channel region of the …
FIG. 5 is a diagram illustrating a cross-sectional cut through the structure of
FIGS. 6-10 illustrate the device fabrication process using a different exemplary radiation-hard substrate configuration, i.e., a Si wafer covered with a …
FIG. 7 is a three-dimensional diagram illustrating a carbon-based material having been formed on the radiation-hard substrate of
FIG. 8, contacts 802 are formed on the portions of the carbon-based material that serve as source and drain regions of the transistor. According to an …
FIG. 9, a layer of a gate dielectric 902 is then deposited over exposed portions of carbon-based material 704 including the portion of carbon-based material …
FIG. 10 is a three-dimensional diagram illustrating a metal top-gate contact having been formed on the gate dielectric over the portion of the carbon-based …
FIGS. 11-14 illustrate the exemplary embodiment described above wherein epitaxial thermally annealed SiC is the radiation hardened material and wherein the …
FIG. 12. As described above, thermally annealing an SiC film at a temperature of from about 1,200 ° C to about 1,600 ° C, e.g., at about 1,250 ° C, for a …
FIG. 13 is a three-dimensional diagram illustrating the radiation-hardened SiC film having been used to grow graphene according to an embodiment of the present …
FIG. 14. [0051] Although illustrative embodiments of the present invention have been described herein, it is to be understood that the invention is not limited …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A radiation-hard transistor, comprising: a radiation-hard substrate, wherein the substrate comprises a silicon wafer covered with a radiation-hard material; a carbon-based material on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon- based material serve as source and drain regions of the transistor; contacts formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor; a gate dielectric disposed over the portion of the carbon-based material that serves as the channel region of the transistor; and a top-gate contact on the gate dielectric. 2-3..
The radiation-hard transistor of claim 1 3, wherein the radiation-hard material comprises a calcium fluoride film.
The radiation-hard transistor of claim 1 3, wherein the radiation-hard material comprises a fluorinated silicon dioxide film.
The radiation-hard transistor of claim 1 3, wherein the radiation-hard material comprises a silicon carbide film.
The radiation-hard transistor of claim 1, wherein the carbon-based material comprises one or more of graphene and carbon nanotubes.
The radiation-hard transistor of claim 1, wherein the gate dielectric comprises aluminum oxide, hafnium oxide, silicon oxide or zirconium oxide.
canceled
canceled
A radiation-hard transistor, comprising: 3 Docket No. Y O R₉₂₀₁₀₀₃₈₈US₂ Customer No. 63919 a radiation-hard substrate, wherein the substrate comprises a calcium fluoride film; a carbon-based material on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon- based material serve as source and drain regions of the transistor; contacts formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor; a gate dielectric disposed over the portion of the carbon-based material that serves as the channel region of the transistor; and a top-gate contact on the gate dielectric. 4
Layer stacks claimed or described, ordered top of device to substrate.
radiation-hard top-gated transistor (Si wafer with radiation-hard material substrate)
radiation-hard top-gated transistor (CaF₂ substrate)
Materials described outside the worked examples.
silicon wafer
Si
carbon-based material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a three-dimensional diagram illustrating a carbon-based material having been formed (i.e., deposited or grown) on a radiation-hardened calcium …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–20 nm | — |
Duration | 3–100 hours |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,064,776Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a three-dimensional diagram illustrating a carbon-based material having been formed (i.e., deposited or grown) on a radiation-hardened calcium …
FIG. 2, contacts 202 are formed on the portions of the carbon-based material that serve as the source and drain regions of the transistor. According to an …
FIG. 3, a layer of a gate dielectric 302 is then deposited over exposed portions of carbon-based material 104 including the portion of carbon-based material …
FIG. 4, a top-gate contact 402 is formed on gate dielectric 302 over the portion of carbon-based material 104 that serves as the channel region of the …
FIG. 5 is a diagram illustrating a cross-sectional cut through the structure of
FIGS. 6-10 illustrate the device fabrication process using a different exemplary radiation-hard substrate configuration, i.e., a Si wafer covered with a …
FIG. 7 is a three-dimensional diagram illustrating a carbon-based material having been formed on the radiation-hard substrate of
FIG. 8, contacts 802 are formed on the portions of the carbon-based material that serve as source and drain regions of the transistor. According to an …
FIG. 9, a layer of a gate dielectric 902 is then deposited over exposed portions of carbon-based material 704 including the portion of carbon-based material …
FIG. 10 is a three-dimensional diagram illustrating a metal top-gate contact having been formed on the gate dielectric over the portion of the carbon-based …
FIGS. 11-14 illustrate the exemplary embodiment described above wherein epitaxial thermally annealed SiC is the radiation hardened material and wherein the …
FIG. 12. As described above, thermally annealing an SiC film at a temperature of from about 1,200 ° C to about 1,600 ° C, e.g., at about 1,250 ° C, for a …
FIG. 13 is a three-dimensional diagram illustrating the radiation-hardened SiC film having been used to grow graphene according to an embodiment of the present …
FIG. 14. [0051] Although illustrative embodiments of the present invention have been described herein, it is to be understood that the invention is not limited …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A radiation-hard transistor, comprising: a radiation-hard substrate, wherein the substrate comprises a silicon wafer covered with a radiation-hard material; a carbon-based material on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon- based material serve as source and drain regions of the transistor; contacts formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor; a gate dielectric disposed over the portion of the carbon-based material that serves as the channel region of the transistor; and a top-gate contact on the gate dielectric. 2-3..
The radiation-hard transistor of claim 1 3, wherein the radiation-hard material comprises a calcium fluoride film.
The radiation-hard transistor of claim 1 3, wherein the radiation-hard material comprises a fluorinated silicon dioxide film.
The radiation-hard transistor of claim 1 3, wherein the radiation-hard material comprises a silicon carbide film.
The radiation-hard transistor of claim 1, wherein the carbon-based material comprises one or more of graphene and carbon nanotubes.
The radiation-hard transistor of claim 1, wherein the gate dielectric comprises aluminum oxide, hafnium oxide, silicon oxide or zirconium oxide.
canceled
canceled
A radiation-hard transistor, comprising: 3 Docket No. Y O R₉₂₀₁₀₀₃₈₈US₂ Customer No. 63919 a radiation-hard substrate, wherein the substrate comprises a calcium fluoride film; a carbon-based material on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon- based material serve as source and drain regions of the transistor; contacts formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor; a gate dielectric disposed over the portion of the carbon-based material that serves as the channel region of the transistor; and a top-gate contact on the gate dielectric. 4
Layer stacks claimed or described, ordered top of device to substrate.
radiation-hard top-gated transistor (Si wafer with radiation-hard material substrate)
radiation-hard top-gated transistor (CaF₂ substrate)
Materials described outside the worked examples.
silicon wafer
Si
carbon-based material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a three-dimensional diagram illustrating a carbon-based material having been formed (i.e., deposited or grown) on a radiation-hardened calcium …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–20 nm | — |
Duration | 3–100 hours |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,064,776Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a three-dimensional diagram illustrating a carbon-based material having been formed (i.e., deposited or grown) on a radiation-hardened calcium …
FIG. 2, contacts 202 are formed on the portions of the carbon-based material that serve as the source and drain regions of the transistor. According to an …
FIG. 3, a layer of a gate dielectric 302 is then deposited over exposed portions of carbon-based material 104 including the portion of carbon-based material …
FIG. 4, a top-gate contact 402 is formed on gate dielectric 302 over the portion of carbon-based material 104 that serves as the channel region of the …
FIG. 5 is a diagram illustrating a cross-sectional cut through the structure of
FIGS. 6-10 illustrate the device fabrication process using a different exemplary radiation-hard substrate configuration, i.e., a Si wafer covered with a …
FIG. 7 is a three-dimensional diagram illustrating a carbon-based material having been formed on the radiation-hard substrate of
FIG. 8, contacts 802 are formed on the portions of the carbon-based material that serve as source and drain regions of the transistor. According to an …
FIG. 9, a layer of a gate dielectric 902 is then deposited over exposed portions of carbon-based material 704 including the portion of carbon-based material …
FIG. 10 is a three-dimensional diagram illustrating a metal top-gate contact having been formed on the gate dielectric over the portion of the carbon-based …
FIGS. 11-14 illustrate the exemplary embodiment described above wherein epitaxial thermally annealed SiC is the radiation hardened material and wherein the …
FIG. 12. As described above, thermally annealing an SiC film at a temperature of from about 1,200 ° C to about 1,600 ° C, e.g., at about 1,250 ° C, for a …
FIG. 13 is a three-dimensional diagram illustrating the radiation-hardened SiC film having been used to grow graphene according to an embodiment of the present …
FIG. 14. [0051] Although illustrative embodiments of the present invention have been described herein, it is to be understood that the invention is not limited …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A radiation-hard transistor, comprising: a radiation-hard substrate, wherein the substrate comprises a silicon wafer covered with a radiation-hard material; a carbon-based material on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon- based material serve as source and drain regions of the transistor; contacts formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor; a gate dielectric disposed over the portion of the carbon-based material that serves as the channel region of the transistor; and a top-gate contact on the gate dielectric. 2-3..
The radiation-hard transistor of claim 1 3, wherein the radiation-hard material comprises a calcium fluoride film.
The radiation-hard transistor of claim 1 3, wherein the radiation-hard material comprises a fluorinated silicon dioxide film.
The radiation-hard transistor of claim 1 3, wherein the radiation-hard material comprises a silicon carbide film.
The radiation-hard transistor of claim 1, wherein the carbon-based material comprises one or more of graphene and carbon nanotubes.
The radiation-hard transistor of claim 1, wherein the gate dielectric comprises aluminum oxide, hafnium oxide, silicon oxide or zirconium oxide.
canceled
canceled
A radiation-hard transistor, comprising: 3 Docket No. Y O R₉₂₀₁₀₀₃₈₈US₂ Customer No. 63919 a radiation-hard substrate, wherein the substrate comprises a calcium fluoride film; a carbon-based material on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon- based material serve as source and drain regions of the transistor; contacts formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor; a gate dielectric disposed over the portion of the carbon-based material that serves as the channel region of the transistor; and a top-gate contact on the gate dielectric. 4
Layer stacks claimed or described, ordered top of device to substrate.
radiation-hard top-gated transistor (Si wafer with radiation-hard material substrate)
radiation-hard top-gated transistor (CaF₂ substrate)
Materials described outside the worked examples.
silicon wafer
Si
carbon-based material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a three-dimensional diagram illustrating a carbon-based material having been formed (i.e., deposited or grown) on a radiation-hardened calcium …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–20 nm | — |
Duration | 3–100 hours |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,064,776Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a three-dimensional diagram illustrating a carbon-based material having been formed (i.e., deposited or grown) on a radiation-hardened calcium …
FIG. 2, contacts 202 are formed on the portions of the carbon-based material that serve as the source and drain regions of the transistor. According to an …
FIG. 3, a layer of a gate dielectric 302 is then deposited over exposed portions of carbon-based material 104 including the portion of carbon-based material …
FIG. 4, a top-gate contact 402 is formed on gate dielectric 302 over the portion of carbon-based material 104 that serves as the channel region of the …
FIG. 5 is a diagram illustrating a cross-sectional cut through the structure of
FIGS. 6-10 illustrate the device fabrication process using a different exemplary radiation-hard substrate configuration, i.e., a Si wafer covered with a …
FIG. 7 is a three-dimensional diagram illustrating a carbon-based material having been formed on the radiation-hard substrate of
FIG. 8, contacts 802 are formed on the portions of the carbon-based material that serve as source and drain regions of the transistor. According to an …
FIG. 9, a layer of a gate dielectric 902 is then deposited over exposed portions of carbon-based material 704 including the portion of carbon-based material …
FIG. 10 is a three-dimensional diagram illustrating a metal top-gate contact having been formed on the gate dielectric over the portion of the carbon-based …
FIGS. 11-14 illustrate the exemplary embodiment described above wherein epitaxial thermally annealed SiC is the radiation hardened material and wherein the …
FIG. 12. As described above, thermally annealing an SiC film at a temperature of from about 1,200 ° C to about 1,600 ° C, e.g., at about 1,250 ° C, for a …
FIG. 13 is a three-dimensional diagram illustrating the radiation-hardened SiC film having been used to grow graphene according to an embodiment of the present …
FIG. 14. [0051] Although illustrative embodiments of the present invention have been described herein, it is to be understood that the invention is not limited …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A radiation-hard transistor, comprising: a radiation-hard substrate, wherein the substrate comprises a silicon wafer covered with a radiation-hard material; a carbon-based material on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon- based material serve as source and drain regions of the transistor; contacts formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor; a gate dielectric disposed over the portion of the carbon-based material that serves as the channel region of the transistor; and a top-gate contact on the gate dielectric. 2-3..
The radiation-hard transistor of claim 1 3, wherein the radiation-hard material comprises a calcium fluoride film.
The radiation-hard transistor of claim 1 3, wherein the radiation-hard material comprises a fluorinated silicon dioxide film.
The radiation-hard transistor of claim 1 3, wherein the radiation-hard material comprises a silicon carbide film.
The radiation-hard transistor of claim 1, wherein the carbon-based material comprises one or more of graphene and carbon nanotubes.
The radiation-hard transistor of claim 1, wherein the gate dielectric comprises aluminum oxide, hafnium oxide, silicon oxide or zirconium oxide.
canceled
canceled
A radiation-hard transistor, comprising: 3 Docket No. Y O R₉₂₀₁₀₀₃₈₈US₂ Customer No. 63919 a radiation-hard substrate, wherein the substrate comprises a calcium fluoride film; a carbon-based material on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon- based material serve as source and drain regions of the transistor; contacts formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor; a gate dielectric disposed over the portion of the carbon-based material that serves as the channel region of the transistor; and a top-gate contact on the gate dielectric. 4
Layer stacks claimed or described, ordered top of device to substrate.
radiation-hard top-gated transistor (Si wafer with radiation-hard material substrate)
radiation-hard top-gated transistor (CaF₂ substrate)
Materials described outside the worked examples.
silicon wafer
Si
carbon-based material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a three-dimensional diagram illustrating a carbon-based material having been formed (i.e., deposited or grown) on a radiation-hardened calcium …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–20 nm | — |
Duration | 3–100 hours |
Related documents with shared materials, methods, properties, or citations.
gate dielectric
calcium fluoride film
CaF₂
fluorinated silicon dioxide film
silicon carbide film
SiC
graphene
carbon nanotubes
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon oxide
SiO₂
zirconium oxide
ZrO₂
FIG. 2, contacts 202 are formed on the portions of the carbon-based material that serve as the source and drain regions of the transistor. According to an …
FIG. 3, a layer of a gate dielectric 302 is then deposited over exposed portions of carbon-based material 104 including the portion of carbon-based material …
FIG. 4, a top-gate contact 402 is formed on gate dielectric 302 over the portion of carbon-based material 104 that serves as the channel region of the …
FIGS. 6-10 illustrate the device fabrication process using a different exemplary radiation-hard substrate configuration, i.e., a Si wafer covered with a …
FIG. 8, contacts 802 are formed on the portions of the carbon-based material that serve as source and drain regions of the transistor. According to an …
FIG. 9, a layer of a gate dielectric 902 is then deposited over exposed portions of carbon-based material 704 including the portion of carbon-based material …
FIG. 10 is a three-dimensional diagram illustrating a metal top-gate contact having been formed on the gate dielectric over the portion of the carbon-based …
FIGS. 11-14 illustrate the exemplary embodiment described above wherein epitaxial thermally annealed SiC is the radiation hardened material and wherein the …
| — |
Temperature | 1200–1600 °C | — |
Duration | 1–3 hours | — |
gate dielectric
calcium fluoride film
CaF₂
fluorinated silicon dioxide film
silicon carbide film
SiC
graphene
carbon nanotubes
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon oxide
SiO₂
zirconium oxide
ZrO₂
FIG. 2, contacts 202 are formed on the portions of the carbon-based material that serve as the source and drain regions of the transistor. According to an …
FIG. 3, a layer of a gate dielectric 302 is then deposited over exposed portions of carbon-based material 104 including the portion of carbon-based material …
FIG. 4, a top-gate contact 402 is formed on gate dielectric 302 over the portion of carbon-based material 104 that serves as the channel region of the …
FIGS. 6-10 illustrate the device fabrication process using a different exemplary radiation-hard substrate configuration, i.e., a Si wafer covered with a …
FIG. 8, contacts 802 are formed on the portions of the carbon-based material that serve as source and drain regions of the transistor. According to an …
FIG. 9, a layer of a gate dielectric 902 is then deposited over exposed portions of carbon-based material 704 including the portion of carbon-based material …
FIG. 10 is a three-dimensional diagram illustrating a metal top-gate contact having been formed on the gate dielectric over the portion of the carbon-based …
FIGS. 11-14 illustrate the exemplary embodiment described above wherein epitaxial thermally annealed SiC is the radiation hardened material and wherein the …
| — |
Temperature | 1200–1600 °C | — |
Duration | 1–3 hours | — |
gate dielectric
calcium fluoride film
CaF₂
fluorinated silicon dioxide film
silicon carbide film
SiC
graphene
carbon nanotubes
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon oxide
SiO₂
zirconium oxide
ZrO₂
FIG. 2, contacts 202 are formed on the portions of the carbon-based material that serve as the source and drain regions of the transistor. According to an …
FIG. 3, a layer of a gate dielectric 302 is then deposited over exposed portions of carbon-based material 104 including the portion of carbon-based material …
FIG. 4, a top-gate contact 402 is formed on gate dielectric 302 over the portion of carbon-based material 104 that serves as the channel region of the …
FIGS. 6-10 illustrate the device fabrication process using a different exemplary radiation-hard substrate configuration, i.e., a Si wafer covered with a …
FIG. 8, contacts 802 are formed on the portions of the carbon-based material that serve as source and drain regions of the transistor. According to an …
FIG. 9, a layer of a gate dielectric 902 is then deposited over exposed portions of carbon-based material 704 including the portion of carbon-based material …
FIG. 10 is a three-dimensional diagram illustrating a metal top-gate contact having been formed on the gate dielectric over the portion of the carbon-based …
FIGS. 11-14 illustrate the exemplary embodiment described above wherein epitaxial thermally annealed SiC is the radiation hardened material and wherein the …
| — |
Temperature | 1200–1600 °C | — |
Duration | 1–3 hours | — |
gate dielectric
calcium fluoride film
CaF₂
fluorinated silicon dioxide film
silicon carbide film
SiC
graphene
carbon nanotubes
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon oxide
SiO₂
zirconium oxide
ZrO₂
FIG. 2, contacts 202 are formed on the portions of the carbon-based material that serve as the source and drain regions of the transistor. According to an …
FIG. 3, a layer of a gate dielectric 302 is then deposited over exposed portions of carbon-based material 104 including the portion of carbon-based material …
FIG. 4, a top-gate contact 402 is formed on gate dielectric 302 over the portion of carbon-based material 104 that serves as the channel region of the …
FIGS. 6-10 illustrate the device fabrication process using a different exemplary radiation-hard substrate configuration, i.e., a Si wafer covered with a …
FIG. 8, contacts 802 are formed on the portions of the carbon-based material that serve as source and drain regions of the transistor. According to an …
FIG. 9, a layer of a gate dielectric 902 is then deposited over exposed portions of carbon-based material 704 including the portion of carbon-based material …
FIG. 10 is a three-dimensional diagram illustrating a metal top-gate contact having been formed on the gate dielectric over the portion of the carbon-based …
FIGS. 11-14 illustrate the exemplary embodiment described above wherein epitaxial thermally annealed SiC is the radiation hardened material and wherein the …
| — |
Temperature | 1200–1600 °C | — |
Duration | 1–3 hours | — |