Patent
US 10,998,405Low-Defect Graphene-Based Devices & Interconnects
Paul A. ZIMMERMAN
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,998,405Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flow diagram illustrating a method for fabricating low-defect graphene- based devices and device interconnects, in accordance with some embodiments;
FIG. 2A is a flow diagram illustrating a method for preparing a substrate suitable for low-defect graphene-based devices and device interconnects, in accordance …
FIG. 3A is a flow diagram illustrating a method for synthesizing a solution with molecular graphene suitable for fabricating low-defect graphene-based devices …
FIG. 4D is XPS output showing element composition of a sample including molecular graphene suitable for fabricating low-defect graphene-based devices and …
FIG. 5 is a flow diagram illustrating a method of depositing molecular graphene on a substrate with template structures, in accordance with some embodiments;
FIG. 6A, 6 B, 6C, 6 D, and 6E illustrate isometric views of substrate processing and molecular graphene deposition for selected operations in the method …
FIG. 7 is a flow diagram illustrating a method for fabricating a transistor employing a molecular graphene disposed on a substrate, in accordance with some …
FIG. 8A, 8 B, 8C, 8 D, 8E, 8F, and 8G illustrate isometric views of substrate processing for selected operations in the method illustrated in
FIG. 9 is a flow diagram illustrating a method for fabricating a graphene-based interconnects, in accordance with some embodiments;
FIG. 10 A, 10 B, and 10 C illustrate isometric views of substrate processing for selected operations in the method illustrated in
FIG. 11 is an isometric view of a low-defect graphene-based transistor coupled to a low-defect graphene-based interconnect, in accordance with an embodiment;
FIG. 12 is a schematic illustrating a mobile computing platform and a data server machine employing low-defect graphene-based TFETs and/or interconnects, in …
FIG. 13 is a functional block diagram illustrating an electronic computing device, in accordance with some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Claims 1-31 Canceled
Canceled
A graphene-based transistor, comprising: a polycyclic aromatic hydrocarbon (PAH) molecule over a substrate surface, wherein the PAH molecule has a lateral dimension in the plane of the substrate surface of at least I nm, and wherein the PAH molecule extends between a pluralit y of vias through the substrate, a gate stack over at least a first portion of the PAH molecule; and a conductive source terminal and a drain terminal electrically coupled to, and in direct physical contact with, second and third portions of the PAH molecule, respectively, wherein the first portion of the PAH molecule is between the second and third portions of the PAH molecule, and wherein the conductive source terminal and a drain terminal intersect the PAH molecule at the vias. Currently amended
The transistor of claim 32, wherein: the substrate comprises a porous oxide;. Currently amended
The transistor of claim 32, wherein the PAH molecule has six-fold rotational symmetry. Previously presented
. Canceled
A device, comprising: a substrate; a two-dimensional (2 D) array of vias through the substrate; a linear array of polycyclic aromatic hydrocarbon (PAH) molecules over a substrate surface between adjacent ones of the vias, wherein the linear array comprises two layers of the PAH molecules, and individual ones of the PAH molecules within a first of the layers each have a first portion between second and third portions, the second portion in direct physical contact with a first of the vias and the third portion in direct physical contact with a second of the vias; and a gate electrode coupled to the first portion of the PAH molecules. Previously presented
The device of claim 43, wherein the PAH molecule has six-fold rotational symmetry. Previously presented
A method of fabricating a graphene-based transistor, the method comprising: forming a plurality of through-substrate vias (TSVs) extending through an insulating substrate; depositing a polycyclic aromatic hydrocarbon (PAH) molecule with six-fold rotational symmetry over a first substrate surface between the plurality of the TSVs, wherein a first portion of the PAH molecule is between a second portion and third portion of the PAH molecule, wherein the second portion of the PAH molecule is in direct physical contact with a first of the TSVs and wherein the third portion of the PAH molecule is in direct physical contact with a second of the TSVs; forming a gate stack over the PAH molecule; backfilling the TSVs with a conductive material from a second side of the substrate, opposite the first side; and forming a source and drain interconnect on the second side of the substrate, the source and drain interconnect contacting conductive material in at least a pair of the TSVs. Previously presented
The method of claim 46, wherein forming the TSVs further comprises: applying a polymer mixture over a metal substrate; patterning an array of vias in a mask material by directed self-assembly; and performing a masked anodic etch of the metal substrate. Previously presented
The method of claim 46, wherein depositing the PAH molecules further comprises: rendering a rim of the TSVs hydrophobic; forming aqueous hemispheres confined to the hydrophobic TSV rims; exposing a surface on the first side of substrate between the TSVs to a non-polar solution containing the PAH molecule; evaporating the aqueous hemispheres; and irradiating the non-polar solution with a UV source. Previously presented
The method of claim 46, wherein backfilling the TSVs with conductive material further
. Canceled
The method of claim 50, further comprising forming the non-polar solution by: forming PAH molecules by irradiating, with a DUV source, a precursor solution containing cyclohexane; and hydroxylating the PAH molecules. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based transistor (TFET)
device with 2D array of vias and linear array of PAH molecules
Materials described outside the worked examples.
polycyclic aromatic hydrocarbon (PAH) molecule/molecular graphene
porous oxide substrate
C₅₄H₁₈
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4D is XPS output showing element composition of a sample including molecular graphene suitable for fabricating low-defect graphene-based devices and …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–15 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,998,405Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flow diagram illustrating a method for fabricating low-defect graphene- based devices and device interconnects, in accordance with some embodiments;
FIG. 2A is a flow diagram illustrating a method for preparing a substrate suitable for low-defect graphene-based devices and device interconnects, in accordance …
FIG. 3A is a flow diagram illustrating a method for synthesizing a solution with molecular graphene suitable for fabricating low-defect graphene-based devices …
FIG. 4D is XPS output showing element composition of a sample including molecular graphene suitable for fabricating low-defect graphene-based devices and …
FIG. 5 is a flow diagram illustrating a method of depositing molecular graphene on a substrate with template structures, in accordance with some embodiments;
FIG. 6A, 6 B, 6C, 6 D, and 6E illustrate isometric views of substrate processing and molecular graphene deposition for selected operations in the method …
FIG. 7 is a flow diagram illustrating a method for fabricating a transistor employing a molecular graphene disposed on a substrate, in accordance with some …
FIG. 8A, 8 B, 8C, 8 D, 8E, 8F, and 8G illustrate isometric views of substrate processing for selected operations in the method illustrated in
FIG. 9 is a flow diagram illustrating a method for fabricating a graphene-based interconnects, in accordance with some embodiments;
FIG. 10 A, 10 B, and 10 C illustrate isometric views of substrate processing for selected operations in the method illustrated in
FIG. 11 is an isometric view of a low-defect graphene-based transistor coupled to a low-defect graphene-based interconnect, in accordance with an embodiment;
FIG. 12 is a schematic illustrating a mobile computing platform and a data server machine employing low-defect graphene-based TFETs and/or interconnects, in …
FIG. 13 is a functional block diagram illustrating an electronic computing device, in accordance with some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Claims 1-31 Canceled
Canceled
A graphene-based transistor, comprising: a polycyclic aromatic hydrocarbon (PAH) molecule over a substrate surface, wherein the PAH molecule has a lateral dimension in the plane of the substrate surface of at least I nm, and wherein the PAH molecule extends between a pluralit y of vias through the substrate, a gate stack over at least a first portion of the PAH molecule; and a conductive source terminal and a drain terminal electrically coupled to, and in direct physical contact with, second and third portions of the PAH molecule, respectively, wherein the first portion of the PAH molecule is between the second and third portions of the PAH molecule, and wherein the conductive source terminal and a drain terminal intersect the PAH molecule at the vias. Currently amended
The transistor of claim 32, wherein: the substrate comprises a porous oxide;. Currently amended
The transistor of claim 32, wherein the PAH molecule has six-fold rotational symmetry. Previously presented
. Canceled
A device, comprising: a substrate; a two-dimensional (2 D) array of vias through the substrate; a linear array of polycyclic aromatic hydrocarbon (PAH) molecules over a substrate surface between adjacent ones of the vias, wherein the linear array comprises two layers of the PAH molecules, and individual ones of the PAH molecules within a first of the layers each have a first portion between second and third portions, the second portion in direct physical contact with a first of the vias and the third portion in direct physical contact with a second of the vias; and a gate electrode coupled to the first portion of the PAH molecules. Previously presented
The device of claim 43, wherein the PAH molecule has six-fold rotational symmetry. Previously presented
A method of fabricating a graphene-based transistor, the method comprising: forming a plurality of through-substrate vias (TSVs) extending through an insulating substrate; depositing a polycyclic aromatic hydrocarbon (PAH) molecule with six-fold rotational symmetry over a first substrate surface between the plurality of the TSVs, wherein a first portion of the PAH molecule is between a second portion and third portion of the PAH molecule, wherein the second portion of the PAH molecule is in direct physical contact with a first of the TSVs and wherein the third portion of the PAH molecule is in direct physical contact with a second of the TSVs; forming a gate stack over the PAH molecule; backfilling the TSVs with a conductive material from a second side of the substrate, opposite the first side; and forming a source and drain interconnect on the second side of the substrate, the source and drain interconnect contacting conductive material in at least a pair of the TSVs. Previously presented
The method of claim 46, wherein forming the TSVs further comprises: applying a polymer mixture over a metal substrate; patterning an array of vias in a mask material by directed self-assembly; and performing a masked anodic etch of the metal substrate. Previously presented
The method of claim 46, wherein depositing the PAH molecules further comprises: rendering a rim of the TSVs hydrophobic; forming aqueous hemispheres confined to the hydrophobic TSV rims; exposing a surface on the first side of substrate between the TSVs to a non-polar solution containing the PAH molecule; evaporating the aqueous hemispheres; and irradiating the non-polar solution with a UV source. Previously presented
The method of claim 46, wherein backfilling the TSVs with conductive material further
. Canceled
The method of claim 50, further comprising forming the non-polar solution by: forming PAH molecules by irradiating, with a DUV source, a precursor solution containing cyclohexane; and hydroxylating the PAH molecules. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based transistor (TFET)
device with 2D array of vias and linear array of PAH molecules
Materials described outside the worked examples.
polycyclic aromatic hydrocarbon (PAH) molecule/molecular graphene
porous oxide substrate
C₅₄H₁₈
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4D is XPS output showing element composition of a sample including molecular graphene suitable for fabricating low-defect graphene-based devices and …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–15 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,998,405Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flow diagram illustrating a method for fabricating low-defect graphene- based devices and device interconnects, in accordance with some embodiments;
FIG. 2A is a flow diagram illustrating a method for preparing a substrate suitable for low-defect graphene-based devices and device interconnects, in accordance …
FIG. 3A is a flow diagram illustrating a method for synthesizing a solution with molecular graphene suitable for fabricating low-defect graphene-based devices …
FIG. 4D is XPS output showing element composition of a sample including molecular graphene suitable for fabricating low-defect graphene-based devices and …
FIG. 5 is a flow diagram illustrating a method of depositing molecular graphene on a substrate with template structures, in accordance with some embodiments;
FIG. 6A, 6 B, 6C, 6 D, and 6E illustrate isometric views of substrate processing and molecular graphene deposition for selected operations in the method …
FIG. 7 is a flow diagram illustrating a method for fabricating a transistor employing a molecular graphene disposed on a substrate, in accordance with some …
FIG. 8A, 8 B, 8C, 8 D, 8E, 8F, and 8G illustrate isometric views of substrate processing for selected operations in the method illustrated in
FIG. 9 is a flow diagram illustrating a method for fabricating a graphene-based interconnects, in accordance with some embodiments;
FIG. 10 A, 10 B, and 10 C illustrate isometric views of substrate processing for selected operations in the method illustrated in
FIG. 11 is an isometric view of a low-defect graphene-based transistor coupled to a low-defect graphene-based interconnect, in accordance with an embodiment;
FIG. 12 is a schematic illustrating a mobile computing platform and a data server machine employing low-defect graphene-based TFETs and/or interconnects, in …
FIG. 13 is a functional block diagram illustrating an electronic computing device, in accordance with some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Claims 1-31 Canceled
Canceled
A graphene-based transistor, comprising: a polycyclic aromatic hydrocarbon (PAH) molecule over a substrate surface, wherein the PAH molecule has a lateral dimension in the plane of the substrate surface of at least I nm, and wherein the PAH molecule extends between a pluralit y of vias through the substrate, a gate stack over at least a first portion of the PAH molecule; and a conductive source terminal and a drain terminal electrically coupled to, and in direct physical contact with, second and third portions of the PAH molecule, respectively, wherein the first portion of the PAH molecule is between the second and third portions of the PAH molecule, and wherein the conductive source terminal and a drain terminal intersect the PAH molecule at the vias. Currently amended
The transistor of claim 32, wherein: the substrate comprises a porous oxide;. Currently amended
The transistor of claim 32, wherein the PAH molecule has six-fold rotational symmetry. Previously presented
. Canceled
A device, comprising: a substrate; a two-dimensional (2 D) array of vias through the substrate; a linear array of polycyclic aromatic hydrocarbon (PAH) molecules over a substrate surface between adjacent ones of the vias, wherein the linear array comprises two layers of the PAH molecules, and individual ones of the PAH molecules within a first of the layers each have a first portion between second and third portions, the second portion in direct physical contact with a first of the vias and the third portion in direct physical contact with a second of the vias; and a gate electrode coupled to the first portion of the PAH molecules. Previously presented
The device of claim 43, wherein the PAH molecule has six-fold rotational symmetry. Previously presented
A method of fabricating a graphene-based transistor, the method comprising: forming a plurality of through-substrate vias (TSVs) extending through an insulating substrate; depositing a polycyclic aromatic hydrocarbon (PAH) molecule with six-fold rotational symmetry over a first substrate surface between the plurality of the TSVs, wherein a first portion of the PAH molecule is between a second portion and third portion of the PAH molecule, wherein the second portion of the PAH molecule is in direct physical contact with a first of the TSVs and wherein the third portion of the PAH molecule is in direct physical contact with a second of the TSVs; forming a gate stack over the PAH molecule; backfilling the TSVs with a conductive material from a second side of the substrate, opposite the first side; and forming a source and drain interconnect on the second side of the substrate, the source and drain interconnect contacting conductive material in at least a pair of the TSVs. Previously presented
The method of claim 46, wherein forming the TSVs further comprises: applying a polymer mixture over a metal substrate; patterning an array of vias in a mask material by directed self-assembly; and performing a masked anodic etch of the metal substrate. Previously presented
The method of claim 46, wherein depositing the PAH molecules further comprises: rendering a rim of the TSVs hydrophobic; forming aqueous hemispheres confined to the hydrophobic TSV rims; exposing a surface on the first side of substrate between the TSVs to a non-polar solution containing the PAH molecule; evaporating the aqueous hemispheres; and irradiating the non-polar solution with a UV source. Previously presented
The method of claim 46, wherein backfilling the TSVs with conductive material further
. Canceled
The method of claim 50, further comprising forming the non-polar solution by: forming PAH molecules by irradiating, with a DUV source, a precursor solution containing cyclohexane; and hydroxylating the PAH molecules. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based transistor (TFET)
device with 2D array of vias and linear array of PAH molecules
Materials described outside the worked examples.
polycyclic aromatic hydrocarbon (PAH) molecule/molecular graphene
porous oxide substrate
C₅₄H₁₈
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4D is XPS output showing element composition of a sample including molecular graphene suitable for fabricating low-defect graphene-based devices and …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–15 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,998,405Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flow diagram illustrating a method for fabricating low-defect graphene- based devices and device interconnects, in accordance with some embodiments;
FIG. 2A is a flow diagram illustrating a method for preparing a substrate suitable for low-defect graphene-based devices and device interconnects, in accordance …
FIG. 3A is a flow diagram illustrating a method for synthesizing a solution with molecular graphene suitable for fabricating low-defect graphene-based devices …
FIG. 4D is XPS output showing element composition of a sample including molecular graphene suitable for fabricating low-defect graphene-based devices and …
FIG. 5 is a flow diagram illustrating a method of depositing molecular graphene on a substrate with template structures, in accordance with some embodiments;
FIG. 6A, 6 B, 6C, 6 D, and 6E illustrate isometric views of substrate processing and molecular graphene deposition for selected operations in the method …
FIG. 7 is a flow diagram illustrating a method for fabricating a transistor employing a molecular graphene disposed on a substrate, in accordance with some …
FIG. 8A, 8 B, 8C, 8 D, 8E, 8F, and 8G illustrate isometric views of substrate processing for selected operations in the method illustrated in
FIG. 9 is a flow diagram illustrating a method for fabricating a graphene-based interconnects, in accordance with some embodiments;
FIG. 10 A, 10 B, and 10 C illustrate isometric views of substrate processing for selected operations in the method illustrated in
FIG. 11 is an isometric view of a low-defect graphene-based transistor coupled to a low-defect graphene-based interconnect, in accordance with an embodiment;
FIG. 12 is a schematic illustrating a mobile computing platform and a data server machine employing low-defect graphene-based TFETs and/or interconnects, in …
FIG. 13 is a functional block diagram illustrating an electronic computing device, in accordance with some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Claims 1-31 Canceled
Canceled
A graphene-based transistor, comprising: a polycyclic aromatic hydrocarbon (PAH) molecule over a substrate surface, wherein the PAH molecule has a lateral dimension in the plane of the substrate surface of at least I nm, and wherein the PAH molecule extends between a pluralit y of vias through the substrate, a gate stack over at least a first portion of the PAH molecule; and a conductive source terminal and a drain terminal electrically coupled to, and in direct physical contact with, second and third portions of the PAH molecule, respectively, wherein the first portion of the PAH molecule is between the second and third portions of the PAH molecule, and wherein the conductive source terminal and a drain terminal intersect the PAH molecule at the vias. Currently amended
The transistor of claim 32, wherein: the substrate comprises a porous oxide;. Currently amended
The transistor of claim 32, wherein the PAH molecule has six-fold rotational symmetry. Previously presented
. Canceled
A device, comprising: a substrate; a two-dimensional (2 D) array of vias through the substrate; a linear array of polycyclic aromatic hydrocarbon (PAH) molecules over a substrate surface between adjacent ones of the vias, wherein the linear array comprises two layers of the PAH molecules, and individual ones of the PAH molecules within a first of the layers each have a first portion between second and third portions, the second portion in direct physical contact with a first of the vias and the third portion in direct physical contact with a second of the vias; and a gate electrode coupled to the first portion of the PAH molecules. Previously presented
The device of claim 43, wherein the PAH molecule has six-fold rotational symmetry. Previously presented
A method of fabricating a graphene-based transistor, the method comprising: forming a plurality of through-substrate vias (TSVs) extending through an insulating substrate; depositing a polycyclic aromatic hydrocarbon (PAH) molecule with six-fold rotational symmetry over a first substrate surface between the plurality of the TSVs, wherein a first portion of the PAH molecule is between a second portion and third portion of the PAH molecule, wherein the second portion of the PAH molecule is in direct physical contact with a first of the TSVs and wherein the third portion of the PAH molecule is in direct physical contact with a second of the TSVs; forming a gate stack over the PAH molecule; backfilling the TSVs with a conductive material from a second side of the substrate, opposite the first side; and forming a source and drain interconnect on the second side of the substrate, the source and drain interconnect contacting conductive material in at least a pair of the TSVs. Previously presented
The method of claim 46, wherein forming the TSVs further comprises: applying a polymer mixture over a metal substrate; patterning an array of vias in a mask material by directed self-assembly; and performing a masked anodic etch of the metal substrate. Previously presented
The method of claim 46, wherein depositing the PAH molecules further comprises: rendering a rim of the TSVs hydrophobic; forming aqueous hemispheres confined to the hydrophobic TSV rims; exposing a surface on the first side of substrate between the TSVs to a non-polar solution containing the PAH molecule; evaporating the aqueous hemispheres; and irradiating the non-polar solution with a UV source. Previously presented
The method of claim 46, wherein backfilling the TSVs with conductive material further
. Canceled
The method of claim 50, further comprising forming the non-polar solution by: forming PAH molecules by irradiating, with a DUV source, a precursor solution containing cyclohexane; and hydroxylating the PAH molecules. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based transistor (TFET)
device with 2D array of vias and linear array of PAH molecules
Materials described outside the worked examples.
polycyclic aromatic hydrocarbon (PAH) molecule/molecular graphene
porous oxide substrate
C₅₄H₁₈
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4D is XPS output showing element composition of a sample including molecular graphene suitable for fabricating low-defect graphene-based devices and …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–15 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
C₇₆H₂₀
C₉₆H₂₄
alumina (Al₂O₃)
Al₂O₃
zinc oxide (ZnO)
ZnO
graphene foam (composite of polymeric material and molecular graphene)
first metal interconnect (TiN, W, Pd, Cu, or Ru)
dielectric comprising metal oxide in polymer matrix
cyclohexane (PAH precursor solution)
C₆H₁₂
polystyrene-block-poly(methyl methacrylate) (PS-PMMA)
aluminum substrate
Al
zinc substrate
Zn
FIG. 7 is a flow diagram illustrating a method for fabricating a transistor employing a molecular graphene disposed on a substrate, in accordance with some …
FIG. 8A, 8 B, 8C, 8 D, 8E, 8F, and 8G illustrate isometric views of substrate processing for selected operations in the method illustrated in
FIG. 11 is an isometric view of a low-defect graphene-based transistor coupled to a low-defect graphene-based interconnect, in accordance with an embodiment;
| — |
Thickness | ≤ 2 nm | — |
Thickness | ≤ 254 nm | — |
Thickness | ≤ 193 nm | — |
Thickness | ≥ 193 nm | — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 1.5 nm | — |
Thickness | ≥ 3 nm | — |
C₇₆H₂₀
C₉₆H₂₄
alumina (Al₂O₃)
Al₂O₃
zinc oxide (ZnO)
ZnO
graphene foam (composite of polymeric material and molecular graphene)
first metal interconnect (TiN, W, Pd, Cu, or Ru)
dielectric comprising metal oxide in polymer matrix
cyclohexane (PAH precursor solution)
C₆H₁₂
polystyrene-block-poly(methyl methacrylate) (PS-PMMA)
aluminum substrate
Al
zinc substrate
Zn
FIG. 7 is a flow diagram illustrating a method for fabricating a transistor employing a molecular graphene disposed on a substrate, in accordance with some …
FIG. 8A, 8 B, 8C, 8 D, 8E, 8F, and 8G illustrate isometric views of substrate processing for selected operations in the method illustrated in
FIG. 11 is an isometric view of a low-defect graphene-based transistor coupled to a low-defect graphene-based interconnect, in accordance with an embodiment;
| — |
Thickness | ≤ 2 nm | — |
Thickness | ≤ 254 nm | — |
Thickness | ≤ 193 nm | — |
Thickness | ≥ 193 nm | — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 1.5 nm | — |
Thickness | ≥ 3 nm | — |
C₇₆H₂₀
C₉₆H₂₄
alumina (Al₂O₃)
Al₂O₃
zinc oxide (ZnO)
ZnO
graphene foam (composite of polymeric material and molecular graphene)
first metal interconnect (TiN, W, Pd, Cu, or Ru)
dielectric comprising metal oxide in polymer matrix
cyclohexane (PAH precursor solution)
C₆H₁₂
polystyrene-block-poly(methyl methacrylate) (PS-PMMA)
aluminum substrate
Al
zinc substrate
Zn
FIG. 7 is a flow diagram illustrating a method for fabricating a transistor employing a molecular graphene disposed on a substrate, in accordance with some …
FIG. 8A, 8 B, 8C, 8 D, 8E, 8F, and 8G illustrate isometric views of substrate processing for selected operations in the method illustrated in
FIG. 11 is an isometric view of a low-defect graphene-based transistor coupled to a low-defect graphene-based interconnect, in accordance with an embodiment;
| — |
Thickness | ≤ 2 nm | — |
Thickness | ≤ 254 nm | — |
Thickness | ≤ 193 nm | — |
Thickness | ≥ 193 nm | — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 1.5 nm | — |
Thickness | ≥ 3 nm | — |
C₇₆H₂₀
C₉₆H₂₄
alumina (Al₂O₃)
Al₂O₃
zinc oxide (ZnO)
ZnO
graphene foam (composite of polymeric material and molecular graphene)
first metal interconnect (TiN, W, Pd, Cu, or Ru)
dielectric comprising metal oxide in polymer matrix
cyclohexane (PAH precursor solution)
C₆H₁₂
polystyrene-block-poly(methyl methacrylate) (PS-PMMA)
aluminum substrate
Al
zinc substrate
Zn
FIG. 7 is a flow diagram illustrating a method for fabricating a transistor employing a molecular graphene disposed on a substrate, in accordance with some …
FIG. 8A, 8 B, 8C, 8 D, 8E, 8F, and 8G illustrate isometric views of substrate processing for selected operations in the method illustrated in
FIG. 11 is an isometric view of a low-defect graphene-based transistor coupled to a low-defect graphene-based interconnect, in accordance with an embodiment;
| — |
Thickness | ≤ 2 nm | — |
Thickness | ≤ 254 nm | — |
Thickness | ≤ 193 nm | — |
Thickness | ≥ 193 nm | — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 1.5 nm | — |
Thickness | ≥ 3 nm | — |