Patent
Atlas literature
Patent
US 12,170,328 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A is a contour diagram and
FIG. 2H are cross sections of an example semiconductor device that includes a gallium nitride field effect transistor (GaN FET), depicted in stages of an …
FIG. 3F are cross sections of another example semiconductor device that includes a GaN FET, depicted in stages of another example method of formation.
FIG. 45 3D, as disclosed in reference to the gate MOVPE process of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a silicon substrate; a buffer layer of III-N semiconductor material over the silicon substrate, wherein: the buffer layer includes a columnar region having a first thickness; the buffer layer includes a transition region surrounding the columnar region; and the buffer layer includes an inter-columnar region around the transition region, the inter-columnar region having a second thickness, the first thickness being greater than the second thickness; and the buffer layer has a (0001) crystal orientation, wherein a c-plane of the III-N semiconductor mate-rial of the buffer layer is parallel to a boundary plane between the buffer layer and the silicon substrate, and wherein a top surface in the inter-columnar region has a higher portion of surfaces off of the c-plane than a top surface in the columnar region; and a gallium nitride field effect transistor (GaN FET), includ-ing: a barrier layer of III-N semiconductor material over the buffer layer, the barrier layer extending across the columnar region and the transition region; and a gate of p-type III-N semiconductor material over the barrier layer, the gate extending over the columnar region and the transition region, wherein: the gate has a first gate thickness over the columnar region and a second gate thickness over the tran-sition region; both the first gate thickness and the second gate thickness are thicker than twice a vertical range of the top surface in the columnar region; and a difference between the first gate thickness and the second gate thickness is less than half the vertical range of the top surface in the columnar region.
The semiconductor device of claim 1, wherein a difference between the first thickness and the second thick-ness is 50 nanometers to 200 nanometers.
The semiconductor device of claim 1, wherein the buffer layer has an average thickness of 5 microns to microns.
The semiconductor device of claim 1, wherein: the vertical range of the top surface in the columnar region is 10 nanometers to 40 nanometers; and the vertical range of the top surface in the transition region extends from the columnar region to the inter-columnar region and is 50 nanometers to 200 nanometers.
The semiconductor device of claim 1, wherein the GaN FET includes an access region barrier sublayer of III-N semiconductor material over the buffer layer adjacent to the gate.
The semiconductor device of claim 1, wherein both the first gate thickness and the second gate thickness are nanometers to 100 nanometers thick.
The semiconductor device of claim 1, wherein the columnar region and the inter-columnar region each extend a lateral distance of 5 microns to 10 microns.
The semiconductor device of claim 1, wherein the GaN FET is free of the III-N semiconductor material of the gate over the barrier layer adjacent to the gate.
The semiconductor device of claim 1, wherein the silicon substrate includes silicon with a (111) lattice orien-tation.
The semiconductor device of claim 1, wherein the first gate thickness is different than the second gate thickness.
A gallium nitride field effect transistor (GaN FET), comprising: a semiconductor substrate; a buffer layer of III-N semiconductor material over the semiconductor substrate, the buffer layer including a (0001) crystal orientation, a c-plane of the III-N semiconductor material of the buffer layer being parallel to a boundary plane between the buffer layer and the semiconductor substrate, wherein the buffer layer has: a columnar region, wherein a top surface in the colum-nar region has a first portion of surfaces off of the c-plane; a transition region connected to and surrounding the columnar region, wherein a top surface in the tran-sition region has a second portion of surfaces off of the c-plane, the second portion greater than the first portion; and an inter-columnar region connected to and surrounding the transition region, wherein a top surface in the inter-columnar region has a third portion of surfaces off of the c-plane, the third portion less than the 20 second portion and greater than the first portion; a barrier layer of III-N semiconductor material on the buffer layer, the barrier layer extending across the columnar region and the transition region; and B₂ a gate layer of III-N semiconductor material on the barrier layer, the gate layer extending across the columnar region and the transition region.
The GaN FET of claim 11, wherein the gate layer has a first thickness over the columnar region and a second thickness over the transition region, the second thickness being different than the first thickness.
The GaN FET of claim 11, further including: a barrier sublayer of III-N semiconductor material over the buffer layer adjacent to the gate layer.
The GaN FET of claim 11, wherein the semiconductor substrate includes silicon with a (111) lattice orientation.
The GaN FET of claim 11, wherein the columnar region has a substantially circular shape parallel to a bound-ary plane between the buffer layer and the semiconductor substrate. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN FET (p-gate HEMT) on silicon substrate
GaN FET (gate layer on barrier layer) on semiconductor substrate
Materials described outside the worked examples.
silicon substrate
Si
III-N semiconductor buffer layer
III-N semiconductor barrier layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2H are cross sections of an example semiconductor device that includes a gallium nitride field effect transistor (GaN FET), depicted in stages of an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
buffer layer thickness for 650 V GaN FET | 7 microns | III-N semiconductor buffer layer |
buffer layer average thickness (claimed range) |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 8
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,170,328 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A is a contour diagram and
FIG. 2H are cross sections of an example semiconductor device that includes a gallium nitride field effect transistor (GaN FET), depicted in stages of an …
FIG. 3F are cross sections of another example semiconductor device that includes a GaN FET, depicted in stages of another example method of formation.
FIG. 45 3D, as disclosed in reference to the gate MOVPE process of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a silicon substrate; a buffer layer of III-N semiconductor material over the silicon substrate, wherein: the buffer layer includes a columnar region having a first thickness; the buffer layer includes a transition region surrounding the columnar region; and the buffer layer includes an inter-columnar region around the transition region, the inter-columnar region having a second thickness, the first thickness being greater than the second thickness; and the buffer layer has a (0001) crystal orientation, wherein a c-plane of the III-N semiconductor mate-rial of the buffer layer is parallel to a boundary plane between the buffer layer and the silicon substrate, and wherein a top surface in the inter-columnar region has a higher portion of surfaces off of the c-plane than a top surface in the columnar region; and a gallium nitride field effect transistor (GaN FET), includ-ing: a barrier layer of III-N semiconductor material over the buffer layer, the barrier layer extending across the columnar region and the transition region; and a gate of p-type III-N semiconductor material over the barrier layer, the gate extending over the columnar region and the transition region, wherein: the gate has a first gate thickness over the columnar region and a second gate thickness over the tran-sition region; both the first gate thickness and the second gate thickness are thicker than twice a vertical range of the top surface in the columnar region; and a difference between the first gate thickness and the second gate thickness is less than half the vertical range of the top surface in the columnar region.
The semiconductor device of claim 1, wherein a difference between the first thickness and the second thick-ness is 50 nanometers to 200 nanometers.
The semiconductor device of claim 1, wherein the buffer layer has an average thickness of 5 microns to microns.
The semiconductor device of claim 1, wherein: the vertical range of the top surface in the columnar region is 10 nanometers to 40 nanometers; and the vertical range of the top surface in the transition region extends from the columnar region to the inter-columnar region and is 50 nanometers to 200 nanometers.
The semiconductor device of claim 1, wherein the GaN FET includes an access region barrier sublayer of III-N semiconductor material over the buffer layer adjacent to the gate.
The semiconductor device of claim 1, wherein both the first gate thickness and the second gate thickness are nanometers to 100 nanometers thick.
The semiconductor device of claim 1, wherein the columnar region and the inter-columnar region each extend a lateral distance of 5 microns to 10 microns.
The semiconductor device of claim 1, wherein the GaN FET is free of the III-N semiconductor material of the gate over the barrier layer adjacent to the gate.
The semiconductor device of claim 1, wherein the silicon substrate includes silicon with a (111) lattice orien-tation.
The semiconductor device of claim 1, wherein the first gate thickness is different than the second gate thickness.
A gallium nitride field effect transistor (GaN FET), comprising: a semiconductor substrate; a buffer layer of III-N semiconductor material over the semiconductor substrate, the buffer layer including a (0001) crystal orientation, a c-plane of the III-N semiconductor material of the buffer layer being parallel to a boundary plane between the buffer layer and the semiconductor substrate, wherein the buffer layer has: a columnar region, wherein a top surface in the colum-nar region has a first portion of surfaces off of the c-plane; a transition region connected to and surrounding the columnar region, wherein a top surface in the tran-sition region has a second portion of surfaces off of the c-plane, the second portion greater than the first portion; and an inter-columnar region connected to and surrounding the transition region, wherein a top surface in the inter-columnar region has a third portion of surfaces off of the c-plane, the third portion less than the 20 second portion and greater than the first portion; a barrier layer of III-N semiconductor material on the buffer layer, the barrier layer extending across the columnar region and the transition region; and B₂ a gate layer of III-N semiconductor material on the barrier layer, the gate layer extending across the columnar region and the transition region.
The GaN FET of claim 11, wherein the gate layer has a first thickness over the columnar region and a second thickness over the transition region, the second thickness being different than the first thickness.
The GaN FET of claim 11, further including: a barrier sublayer of III-N semiconductor material over the buffer layer adjacent to the gate layer.
The GaN FET of claim 11, wherein the semiconductor substrate includes silicon with a (111) lattice orientation.
The GaN FET of claim 11, wherein the columnar region has a substantially circular shape parallel to a bound-ary plane between the buffer layer and the semiconductor substrate. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN FET (p-gate HEMT) on silicon substrate
GaN FET (gate layer on barrier layer) on semiconductor substrate
Materials described outside the worked examples.
silicon substrate
Si
III-N semiconductor buffer layer
III-N semiconductor barrier layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2H are cross sections of an example semiconductor device that includes a gallium nitride field effect transistor (GaN FET), depicted in stages of an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
buffer layer thickness for 650 V GaN FET | 7 microns | III-N semiconductor buffer layer |
buffer layer average thickness (claimed range) |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 8
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,170,328 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A is a contour diagram and
FIG. 2H are cross sections of an example semiconductor device that includes a gallium nitride field effect transistor (GaN FET), depicted in stages of an …
FIG. 3F are cross sections of another example semiconductor device that includes a GaN FET, depicted in stages of another example method of formation.
FIG. 45 3D, as disclosed in reference to the gate MOVPE process of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a silicon substrate; a buffer layer of III-N semiconductor material over the silicon substrate, wherein: the buffer layer includes a columnar region having a first thickness; the buffer layer includes a transition region surrounding the columnar region; and the buffer layer includes an inter-columnar region around the transition region, the inter-columnar region having a second thickness, the first thickness being greater than the second thickness; and the buffer layer has a (0001) crystal orientation, wherein a c-plane of the III-N semiconductor mate-rial of the buffer layer is parallel to a boundary plane between the buffer layer and the silicon substrate, and wherein a top surface in the inter-columnar region has a higher portion of surfaces off of the c-plane than a top surface in the columnar region; and a gallium nitride field effect transistor (GaN FET), includ-ing: a barrier layer of III-N semiconductor material over the buffer layer, the barrier layer extending across the columnar region and the transition region; and a gate of p-type III-N semiconductor material over the barrier layer, the gate extending over the columnar region and the transition region, wherein: the gate has a first gate thickness over the columnar region and a second gate thickness over the tran-sition region; both the first gate thickness and the second gate thickness are thicker than twice a vertical range of the top surface in the columnar region; and a difference between the first gate thickness and the second gate thickness is less than half the vertical range of the top surface in the columnar region.
The semiconductor device of claim 1, wherein a difference between the first thickness and the second thick-ness is 50 nanometers to 200 nanometers.
The semiconductor device of claim 1, wherein the buffer layer has an average thickness of 5 microns to microns.
The semiconductor device of claim 1, wherein: the vertical range of the top surface in the columnar region is 10 nanometers to 40 nanometers; and the vertical range of the top surface in the transition region extends from the columnar region to the inter-columnar region and is 50 nanometers to 200 nanometers.
The semiconductor device of claim 1, wherein the GaN FET includes an access region barrier sublayer of III-N semiconductor material over the buffer layer adjacent to the gate.
The semiconductor device of claim 1, wherein both the first gate thickness and the second gate thickness are nanometers to 100 nanometers thick.
The semiconductor device of claim 1, wherein the columnar region and the inter-columnar region each extend a lateral distance of 5 microns to 10 microns.
The semiconductor device of claim 1, wherein the GaN FET is free of the III-N semiconductor material of the gate over the barrier layer adjacent to the gate.
The semiconductor device of claim 1, wherein the silicon substrate includes silicon with a (111) lattice orien-tation.
The semiconductor device of claim 1, wherein the first gate thickness is different than the second gate thickness.
A gallium nitride field effect transistor (GaN FET), comprising: a semiconductor substrate; a buffer layer of III-N semiconductor material over the semiconductor substrate, the buffer layer including a (0001) crystal orientation, a c-plane of the III-N semiconductor material of the buffer layer being parallel to a boundary plane between the buffer layer and the semiconductor substrate, wherein the buffer layer has: a columnar region, wherein a top surface in the colum-nar region has a first portion of surfaces off of the c-plane; a transition region connected to and surrounding the columnar region, wherein a top surface in the tran-sition region has a second portion of surfaces off of the c-plane, the second portion greater than the first portion; and an inter-columnar region connected to and surrounding the transition region, wherein a top surface in the inter-columnar region has a third portion of surfaces off of the c-plane, the third portion less than the 20 second portion and greater than the first portion; a barrier layer of III-N semiconductor material on the buffer layer, the barrier layer extending across the columnar region and the transition region; and B₂ a gate layer of III-N semiconductor material on the barrier layer, the gate layer extending across the columnar region and the transition region.
The GaN FET of claim 11, wherein the gate layer has a first thickness over the columnar region and a second thickness over the transition region, the second thickness being different than the first thickness.
The GaN FET of claim 11, further including: a barrier sublayer of III-N semiconductor material over the buffer layer adjacent to the gate layer.
The GaN FET of claim 11, wherein the semiconductor substrate includes silicon with a (111) lattice orientation.
The GaN FET of claim 11, wherein the columnar region has a substantially circular shape parallel to a bound-ary plane between the buffer layer and the semiconductor substrate. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN FET (p-gate HEMT) on silicon substrate
GaN FET (gate layer on barrier layer) on semiconductor substrate
Materials described outside the worked examples.
silicon substrate
Si
III-N semiconductor buffer layer
III-N semiconductor barrier layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2H are cross sections of an example semiconductor device that includes a gallium nitride field effect transistor (GaN FET), depicted in stages of an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
buffer layer thickness for 650 V GaN FET | 7 microns | III-N semiconductor buffer layer |
buffer layer average thickness (claimed range) |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 8
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,170,328 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A is a contour diagram and
FIG. 2H are cross sections of an example semiconductor device that includes a gallium nitride field effect transistor (GaN FET), depicted in stages of an …
FIG. 3F are cross sections of another example semiconductor device that includes a GaN FET, depicted in stages of another example method of formation.
FIG. 45 3D, as disclosed in reference to the gate MOVPE process of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a silicon substrate; a buffer layer of III-N semiconductor material over the silicon substrate, wherein: the buffer layer includes a columnar region having a first thickness; the buffer layer includes a transition region surrounding the columnar region; and the buffer layer includes an inter-columnar region around the transition region, the inter-columnar region having a second thickness, the first thickness being greater than the second thickness; and the buffer layer has a (0001) crystal orientation, wherein a c-plane of the III-N semiconductor mate-rial of the buffer layer is parallel to a boundary plane between the buffer layer and the silicon substrate, and wherein a top surface in the inter-columnar region has a higher portion of surfaces off of the c-plane than a top surface in the columnar region; and a gallium nitride field effect transistor (GaN FET), includ-ing: a barrier layer of III-N semiconductor material over the buffer layer, the barrier layer extending across the columnar region and the transition region; and a gate of p-type III-N semiconductor material over the barrier layer, the gate extending over the columnar region and the transition region, wherein: the gate has a first gate thickness over the columnar region and a second gate thickness over the tran-sition region; both the first gate thickness and the second gate thickness are thicker than twice a vertical range of the top surface in the columnar region; and a difference between the first gate thickness and the second gate thickness is less than half the vertical range of the top surface in the columnar region.
The semiconductor device of claim 1, wherein a difference between the first thickness and the second thick-ness is 50 nanometers to 200 nanometers.
The semiconductor device of claim 1, wherein the buffer layer has an average thickness of 5 microns to microns.
The semiconductor device of claim 1, wherein: the vertical range of the top surface in the columnar region is 10 nanometers to 40 nanometers; and the vertical range of the top surface in the transition region extends from the columnar region to the inter-columnar region and is 50 nanometers to 200 nanometers.
The semiconductor device of claim 1, wherein the GaN FET includes an access region barrier sublayer of III-N semiconductor material over the buffer layer adjacent to the gate.
The semiconductor device of claim 1, wherein both the first gate thickness and the second gate thickness are nanometers to 100 nanometers thick.
The semiconductor device of claim 1, wherein the columnar region and the inter-columnar region each extend a lateral distance of 5 microns to 10 microns.
The semiconductor device of claim 1, wherein the GaN FET is free of the III-N semiconductor material of the gate over the barrier layer adjacent to the gate.
The semiconductor device of claim 1, wherein the silicon substrate includes silicon with a (111) lattice orien-tation.
The semiconductor device of claim 1, wherein the first gate thickness is different than the second gate thickness.
A gallium nitride field effect transistor (GaN FET), comprising: a semiconductor substrate; a buffer layer of III-N semiconductor material over the semiconductor substrate, the buffer layer including a (0001) crystal orientation, a c-plane of the III-N semiconductor material of the buffer layer being parallel to a boundary plane between the buffer layer and the semiconductor substrate, wherein the buffer layer has: a columnar region, wherein a top surface in the colum-nar region has a first portion of surfaces off of the c-plane; a transition region connected to and surrounding the columnar region, wherein a top surface in the tran-sition region has a second portion of surfaces off of the c-plane, the second portion greater than the first portion; and an inter-columnar region connected to and surrounding the transition region, wherein a top surface in the inter-columnar region has a third portion of surfaces off of the c-plane, the third portion less than the 20 second portion and greater than the first portion; a barrier layer of III-N semiconductor material on the buffer layer, the barrier layer extending across the columnar region and the transition region; and B₂ a gate layer of III-N semiconductor material on the barrier layer, the gate layer extending across the columnar region and the transition region.
The GaN FET of claim 11, wherein the gate layer has a first thickness over the columnar region and a second thickness over the transition region, the second thickness being different than the first thickness.
The GaN FET of claim 11, further including: a barrier sublayer of III-N semiconductor material over the buffer layer adjacent to the gate layer.
The GaN FET of claim 11, wherein the semiconductor substrate includes silicon with a (111) lattice orientation.
The GaN FET of claim 11, wherein the columnar region has a substantially circular shape parallel to a bound-ary plane between the buffer layer and the semiconductor substrate. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN FET (p-gate HEMT) on silicon substrate
GaN FET (gate layer on barrier layer) on semiconductor substrate
Materials described outside the worked examples.
silicon substrate
Si
III-N semiconductor buffer layer
III-N semiconductor barrier layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2H are cross sections of an example semiconductor device that includes a gallium nitride field effect transistor (GaN FET), depicted in stages of an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
buffer layer thickness for 650 V GaN FET | 7 microns | III-N semiconductor buffer layer |
buffer layer average thickness (claimed range) |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 8
Related documents with shared materials, methods, properties, or citations.
p-type III-N semiconductor gate
gallium nitride
GaN
aluminum nitride
AlN
aluminum gallium nitride
AlxGa₁-xN
FIG. 3F are cross sections of another example semiconductor device that includes a GaN FET, depicted in stages of another example method of formation.
| ≥ 5 microns |
III-N semiconductor buffer layer |
difference between columnar and inter-columnar buffer layer thickness | 50–200 nanometers | III-N semiconductor buffer layer |
vertical range of top surface in columnar region (claimed) | 10–40 nanometers | III-N semiconductor buffer layer |
vertical range of top surface in transition region (claimed) | 50–200 nanometers | III-N semiconductor buffer layer |
first and second gate thickness (claimed range) | ≤ 100 nanometers | p-type III-N semiconductor gate |
lateral distance of columnar and inter-columnar regions (claimed) | 5–10 microns | III-N semiconductor buffer layer |
Thickness | 150–300 mm | — |
Thickness | 50–200 µm | — |
Thickness | 10–40 nm | — |
Thickness | 1–2 µm | — |
Thickness | 80–120 nm | — |
Thickness | 50–200 nm | — |
Thickness | 5–40 µm | — |
Temperature | 700–900 °C | — |
Temperature | 1000–1200 °C | — |
Thickness | 25–100 nm | — |
Thickness | 5–10 µm | — |
Thickness | 10–25 nm | — |
Temperature | 900–1100 °C | — |
Flow Rate | 50–1000 sccm | — |
Pressure | 10–50 mTorr | — |
Thickness | 40–100 nm | — |
Thickness | 10–50 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≥ 25 nm | — |
Thickness | ≤ 30 nm | — |
Thickness | ≥ 50 nm | — |
Cited non-patent literature · 3
p-type III-N semiconductor gate
gallium nitride
GaN
aluminum nitride
AlN
aluminum gallium nitride
AlxGa₁-xN
FIG. 3F are cross sections of another example semiconductor device that includes a GaN FET, depicted in stages of another example method of formation.
| ≥ 5 microns |
III-N semiconductor buffer layer |
difference between columnar and inter-columnar buffer layer thickness | 50–200 nanometers | III-N semiconductor buffer layer |
vertical range of top surface in columnar region (claimed) | 10–40 nanometers | III-N semiconductor buffer layer |
vertical range of top surface in transition region (claimed) | 50–200 nanometers | III-N semiconductor buffer layer |
first and second gate thickness (claimed range) | ≤ 100 nanometers | p-type III-N semiconductor gate |
lateral distance of columnar and inter-columnar regions (claimed) | 5–10 microns | III-N semiconductor buffer layer |
Thickness | 150–300 mm | — |
Thickness | 50–200 µm | — |
Thickness | 10–40 nm | — |
Thickness | 1–2 µm | — |
Thickness | 80–120 nm | — |
Thickness | 50–200 nm | — |
Thickness | 5–40 µm | — |
Temperature | 700–900 °C | — |
Temperature | 1000–1200 °C | — |
Thickness | 25–100 nm | — |
Thickness | 5–10 µm | — |
Thickness | 10–25 nm | — |
Temperature | 900–1100 °C | — |
Flow Rate | 50–1000 sccm | — |
Pressure | 10–50 mTorr | — |
Thickness | 40–100 nm | — |
Thickness | 10–50 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≥ 25 nm | — |
Thickness | ≤ 30 nm | — |
Thickness | ≥ 50 nm | — |
Cited non-patent literature · 3
p-type III-N semiconductor gate
gallium nitride
GaN
aluminum nitride
AlN
aluminum gallium nitride
AlxGa₁-xN
FIG. 3F are cross sections of another example semiconductor device that includes a GaN FET, depicted in stages of another example method of formation.
| ≥ 5 microns |
III-N semiconductor buffer layer |
difference between columnar and inter-columnar buffer layer thickness | 50–200 nanometers | III-N semiconductor buffer layer |
vertical range of top surface in columnar region (claimed) | 10–40 nanometers | III-N semiconductor buffer layer |
vertical range of top surface in transition region (claimed) | 50–200 nanometers | III-N semiconductor buffer layer |
first and second gate thickness (claimed range) | ≤ 100 nanometers | p-type III-N semiconductor gate |
lateral distance of columnar and inter-columnar regions (claimed) | 5–10 microns | III-N semiconductor buffer layer |
Thickness | 150–300 mm | — |
Thickness | 50–200 µm | — |
Thickness | 10–40 nm | — |
Thickness | 1–2 µm | — |
Thickness | 80–120 nm | — |
Thickness | 50–200 nm | — |
Thickness | 5–40 µm | — |
Temperature | 700–900 °C | — |
Temperature | 1000–1200 °C | — |
Thickness | 25–100 nm | — |
Thickness | 5–10 µm | — |
Thickness | 10–25 nm | — |
Temperature | 900–1100 °C | — |
Flow Rate | 50–1000 sccm | — |
Pressure | 10–50 mTorr | — |
Thickness | 40–100 nm | — |
Thickness | 10–50 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≥ 25 nm | — |
Thickness | ≤ 30 nm | — |
Thickness | ≥ 50 nm | — |
Cited non-patent literature · 3
p-type III-N semiconductor gate
gallium nitride
GaN
aluminum nitride
AlN
aluminum gallium nitride
AlxGa₁-xN
FIG. 3F are cross sections of another example semiconductor device that includes a GaN FET, depicted in stages of another example method of formation.
| ≥ 5 microns |
III-N semiconductor buffer layer |
difference between columnar and inter-columnar buffer layer thickness | 50–200 nanometers | III-N semiconductor buffer layer |
vertical range of top surface in columnar region (claimed) | 10–40 nanometers | III-N semiconductor buffer layer |
vertical range of top surface in transition region (claimed) | 50–200 nanometers | III-N semiconductor buffer layer |
first and second gate thickness (claimed range) | ≤ 100 nanometers | p-type III-N semiconductor gate |
lateral distance of columnar and inter-columnar regions (claimed) | 5–10 microns | III-N semiconductor buffer layer |
Thickness | 150–300 mm | — |
Thickness | 50–200 µm | — |
Thickness | 10–40 nm | — |
Thickness | 1–2 µm | — |
Thickness | 80–120 nm | — |
Thickness | 50–200 nm | — |
Thickness | 5–40 µm | — |
Temperature | 700–900 °C | — |
Temperature | 1000–1200 °C | — |
Thickness | 25–100 nm | — |
Thickness | 5–10 µm | — |
Thickness | 10–25 nm | — |
Temperature | 900–1100 °C | — |
Flow Rate | 50–1000 sccm | — |
Pressure | 10–50 mTorr | — |
Thickness | 40–100 nm | — |
Thickness | 10–50 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≥ 25 nm | — |
Thickness | ≤ 30 nm | — |
Thickness | ≥ 50 nm | — |
Cited non-patent literature · 3
