Patent
US 12,166,119 B2GALLIUM NITRIDE TRANSISTOR WITH A DOPED REGION
Dong Seup Lee, Jungwoo Joh, Pinghai Hao, Sameer Pendharkar
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)·Dec. 10, 2024·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 12,166,119 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1(a) depicts a cross-section of an illustrative GaN- based high electron mobility transistor (HEMT), in accor- dance with various examples.
FIGS. 2(a)-2(f) are illustrative flow diagrams depicting the steps involved in fabricating an enhancement mode HEMT (e-HEMT), in accordance with various …
FIGS. 3(a)-3(d) are illustrative flow diagrams depicting the steps involved in fabricating a depletion mode HEMT, in accordance with various examples.
FIG. 4 depicts an illustrative method to fabricate an e-HEMT, in accordance with various examples.
FIG. 5 depicts an illustrative method to fabricate a d-HEMT, in accordance with various examples.
FIG. 100(e) includes a highly-doped region 108 that extends from the top surface 103 into the GaN layer 106. In the example shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor, comprising: a gallium nitride (GaN) layer; 20 a GaN-based alloy layer supported by the GaN layer, the GaN-based alloy layer having a first side facing away from the GaN layer and a second side opposite the first side and facing the GaN layer; source, drain, and gate contact structures that are sup-ported by the GaN-based alloy layer; and an n-doped region including at least a portion positioned in a drain access region of the transistor, the n-doped region extending from the first side of the GaN-based alloy layer into the GaN layer, wherein: the drain contact structure has a first edge facing the gate contact structure and a second edge opposite the first edge; the n-doped region has a first edge facing the gate contact structure and a second edge opposite the first edge; and the second edge of the n-doped region is laterally closer to the gate contact structure than the second edge of the drain contact structure, wherein the drain contact structure laterally extends past the n-doped region.
The transistor of claim 1, wherein the n-doped region contacts the drain contact structure.
The transistor of claim 1, wherein the n-doped region is a first n-doped region, the transistor further comprising: a second n-doped region extending from the first side of the GaN-based alloy layer into the GaN layer.
The transistor of claim 1, further comprising: a p-doped GaN layer positioned on the first side, wherein the gate contact structure is positioned on the p-doped GaN layer.
The transistor of claim 1, wherein the GaN-based alloy layer comprises Al(X)In(Y)Ga(1-X-Y)N, where X and Y are the concentrations of aluminum and indium, respectively.
The transistor of claim 1, wherein the n-doped region comprises silicon, germanium, or both.
The transistor of claim 1, wherein the n-doped region comprises an n-type dopant concentration greater than 1×1017 cm⁻³.
The transistor of claim 1, wherein the n-doped region prevents a depletion region reaching a drain contact region of the transistor.
The transistor of claim 1, wherein the n-doped region increases an electron density proximate a drain contact region of the transistor.
A transistor, comprising: a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the top side of the GaN-based alloy layer; and an n-doped region including at least a portion positioned in a drain access region between the gate contact structure and the drain contact structure, the n-doped region extending from the top side of the GaN-based alloy layer into the GaN layer, wherein: the drain contact structure has a first edge facing the gate contact structure and a second edge opposite the first edge; the n-doped region has a first edge facing the gate contact structure and a second edge opposite the first edge; and the second edge of the n-doped region is laterally closer to the gate contact structure than the second edge of the drain contact structure, wherein the drain contact structure laterally extends past the n-doped region.
The transistor of claim 12, wherein the n-doped region contacts the drain contact structure.
The transistor of claim 12, further comprising: another n-doped region extending from the top side of the GaN-based alloy layer into the GaN layer, and contact-ing the source contact structure.
The transistor of claim 12, further comprising: a p-doped GaN layer positioned on the top side, wherein the gate contact structure is positioned on the p-doped GaN layer.
The transistor of claim 12, wherein the GaN-based alloy layer comprises Al(X)In(Y)Ga(1-X-Y)N, where X and Y are the concentrations of aluminum and indium, respec-tively.
The transistor of claim 12, wherein the n-doped region includes silicon or germanium, or both.
The transistor of claim 12, wherein the n-doped region prevents a depletion region reaching a drain contact region of the transistor. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based high electron mobility transistor (HEMT)
Materials described outside the worked examples.
gallium nitride (GaN) layer
GaN
GaN-based alloy layer
Al(X)In(Y)Ga(1-X-Y)N
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1(a) depicts a cross-section of an illustrative GaN- based high electron mobility transistor (HEMT), in accor- dance with various examples.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
n-type dopant concentration in n-doped region | ≥ 100000000000000000 cm⁻³ | n-doped region |
AlGaN layer thickness | 5–300 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 16
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,166,119 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1(a) depicts a cross-section of an illustrative GaN- based high electron mobility transistor (HEMT), in accor- dance with various examples.
FIGS. 2(a)-2(f) are illustrative flow diagrams depicting the steps involved in fabricating an enhancement mode HEMT (e-HEMT), in accordance with various …
FIGS. 3(a)-3(d) are illustrative flow diagrams depicting the steps involved in fabricating a depletion mode HEMT, in accordance with various examples.
FIG. 4 depicts an illustrative method to fabricate an e-HEMT, in accordance with various examples.
FIG. 5 depicts an illustrative method to fabricate a d-HEMT, in accordance with various examples.
FIG. 100(e) includes a highly-doped region 108 that extends from the top surface 103 into the GaN layer 106. In the example shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor, comprising: a gallium nitride (GaN) layer; 20 a GaN-based alloy layer supported by the GaN layer, the GaN-based alloy layer having a first side facing away from the GaN layer and a second side opposite the first side and facing the GaN layer; source, drain, and gate contact structures that are sup-ported by the GaN-based alloy layer; and an n-doped region including at least a portion positioned in a drain access region of the transistor, the n-doped region extending from the first side of the GaN-based alloy layer into the GaN layer, wherein: the drain contact structure has a first edge facing the gate contact structure and a second edge opposite the first edge; the n-doped region has a first edge facing the gate contact structure and a second edge opposite the first edge; and the second edge of the n-doped region is laterally closer to the gate contact structure than the second edge of the drain contact structure, wherein the drain contact structure laterally extends past the n-doped region.
The transistor of claim 1, wherein the n-doped region contacts the drain contact structure.
The transistor of claim 1, wherein the n-doped region is a first n-doped region, the transistor further comprising: a second n-doped region extending from the first side of the GaN-based alloy layer into the GaN layer.
The transistor of claim 1, further comprising: a p-doped GaN layer positioned on the first side, wherein the gate contact structure is positioned on the p-doped GaN layer.
The transistor of claim 1, wherein the GaN-based alloy layer comprises Al(X)In(Y)Ga(1-X-Y)N, where X and Y are the concentrations of aluminum and indium, respectively.
The transistor of claim 1, wherein the n-doped region comprises silicon, germanium, or both.
The transistor of claim 1, wherein the n-doped region comprises an n-type dopant concentration greater than 1×1017 cm⁻³.
The transistor of claim 1, wherein the n-doped region prevents a depletion region reaching a drain contact region of the transistor.
The transistor of claim 1, wherein the n-doped region increases an electron density proximate a drain contact region of the transistor.
A transistor, comprising: a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the top side of the GaN-based alloy layer; and an n-doped region including at least a portion positioned in a drain access region between the gate contact structure and the drain contact structure, the n-doped region extending from the top side of the GaN-based alloy layer into the GaN layer, wherein: the drain contact structure has a first edge facing the gate contact structure and a second edge opposite the first edge; the n-doped region has a first edge facing the gate contact structure and a second edge opposite the first edge; and the second edge of the n-doped region is laterally closer to the gate contact structure than the second edge of the drain contact structure, wherein the drain contact structure laterally extends past the n-doped region.
The transistor of claim 12, wherein the n-doped region contacts the drain contact structure.
The transistor of claim 12, further comprising: another n-doped region extending from the top side of the GaN-based alloy layer into the GaN layer, and contact-ing the source contact structure.
The transistor of claim 12, further comprising: a p-doped GaN layer positioned on the top side, wherein the gate contact structure is positioned on the p-doped GaN layer.
The transistor of claim 12, wherein the GaN-based alloy layer comprises Al(X)In(Y)Ga(1-X-Y)N, where X and Y are the concentrations of aluminum and indium, respec-tively.
The transistor of claim 12, wherein the n-doped region includes silicon or germanium, or both.
The transistor of claim 12, wherein the n-doped region prevents a depletion region reaching a drain contact region of the transistor. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based high electron mobility transistor (HEMT)
Materials described outside the worked examples.
gallium nitride (GaN) layer
GaN
GaN-based alloy layer
Al(X)In(Y)Ga(1-X-Y)N
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1(a) depicts a cross-section of an illustrative GaN- based high electron mobility transistor (HEMT), in accor- dance with various examples.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
n-type dopant concentration in n-doped region | ≥ 100000000000000000 cm⁻³ | n-doped region |
AlGaN layer thickness | 5–300 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 16
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,166,119 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1(a) depicts a cross-section of an illustrative GaN- based high electron mobility transistor (HEMT), in accor- dance with various examples.
FIGS. 2(a)-2(f) are illustrative flow diagrams depicting the steps involved in fabricating an enhancement mode HEMT (e-HEMT), in accordance with various …
FIGS. 3(a)-3(d) are illustrative flow diagrams depicting the steps involved in fabricating a depletion mode HEMT, in accordance with various examples.
FIG. 4 depicts an illustrative method to fabricate an e-HEMT, in accordance with various examples.
FIG. 5 depicts an illustrative method to fabricate a d-HEMT, in accordance with various examples.
FIG. 100(e) includes a highly-doped region 108 that extends from the top surface 103 into the GaN layer 106. In the example shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor, comprising: a gallium nitride (GaN) layer; 20 a GaN-based alloy layer supported by the GaN layer, the GaN-based alloy layer having a first side facing away from the GaN layer and a second side opposite the first side and facing the GaN layer; source, drain, and gate contact structures that are sup-ported by the GaN-based alloy layer; and an n-doped region including at least a portion positioned in a drain access region of the transistor, the n-doped region extending from the first side of the GaN-based alloy layer into the GaN layer, wherein: the drain contact structure has a first edge facing the gate contact structure and a second edge opposite the first edge; the n-doped region has a first edge facing the gate contact structure and a second edge opposite the first edge; and the second edge of the n-doped region is laterally closer to the gate contact structure than the second edge of the drain contact structure, wherein the drain contact structure laterally extends past the n-doped region.
The transistor of claim 1, wherein the n-doped region contacts the drain contact structure.
The transistor of claim 1, wherein the n-doped region is a first n-doped region, the transistor further comprising: a second n-doped region extending from the first side of the GaN-based alloy layer into the GaN layer.
The transistor of claim 1, further comprising: a p-doped GaN layer positioned on the first side, wherein the gate contact structure is positioned on the p-doped GaN layer.
The transistor of claim 1, wherein the GaN-based alloy layer comprises Al(X)In(Y)Ga(1-X-Y)N, where X and Y are the concentrations of aluminum and indium, respectively.
The transistor of claim 1, wherein the n-doped region comprises silicon, germanium, or both.
The transistor of claim 1, wherein the n-doped region comprises an n-type dopant concentration greater than 1×1017 cm⁻³.
The transistor of claim 1, wherein the n-doped region prevents a depletion region reaching a drain contact region of the transistor.
The transistor of claim 1, wherein the n-doped region increases an electron density proximate a drain contact region of the transistor.
A transistor, comprising: a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the top side of the GaN-based alloy layer; and an n-doped region including at least a portion positioned in a drain access region between the gate contact structure and the drain contact structure, the n-doped region extending from the top side of the GaN-based alloy layer into the GaN layer, wherein: the drain contact structure has a first edge facing the gate contact structure and a second edge opposite the first edge; the n-doped region has a first edge facing the gate contact structure and a second edge opposite the first edge; and the second edge of the n-doped region is laterally closer to the gate contact structure than the second edge of the drain contact structure, wherein the drain contact structure laterally extends past the n-doped region.
The transistor of claim 12, wherein the n-doped region contacts the drain contact structure.
The transistor of claim 12, further comprising: another n-doped region extending from the top side of the GaN-based alloy layer into the GaN layer, and contact-ing the source contact structure.
The transistor of claim 12, further comprising: a p-doped GaN layer positioned on the top side, wherein the gate contact structure is positioned on the p-doped GaN layer.
The transistor of claim 12, wherein the GaN-based alloy layer comprises Al(X)In(Y)Ga(1-X-Y)N, where X and Y are the concentrations of aluminum and indium, respec-tively.
The transistor of claim 12, wherein the n-doped region includes silicon or germanium, or both.
The transistor of claim 12, wherein the n-doped region prevents a depletion region reaching a drain contact region of the transistor. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based high electron mobility transistor (HEMT)
Materials described outside the worked examples.
gallium nitride (GaN) layer
GaN
GaN-based alloy layer
Al(X)In(Y)Ga(1-X-Y)N
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1(a) depicts a cross-section of an illustrative GaN- based high electron mobility transistor (HEMT), in accor- dance with various examples.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
n-type dopant concentration in n-doped region | ≥ 100000000000000000 cm⁻³ | n-doped region |
AlGaN layer thickness | 5–300 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 16
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,166,119 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1(a) depicts a cross-section of an illustrative GaN- based high electron mobility transistor (HEMT), in accor- dance with various examples.
FIGS. 2(a)-2(f) are illustrative flow diagrams depicting the steps involved in fabricating an enhancement mode HEMT (e-HEMT), in accordance with various …
FIGS. 3(a)-3(d) are illustrative flow diagrams depicting the steps involved in fabricating a depletion mode HEMT, in accordance with various examples.
FIG. 4 depicts an illustrative method to fabricate an e-HEMT, in accordance with various examples.
FIG. 5 depicts an illustrative method to fabricate a d-HEMT, in accordance with various examples.
FIG. 100(e) includes a highly-doped region 108 that extends from the top surface 103 into the GaN layer 106. In the example shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor, comprising: a gallium nitride (GaN) layer; 20 a GaN-based alloy layer supported by the GaN layer, the GaN-based alloy layer having a first side facing away from the GaN layer and a second side opposite the first side and facing the GaN layer; source, drain, and gate contact structures that are sup-ported by the GaN-based alloy layer; and an n-doped region including at least a portion positioned in a drain access region of the transistor, the n-doped region extending from the first side of the GaN-based alloy layer into the GaN layer, wherein: the drain contact structure has a first edge facing the gate contact structure and a second edge opposite the first edge; the n-doped region has a first edge facing the gate contact structure and a second edge opposite the first edge; and the second edge of the n-doped region is laterally closer to the gate contact structure than the second edge of the drain contact structure, wherein the drain contact structure laterally extends past the n-doped region.
The transistor of claim 1, wherein the n-doped region contacts the drain contact structure.
The transistor of claim 1, wherein the n-doped region is a first n-doped region, the transistor further comprising: a second n-doped region extending from the first side of the GaN-based alloy layer into the GaN layer.
The transistor of claim 1, further comprising: a p-doped GaN layer positioned on the first side, wherein the gate contact structure is positioned on the p-doped GaN layer.
The transistor of claim 1, wherein the GaN-based alloy layer comprises Al(X)In(Y)Ga(1-X-Y)N, where X and Y are the concentrations of aluminum and indium, respectively.
The transistor of claim 1, wherein the n-doped region comprises silicon, germanium, or both.
The transistor of claim 1, wherein the n-doped region comprises an n-type dopant concentration greater than 1×1017 cm⁻³.
The transistor of claim 1, wherein the n-doped region prevents a depletion region reaching a drain contact region of the transistor.
The transistor of claim 1, wherein the n-doped region increases an electron density proximate a drain contact region of the transistor.
A transistor, comprising: a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the top side of the GaN-based alloy layer; and an n-doped region including at least a portion positioned in a drain access region between the gate contact structure and the drain contact structure, the n-doped region extending from the top side of the GaN-based alloy layer into the GaN layer, wherein: the drain contact structure has a first edge facing the gate contact structure and a second edge opposite the first edge; the n-doped region has a first edge facing the gate contact structure and a second edge opposite the first edge; and the second edge of the n-doped region is laterally closer to the gate contact structure than the second edge of the drain contact structure, wherein the drain contact structure laterally extends past the n-doped region.
The transistor of claim 12, wherein the n-doped region contacts the drain contact structure.
The transistor of claim 12, further comprising: another n-doped region extending from the top side of the GaN-based alloy layer into the GaN layer, and contact-ing the source contact structure.
The transistor of claim 12, further comprising: a p-doped GaN layer positioned on the top side, wherein the gate contact structure is positioned on the p-doped GaN layer.
The transistor of claim 12, wherein the GaN-based alloy layer comprises Al(X)In(Y)Ga(1-X-Y)N, where X and Y are the concentrations of aluminum and indium, respec-tively.
The transistor of claim 12, wherein the n-doped region includes silicon or germanium, or both.
The transistor of claim 12, wherein the n-doped region prevents a depletion region reaching a drain contact region of the transistor. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based high electron mobility transistor (HEMT)
Materials described outside the worked examples.
gallium nitride (GaN) layer
GaN
GaN-based alloy layer
Al(X)In(Y)Ga(1-X-Y)N
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1(a) depicts a cross-section of an illustrative GaN- based high electron mobility transistor (HEMT), in accor- dance with various examples.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
n-type dopant concentration in n-doped region | ≥ 100000000000000000 cm⁻³ | n-doped region |
AlGaN layer thickness | 5–300 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 16
Related documents with shared materials, methods, properties, or citations.
n-doped region
second n-doped region
p-doped GaN layer
GaN:p
magnesium dopant in p-doped GaN
Mg
silicon dopant
Si
germanium dopant
Ge
AlGaN layer
AlGaN
aluminum nitride seed layer
AlN
GaN layer thickness | 5–50000 nm | GaN |
seed layer (AlN) thickness | 0.1–0.5 µm | AlN |
n-doped region
second n-doped region
p-doped GaN layer
GaN:p
magnesium dopant in p-doped GaN
Mg
silicon dopant
Si
germanium dopant
Ge
AlGaN layer
AlGaN
aluminum nitride seed layer
AlN
GaN layer thickness | 5–50000 nm | GaN |
seed layer (AlN) thickness | 0.1–0.5 µm | AlN |
n-doped region
second n-doped region
p-doped GaN layer
GaN:p
magnesium dopant in p-doped GaN
Mg
silicon dopant
Si
germanium dopant
Ge
AlGaN layer
AlGaN
aluminum nitride seed layer
AlN
GaN layer thickness | 5–50000 nm | GaN |
seed layer (AlN) thickness | 0.1–0.5 µm | AlN |
n-doped region
second n-doped region
p-doped GaN layer
GaN:p
magnesium dopant in p-doped GaN
Mg
silicon dopant
Si
germanium dopant
Ge
AlGaN layer
AlGaN
aluminum nitride seed layer
AlN
GaN layer thickness | 5–50000 nm | GaN |
seed layer (AlN) thickness | 0.1–0.5 µm | AlN |