The electronic device of claim 1, wherein: the carrier accumulation layer has a first bandgap energy; the carrier ba tr er layer has a second bandgap energy; the channel layer has a third bandgap energy; and the second bandgap energy is greater than the third bandgap energy. Page 3 of 9 U.S. App. No.: 14/741,567

The electronic device of claim 1, wherein the carrier barrier layer is at least 1.5 times thicker than the carrier accumulation layer.

The electronic device of claim 1, further comprising a barrier layer overlying the channel layer.

The electronic device of claim 1, wherein the transistor at 150 ° C has a resistance reduction that is given by: ((RDSON-max-RD SON-VDS)/(RDSON-max)) * 100 %, wherein R DSON-max is a maximum on-state resistance a drain-to-source voltage is in a range of 0 to 700 V, and R DSON-VDS is an on-state resistance at a particular drain-to- source voltage (V DS); and wherein: when V DS is 300 V, the resistance reduction is at least 2%; when V DS is 400 V, the resistance reduction is at least 3%; when V DS is 500 V, the resistance reduction is at least 6%; when V DS is 600 V, the resistance reduction is at least 6%; or any combination thereof. Page 4 of 9 U.S. App. No.: 14/741,567

The electronic device of claim 1, further comprising: a ba rri er layer overlying the channel layer; a gate electrode of the transistor, wherein the barrier layer is disposed between the channel layer and the gate electrode; a source electrode of the transistor; and a drain electrode of the transistor, wherein: the carrier ba rri er layer abuts each of the carrier accumulation layer and the channel layer; the carrier accumulation layer includes A l X Ga(i _ X)N, wherein x is in a range of 0.08 to 0.12, has a concentration of a carrier impurity of a first ca rri er type that is at least 1x 18 atoms/cm 3, and has a thickness in a range of 200 nm to 300 nm; the carrier ba rri er layer includes A l X Ga(1 _ X)N, wherein x is in a range of 0.08 to 0. 12, has a concentration of a ca rri er impurity of the first carrier type that is no greater than 3x10 16 atoms/cm 3, and has a thickness in a range of 600 nm to 900 nm; the channel layer includes GaN, has a concentration of a carrier impurity of the first ca rri er type that is no greater than 3x10 16 atoms/cm 3, and has a thickness in a range of 110 nm to 300 nm; and the barrier layer includes Al X Ga(1 _ X)N, wherein x is in a range of 0.15 to 0.30, and has a thickness in a range of 5 nm to 40 nm. Page 5 of 9 U.S. App. No.: 14/741,567

The electronic device of claim 1, wherein the channel layer comprises carbon as a dopant.

The electronic device of claim 1, further comprising a superlattice structure SVG 14741567.09-20-2016.ITBXB₉GBRXEAPX4.CLM.4.21.1034.2379.1152.2416.svg 0.123 0.393 Chemistry Black and white comprising A l z Ga(- z)N, where 1.

The electronic device of claim 18, further comprising a barrier layer that includes Al X Ga(_ X)N, wherein x is in a range of 0.15 to 0.30.

The electronic device of claim 1, wherein: the carrier accumulation layer has a first bandgap energy; the carrier ba tr er layer has a second bandgap energy; the channel layer has a third bandgap energy; and the second bandgap energy is greater than the third bandgap energy. Page 3 of 9 U.S. App. No.: 14/741,567

The electronic device of claim 1, wherein the carrier barrier layer is at least 1.5 times thicker than the carrier accumulation layer.

The electronic device of claim 1, further comprising a barrier layer overlying the channel layer.

The electronic device of claim 1, wherein the transistor at 150 ° C has a resistance reduction that is given by: ((RDSON-max-RD SON-VDS)/(RDSON-max)) * 100 %, wherein R DSON-max is a maximum on-state resistance a drain-to-source voltage is in a range of 0 to 700 V, and R DSON-VDS is an on-state resistance at a particular drain-to- source voltage (V DS); and wherein: when V DS is 300 V, the resistance reduction is at least 2%; when V DS is 400 V, the resistance reduction is at least 3%; when V DS is 500 V, the resistance reduction is at least 6%; when V DS is 600 V, the resistance reduction is at least 6%; or any combination thereof. Page 4 of 9 U.S. App. No.: 14/741,567

The electronic device of claim 1, further comprising: a ba rri er layer overlying the channel layer; a gate electrode of the transistor, wherein the barrier layer is disposed between the channel layer and the gate electrode; a source electrode of the transistor; and a drain electrode of the transistor, wherein: the carrier ba rri er layer abuts each of the carrier accumulation layer and the channel layer; the carrier accumulation layer includes A l X Ga(i _ X)N, wherein x is in a range of 0.08 to 0.12, has a concentration of a carrier impurity of a first ca rri er type that is at least 1x 18 atoms/cm 3, and has a thickness in a range of 200 nm to 300 nm; the carrier ba rri er layer includes A l X Ga(1 _ X)N, wherein x is in a range of 0.08 to 0. 12, has a concentration of a ca rri er impurity of the first carrier type that is no greater than 3x10 16 atoms/cm 3, and has a thickness in a range of 600 nm to 900 nm; the channel layer includes GaN, has a concentration of a carrier impurity of the first ca rri er type that is no greater than 3x10 16 atoms/cm 3, and has a thickness in a range of 110 nm to 300 nm; and the barrier layer includes Al X Ga(1 _ X)N, wherein x is in a range of 0.15 to 0.30, and has a thickness in a range of 5 nm to 40 nm. Page 5 of 9 U.S. App. No.: 14/741,567

The electronic device of claim 1, wherein the channel layer comprises carbon as a dopant.

The electronic device of claim 1, further comprising a superlattice structure SVG 14741567.09-20-2016.ITBXB₉GBRXEAPX4.CLM.4.21.1034.2379.1152.2416.svg 0.123 0.393 Chemistry Black and white comprising A l z Ga(- z)N, where 1.

The electronic device of claim 18, further comprising a barrier layer that includes Al X Ga(_ X)N, wherein x is in a range of 0.15 to 0.30.

The electronic device of claim 1, wherein: the carrier accumulation layer has a first bandgap energy; the carrier ba tr er layer has a second bandgap energy; the channel layer has a third bandgap energy; and the second bandgap energy is greater than the third bandgap energy. Page 3 of 9 U.S. App. No.: 14/741,567

The electronic device of claim 1, wherein the carrier barrier layer is at least 1.5 times thicker than the carrier accumulation layer.

The electronic device of claim 1, further comprising a barrier layer overlying the channel layer.

The electronic device of claim 1, wherein the transistor at 150 ° C has a resistance reduction that is given by: ((RDSON-max-RD SON-VDS)/(RDSON-max)) * 100 %, wherein R DSON-max is a maximum on-state resistance a drain-to-source voltage is in a range of 0 to 700 V, and R DSON-VDS is an on-state resistance at a particular drain-to- source voltage (V DS); and wherein: when V DS is 300 V, the resistance reduction is at least 2%; when V DS is 400 V, the resistance reduction is at least 3%; when V DS is 500 V, the resistance reduction is at least 6%; when V DS is 600 V, the resistance reduction is at least 6%; or any combination thereof. Page 4 of 9 U.S. App. No.: 14/741,567

The electronic device of claim 1, further comprising: a ba rri er layer overlying the channel layer; a gate electrode of the transistor, wherein the barrier layer is disposed between the channel layer and the gate electrode; a source electrode of the transistor; and a drain electrode of the transistor, wherein: the carrier ba rri er layer abuts each of the carrier accumulation layer and the channel layer; the carrier accumulation layer includes A l X Ga(i _ X)N, wherein x is in a range of 0.08 to 0.12, has a concentration of a carrier impurity of a first ca rri er type that is at least 1x 18 atoms/cm 3, and has a thickness in a range of 200 nm to 300 nm; the carrier ba rri er layer includes A l X Ga(1 _ X)N, wherein x is in a range of 0.08 to 0. 12, has a concentration of a ca rri er impurity of the first carrier type that is no greater than 3x10 16 atoms/cm 3, and has a thickness in a range of 600 nm to 900 nm; the channel layer includes GaN, has a concentration of a carrier impurity of the first ca rri er type that is no greater than 3x10 16 atoms/cm 3, and has a thickness in a range of 110 nm to 300 nm; and the barrier layer includes Al X Ga(1 _ X)N, wherein x is in a range of 0.15 to 0.30, and has a thickness in a range of 5 nm to 40 nm. Page 5 of 9 U.S. App. No.: 14/741,567

The electronic device of claim 1, wherein the channel layer comprises carbon as a dopant.

The electronic device of claim 1, further comprising a superlattice structure SVG 14741567.09-20-2016.ITBXB₉GBRXEAPX4.CLM.4.21.1034.2379.1152.2416.svg 0.123 0.393 Chemistry Black and white comprising A l z Ga(- z)N, where 1.

The electronic device of claim 18, further comprising a barrier layer that includes Al X Ga(_ X)N, wherein x is in a range of 0.15 to 0.30.

The electronic device of claim 1, wherein: the carrier accumulation layer has a first bandgap energy; the carrier ba tr er layer has a second bandgap energy; the channel layer has a third bandgap energy; and the second bandgap energy is greater than the third bandgap energy. Page 3 of 9 U.S. App. No.: 14/741,567

The electronic device of claim 1, wherein the carrier barrier layer is at least 1.5 times thicker than the carrier accumulation layer.

The electronic device of claim 1, further comprising a barrier layer overlying the channel layer.

The electronic device of claim 1, wherein the transistor at 150 ° C has a resistance reduction that is given by: ((RDSON-max-RD SON-VDS)/(RDSON-max)) * 100 %, wherein R DSON-max is a maximum on-state resistance a drain-to-source voltage is in a range of 0 to 700 V, and R DSON-VDS is an on-state resistance at a particular drain-to- source voltage (V DS); and wherein: when V DS is 300 V, the resistance reduction is at least 2%; when V DS is 400 V, the resistance reduction is at least 3%; when V DS is 500 V, the resistance reduction is at least 6%; when V DS is 600 V, the resistance reduction is at least 6%; or any combination thereof. Page 4 of 9 U.S. App. No.: 14/741,567

The electronic device of claim 1, further comprising: a ba rri er layer overlying the channel layer; a gate electrode of the transistor, wherein the barrier layer is disposed between the channel layer and the gate electrode; a source electrode of the transistor; and a drain electrode of the transistor, wherein: the carrier ba rri er layer abuts each of the carrier accumulation layer and the channel layer; the carrier accumulation layer includes A l X Ga(i _ X)N, wherein x is in a range of 0.08 to 0.12, has a concentration of a carrier impurity of a first ca rri er type that is at least 1x 18 atoms/cm 3, and has a thickness in a range of 200 nm to 300 nm; the carrier ba rri er layer includes A l X Ga(1 _ X)N, wherein x is in a range of 0.08 to 0. 12, has a concentration of a ca rri er impurity of the first carrier type that is no greater than 3x10 16 atoms/cm 3, and has a thickness in a range of 600 nm to 900 nm; the channel layer includes GaN, has a concentration of a carrier impurity of the first ca rri er type that is no greater than 3x10 16 atoms/cm 3, and has a thickness in a range of 110 nm to 300 nm; and the barrier layer includes Al X Ga(1 _ X)N, wherein x is in a range of 0.15 to 0.30, and has a thickness in a range of 5 nm to 40 nm. Page 5 of 9 U.S. App. No.: 14/741,567

The electronic device of claim 1, wherein the channel layer comprises carbon as a dopant.

The electronic device of claim 1, further comprising a superlattice structure SVG 14741567.09-20-2016.ITBXB₉GBRXEAPX4.CLM.4.21.1034.2379.1152.2416.svg 0.123 0.393 Chemistry Black and white comprising A l z Ga(- z)N, where 1.

The electronic device of claim 18, further comprising a barrier layer that includes Al X Ga(_ X)N, wherein x is in a range of 0.15 to 0.30.