Patent
US 11,195,944GALLIUM NITRIDE (GaN) TRANSISTOR STRUCTURES ON A SUBSTRATE
HAN WUI THEN
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,195,944Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a method of forming an integrated circuit, in accordance with various embodiments of the present disclosure.
Figures 2A-F illustrate example structures that are formed when carrying out the method of
Figure 2F' illustrates a cross-section through a channel region of a finned non-planar multiple-quantum well (MQW) gallium nitride (GaN) transistor structure, in accordance with an embodiment of the present disclosure.
Figure 3 is a transmission electron microscopy (TEM) image illustrating a cross-sectional side view of an integrated circuit structure formed in accordance with an embodiment of the present disclosure.
Figure 4 illustrates a functional block diagram of a system-on-chip (So C) implementation of a mobile computing platform, in accordance with various embodiments of the present disclosure.
Figure 5 illustrates a computing system implemented with integrated circuit structures or devices formed using the techniques disclosed herein, in accordance with various embodiments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a bulk substrate including semiconductor material; a plurality of fins native to the bulk substrate, wherein at least one of the fins includes an oxidized portion and an unoxidized portion above the oxidized portion; a structure including gallium and nitrogen, the structure directly on at least some of the fins and above the oxidized portion of the at least one fin; and a transistor having a gate stack on the structure, such that the gate stack overlaps the structure in a plan view. Currently amended
The integrated circuit of claim 1, wherein the bulk substrate is one of a silicon bulk substrate, a silicon germanium bulk substrate, or a germanium bulk substrate. Currently amended
The integrated circuit of claim 1, wherein the structure includes a first layer and a second layer, the first layer including gallium and nitrogen, and the second layer is at least partially between some of the fins and the first layer, wherein the second layer includes aluminum and nitrogen. Previously presented
The integrated circuit of claim 1, wherein the structure includes a first layer and a second layer, the first layer including gallium and nitrogen, and the second layer at least partially between some of the fins and the first layer, wherein the second layer includes gallium and nitrogen. Currently amended
The integrated circuit of claim 1, wherein the structure includes a first layer and a second layer, the first layer including gallium and nitrogen, and the second layer is a graded layer above the first layer, the graded layer including a change in content of at least one material. Previously presented
The integrated circuit of claim 1, further comprising a source region and a drain region, the source and drain regions including gallium and nitrogen, the source and drain regions further including an n-type dopant. Previously presented
The integrated circuit of claim 1, wherein the transistor is electrically isolated from the substrate by way of the oxidized portion of the at least one fin. Previously presented
The integrated circuit of claim 1, wherein the transistor includes at least one of: a planar configuration, a non-planar configuration, a finned configuration, a t ri -gate configuration, a nanowire configuration, a gate-all-around configuration, high-electron- mobility transistor (HEMT) architecture, pseudomorphic HEMT (pHEMT) architecture, two- dimensional electron gas (2DEG) architecture, three-dimensional electron gas (3DEG) architecture, three-dimensional polarization field-effect transistor (F ET) architecture, multiple quantum-well (MQW) architecture, an enhancement mode configuration, or super-lattice architecture. Previously presented
A system-on-chip including a radio frequency (R F) switch, the R F switch comprising the integrated circuit of claim 1. Previously presented
A computing system comprising the integrated circuit of claim 1. Previously presented
The integrated circuit of claim [[1]] 4, wherein,,,, the transistor includes the second layer. Currently amended
The integrated circuit of claim 5, further comprising an aluminum-including layer above the second layer. Previously presented
Canceled
An integrated circuit comprising: a layer including gallium and nitrogen, the layer over one or more fins, each of the one or more fins native to a subjacent bulk silicon (Si) substrate and including an oxidized portion and an unoxidized portion above the oxidized portion, such that the layer is electrically isolated from the Si substrate by the corresponding oxidized portion; and a gate stack over a portion of the layer. Previously presented
The integrated circuit of claim 16, further comprising an additional layer at least partially between at least one of the one or more fins and the layer, wherein the additional layer includes aluminum and nitrogen. Previously presented
The integrated circuit of claim 16, wherein the layer and the gate stack are part of a transistor that includes at least one of: a planar configuration, a non-planar configuration, a finned configuration, a t ri -gate configuration, a nanowire configuration, a gate- all-around configuration, high-electron-mobility transistor (HEMT) architecture, pseudomorphic H EMT (p H EMT) architecture, two-dimensional electron gas (2DEG) architecture, three- dimensional electron gas (3DEG) architecture, three-dimensional polarization field-effect transistor (F ET) architecture, multiple quantum-well (MQW) architecture, an enhancement mode configuration, or super-lattice architecture. Previously presented
The integrated circuit of claim 16, wherein the layer is over at least a portion of the sidewalls of the one or more fins and on a top surface of the one or more fins. Previously presented
Canceled
20-25. Canceled
Canceled
An integrated circuit including at least one transistor, the integrated circuit comprising: a bulk silicon substrate; Title: GALLIUM NITRIDE (GaN) TRANSISTOR STRUCTURES ON A SUBSTRATE first and second fins native to the substrate, wherein each of the first and second fins includes an oxidized portion and an unoxidized portion above the oxidized portion; and a layer including gallium and nitrogen, the layer over at least a portion of the sides of the first fin and over a top surface of the second fin, wherein the oxidized portion of each of the first and second fins is between the layer and the substrate. Currently amended
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor on bulk substrate with oxidized fin isolation
GaN integrated circuit on bulk Si substrate with oxidized fin isolation and gate stack
Materials described outside the worked examples.
gallium nitride
GaN
oxidized fin portion
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 2F' illustrates a cross-section through a channel region of a finned non-planar multiple-quantum well (MQW) gallium nitride (GaN) transistor structure, in accordance with an embodiment of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.25–2.5 µm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,195,944Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a method of forming an integrated circuit, in accordance with various embodiments of the present disclosure.
Figures 2A-F illustrate example structures that are formed when carrying out the method of
Figure 2F' illustrates a cross-section through a channel region of a finned non-planar multiple-quantum well (MQW) gallium nitride (GaN) transistor structure, in accordance with an embodiment of the present disclosure.
Figure 3 is a transmission electron microscopy (TEM) image illustrating a cross-sectional side view of an integrated circuit structure formed in accordance with an embodiment of the present disclosure.
Figure 4 illustrates a functional block diagram of a system-on-chip (So C) implementation of a mobile computing platform, in accordance with various embodiments of the present disclosure.
Figure 5 illustrates a computing system implemented with integrated circuit structures or devices formed using the techniques disclosed herein, in accordance with various embodiments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a bulk substrate including semiconductor material; a plurality of fins native to the bulk substrate, wherein at least one of the fins includes an oxidized portion and an unoxidized portion above the oxidized portion; a structure including gallium and nitrogen, the structure directly on at least some of the fins and above the oxidized portion of the at least one fin; and a transistor having a gate stack on the structure, such that the gate stack overlaps the structure in a plan view. Currently amended
The integrated circuit of claim 1, wherein the bulk substrate is one of a silicon bulk substrate, a silicon germanium bulk substrate, or a germanium bulk substrate. Currently amended
The integrated circuit of claim 1, wherein the structure includes a first layer and a second layer, the first layer including gallium and nitrogen, and the second layer is at least partially between some of the fins and the first layer, wherein the second layer includes aluminum and nitrogen. Previously presented
The integrated circuit of claim 1, wherein the structure includes a first layer and a second layer, the first layer including gallium and nitrogen, and the second layer at least partially between some of the fins and the first layer, wherein the second layer includes gallium and nitrogen. Currently amended
The integrated circuit of claim 1, wherein the structure includes a first layer and a second layer, the first layer including gallium and nitrogen, and the second layer is a graded layer above the first layer, the graded layer including a change in content of at least one material. Previously presented
The integrated circuit of claim 1, further comprising a source region and a drain region, the source and drain regions including gallium and nitrogen, the source and drain regions further including an n-type dopant. Previously presented
The integrated circuit of claim 1, wherein the transistor is electrically isolated from the substrate by way of the oxidized portion of the at least one fin. Previously presented
The integrated circuit of claim 1, wherein the transistor includes at least one of: a planar configuration, a non-planar configuration, a finned configuration, a t ri -gate configuration, a nanowire configuration, a gate-all-around configuration, high-electron- mobility transistor (HEMT) architecture, pseudomorphic HEMT (pHEMT) architecture, two- dimensional electron gas (2DEG) architecture, three-dimensional electron gas (3DEG) architecture, three-dimensional polarization field-effect transistor (F ET) architecture, multiple quantum-well (MQW) architecture, an enhancement mode configuration, or super-lattice architecture. Previously presented
A system-on-chip including a radio frequency (R F) switch, the R F switch comprising the integrated circuit of claim 1. Previously presented
A computing system comprising the integrated circuit of claim 1. Previously presented
The integrated circuit of claim [[1]] 4, wherein,,,, the transistor includes the second layer. Currently amended
The integrated circuit of claim 5, further comprising an aluminum-including layer above the second layer. Previously presented
Canceled
An integrated circuit comprising: a layer including gallium and nitrogen, the layer over one or more fins, each of the one or more fins native to a subjacent bulk silicon (Si) substrate and including an oxidized portion and an unoxidized portion above the oxidized portion, such that the layer is electrically isolated from the Si substrate by the corresponding oxidized portion; and a gate stack over a portion of the layer. Previously presented
The integrated circuit of claim 16, further comprising an additional layer at least partially between at least one of the one or more fins and the layer, wherein the additional layer includes aluminum and nitrogen. Previously presented
The integrated circuit of claim 16, wherein the layer and the gate stack are part of a transistor that includes at least one of: a planar configuration, a non-planar configuration, a finned configuration, a t ri -gate configuration, a nanowire configuration, a gate- all-around configuration, high-electron-mobility transistor (HEMT) architecture, pseudomorphic H EMT (p H EMT) architecture, two-dimensional electron gas (2DEG) architecture, three- dimensional electron gas (3DEG) architecture, three-dimensional polarization field-effect transistor (F ET) architecture, multiple quantum-well (MQW) architecture, an enhancement mode configuration, or super-lattice architecture. Previously presented
The integrated circuit of claim 16, wherein the layer is over at least a portion of the sidewalls of the one or more fins and on a top surface of the one or more fins. Previously presented
Canceled
20-25. Canceled
Canceled
An integrated circuit including at least one transistor, the integrated circuit comprising: a bulk silicon substrate; Title: GALLIUM NITRIDE (GaN) TRANSISTOR STRUCTURES ON A SUBSTRATE first and second fins native to the substrate, wherein each of the first and second fins includes an oxidized portion and an unoxidized portion above the oxidized portion; and a layer including gallium and nitrogen, the layer over at least a portion of the sides of the first fin and over a top surface of the second fin, wherein the oxidized portion of each of the first and second fins is between the layer and the substrate. Currently amended
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor on bulk substrate with oxidized fin isolation
GaN integrated circuit on bulk Si substrate with oxidized fin isolation and gate stack
Materials described outside the worked examples.
gallium nitride
GaN
oxidized fin portion
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 2F' illustrates a cross-section through a channel region of a finned non-planar multiple-quantum well (MQW) gallium nitride (GaN) transistor structure, in accordance with an embodiment of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.25–2.5 µm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,195,944Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a method of forming an integrated circuit, in accordance with various embodiments of the present disclosure.
Figures 2A-F illustrate example structures that are formed when carrying out the method of
Figure 2F' illustrates a cross-section through a channel region of a finned non-planar multiple-quantum well (MQW) gallium nitride (GaN) transistor structure, in accordance with an embodiment of the present disclosure.
Figure 3 is a transmission electron microscopy (TEM) image illustrating a cross-sectional side view of an integrated circuit structure formed in accordance with an embodiment of the present disclosure.
Figure 4 illustrates a functional block diagram of a system-on-chip (So C) implementation of a mobile computing platform, in accordance with various embodiments of the present disclosure.
Figure 5 illustrates a computing system implemented with integrated circuit structures or devices formed using the techniques disclosed herein, in accordance with various embodiments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a bulk substrate including semiconductor material; a plurality of fins native to the bulk substrate, wherein at least one of the fins includes an oxidized portion and an unoxidized portion above the oxidized portion; a structure including gallium and nitrogen, the structure directly on at least some of the fins and above the oxidized portion of the at least one fin; and a transistor having a gate stack on the structure, such that the gate stack overlaps the structure in a plan view. Currently amended
The integrated circuit of claim 1, wherein the bulk substrate is one of a silicon bulk substrate, a silicon germanium bulk substrate, or a germanium bulk substrate. Currently amended
The integrated circuit of claim 1, wherein the structure includes a first layer and a second layer, the first layer including gallium and nitrogen, and the second layer is at least partially between some of the fins and the first layer, wherein the second layer includes aluminum and nitrogen. Previously presented
The integrated circuit of claim 1, wherein the structure includes a first layer and a second layer, the first layer including gallium and nitrogen, and the second layer at least partially between some of the fins and the first layer, wherein the second layer includes gallium and nitrogen. Currently amended
The integrated circuit of claim 1, wherein the structure includes a first layer and a second layer, the first layer including gallium and nitrogen, and the second layer is a graded layer above the first layer, the graded layer including a change in content of at least one material. Previously presented
The integrated circuit of claim 1, further comprising a source region and a drain region, the source and drain regions including gallium and nitrogen, the source and drain regions further including an n-type dopant. Previously presented
The integrated circuit of claim 1, wherein the transistor is electrically isolated from the substrate by way of the oxidized portion of the at least one fin. Previously presented
The integrated circuit of claim 1, wherein the transistor includes at least one of: a planar configuration, a non-planar configuration, a finned configuration, a t ri -gate configuration, a nanowire configuration, a gate-all-around configuration, high-electron- mobility transistor (HEMT) architecture, pseudomorphic HEMT (pHEMT) architecture, two- dimensional electron gas (2DEG) architecture, three-dimensional electron gas (3DEG) architecture, three-dimensional polarization field-effect transistor (F ET) architecture, multiple quantum-well (MQW) architecture, an enhancement mode configuration, or super-lattice architecture. Previously presented
A system-on-chip including a radio frequency (R F) switch, the R F switch comprising the integrated circuit of claim 1. Previously presented
A computing system comprising the integrated circuit of claim 1. Previously presented
The integrated circuit of claim [[1]] 4, wherein,,,, the transistor includes the second layer. Currently amended
The integrated circuit of claim 5, further comprising an aluminum-including layer above the second layer. Previously presented
Canceled
An integrated circuit comprising: a layer including gallium and nitrogen, the layer over one or more fins, each of the one or more fins native to a subjacent bulk silicon (Si) substrate and including an oxidized portion and an unoxidized portion above the oxidized portion, such that the layer is electrically isolated from the Si substrate by the corresponding oxidized portion; and a gate stack over a portion of the layer. Previously presented
The integrated circuit of claim 16, further comprising an additional layer at least partially between at least one of the one or more fins and the layer, wherein the additional layer includes aluminum and nitrogen. Previously presented
The integrated circuit of claim 16, wherein the layer and the gate stack are part of a transistor that includes at least one of: a planar configuration, a non-planar configuration, a finned configuration, a t ri -gate configuration, a nanowire configuration, a gate- all-around configuration, high-electron-mobility transistor (HEMT) architecture, pseudomorphic H EMT (p H EMT) architecture, two-dimensional electron gas (2DEG) architecture, three- dimensional electron gas (3DEG) architecture, three-dimensional polarization field-effect transistor (F ET) architecture, multiple quantum-well (MQW) architecture, an enhancement mode configuration, or super-lattice architecture. Previously presented
The integrated circuit of claim 16, wherein the layer is over at least a portion of the sidewalls of the one or more fins and on a top surface of the one or more fins. Previously presented
Canceled
20-25. Canceled
Canceled
An integrated circuit including at least one transistor, the integrated circuit comprising: a bulk silicon substrate; Title: GALLIUM NITRIDE (GaN) TRANSISTOR STRUCTURES ON A SUBSTRATE first and second fins native to the substrate, wherein each of the first and second fins includes an oxidized portion and an unoxidized portion above the oxidized portion; and a layer including gallium and nitrogen, the layer over at least a portion of the sides of the first fin and over a top surface of the second fin, wherein the oxidized portion of each of the first and second fins is between the layer and the substrate. Currently amended
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor on bulk substrate with oxidized fin isolation
GaN integrated circuit on bulk Si substrate with oxidized fin isolation and gate stack
Materials described outside the worked examples.
gallium nitride
GaN
oxidized fin portion
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 2F' illustrates a cross-section through a channel region of a finned non-planar multiple-quantum well (MQW) gallium nitride (GaN) transistor structure, in accordance with an embodiment of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.25–2.5 µm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,195,944Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a method of forming an integrated circuit, in accordance with various embodiments of the present disclosure.
Figures 2A-F illustrate example structures that are formed when carrying out the method of
Figure 2F' illustrates a cross-section through a channel region of a finned non-planar multiple-quantum well (MQW) gallium nitride (GaN) transistor structure, in accordance with an embodiment of the present disclosure.
Figure 3 is a transmission electron microscopy (TEM) image illustrating a cross-sectional side view of an integrated circuit structure formed in accordance with an embodiment of the present disclosure.
Figure 4 illustrates a functional block diagram of a system-on-chip (So C) implementation of a mobile computing platform, in accordance with various embodiments of the present disclosure.
Figure 5 illustrates a computing system implemented with integrated circuit structures or devices formed using the techniques disclosed herein, in accordance with various embodiments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a bulk substrate including semiconductor material; a plurality of fins native to the bulk substrate, wherein at least one of the fins includes an oxidized portion and an unoxidized portion above the oxidized portion; a structure including gallium and nitrogen, the structure directly on at least some of the fins and above the oxidized portion of the at least one fin; and a transistor having a gate stack on the structure, such that the gate stack overlaps the structure in a plan view. Currently amended
The integrated circuit of claim 1, wherein the bulk substrate is one of a silicon bulk substrate, a silicon germanium bulk substrate, or a germanium bulk substrate. Currently amended
The integrated circuit of claim 1, wherein the structure includes a first layer and a second layer, the first layer including gallium and nitrogen, and the second layer is at least partially between some of the fins and the first layer, wherein the second layer includes aluminum and nitrogen. Previously presented
The integrated circuit of claim 1, wherein the structure includes a first layer and a second layer, the first layer including gallium and nitrogen, and the second layer at least partially between some of the fins and the first layer, wherein the second layer includes gallium and nitrogen. Currently amended
The integrated circuit of claim 1, wherein the structure includes a first layer and a second layer, the first layer including gallium and nitrogen, and the second layer is a graded layer above the first layer, the graded layer including a change in content of at least one material. Previously presented
The integrated circuit of claim 1, further comprising a source region and a drain region, the source and drain regions including gallium and nitrogen, the source and drain regions further including an n-type dopant. Previously presented
The integrated circuit of claim 1, wherein the transistor is electrically isolated from the substrate by way of the oxidized portion of the at least one fin. Previously presented
The integrated circuit of claim 1, wherein the transistor includes at least one of: a planar configuration, a non-planar configuration, a finned configuration, a t ri -gate configuration, a nanowire configuration, a gate-all-around configuration, high-electron- mobility transistor (HEMT) architecture, pseudomorphic HEMT (pHEMT) architecture, two- dimensional electron gas (2DEG) architecture, three-dimensional electron gas (3DEG) architecture, three-dimensional polarization field-effect transistor (F ET) architecture, multiple quantum-well (MQW) architecture, an enhancement mode configuration, or super-lattice architecture. Previously presented
A system-on-chip including a radio frequency (R F) switch, the R F switch comprising the integrated circuit of claim 1. Previously presented
A computing system comprising the integrated circuit of claim 1. Previously presented
The integrated circuit of claim [[1]] 4, wherein,,,, the transistor includes the second layer. Currently amended
The integrated circuit of claim 5, further comprising an aluminum-including layer above the second layer. Previously presented
Canceled
An integrated circuit comprising: a layer including gallium and nitrogen, the layer over one or more fins, each of the one or more fins native to a subjacent bulk silicon (Si) substrate and including an oxidized portion and an unoxidized portion above the oxidized portion, such that the layer is electrically isolated from the Si substrate by the corresponding oxidized portion; and a gate stack over a portion of the layer. Previously presented
The integrated circuit of claim 16, further comprising an additional layer at least partially between at least one of the one or more fins and the layer, wherein the additional layer includes aluminum and nitrogen. Previously presented
The integrated circuit of claim 16, wherein the layer and the gate stack are part of a transistor that includes at least one of: a planar configuration, a non-planar configuration, a finned configuration, a t ri -gate configuration, a nanowire configuration, a gate- all-around configuration, high-electron-mobility transistor (HEMT) architecture, pseudomorphic H EMT (p H EMT) architecture, two-dimensional electron gas (2DEG) architecture, three- dimensional electron gas (3DEG) architecture, three-dimensional polarization field-effect transistor (F ET) architecture, multiple quantum-well (MQW) architecture, an enhancement mode configuration, or super-lattice architecture. Previously presented
The integrated circuit of claim 16, wherein the layer is over at least a portion of the sidewalls of the one or more fins and on a top surface of the one or more fins. Previously presented
Canceled
20-25. Canceled
Canceled
An integrated circuit including at least one transistor, the integrated circuit comprising: a bulk silicon substrate; Title: GALLIUM NITRIDE (GaN) TRANSISTOR STRUCTURES ON A SUBSTRATE first and second fins native to the substrate, wherein each of the first and second fins includes an oxidized portion and an unoxidized portion above the oxidized portion; and a layer including gallium and nitrogen, the layer over at least a portion of the sides of the first fin and over a top surface of the second fin, wherein the oxidized portion of each of the first and second fins is between the layer and the substrate. Currently amended
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor on bulk substrate with oxidized fin isolation
GaN integrated circuit on bulk Si substrate with oxidized fin isolation and gate stack
Materials described outside the worked examples.
gallium nitride
GaN
oxidized fin portion
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 2F' illustrates a cross-section through a channel region of a finned non-planar multiple-quantum well (MQW) gallium nitride (GaN) transistor structure, in accordance with an embodiment of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.25–2.5 µm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
GaN transistor on bulk Si with first and second fins and oxidized portion isolation
silicon germanium
SiGe
germanium
Ge
aluminum nitride
AlN
indium gallium nitride
InGaN
aluminum gallium nitride
AlGaN
indium aluminum nitride
InAlN
indium aluminum gallium nitride
InAlGaN
Figure 3 is a transmission electron microscopy (TEM) image illustrating a cross-sectional side view of an integrated circuit structure formed in accordance with an embodiment of the present disclosure.
| — |
Thickness | ≤ 50 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 20 nm | — |
GaN transistor on bulk Si with first and second fins and oxidized portion isolation
silicon germanium
SiGe
germanium
Ge
aluminum nitride
AlN
indium gallium nitride
InGaN
aluminum gallium nitride
AlGaN
indium aluminum nitride
InAlN
indium aluminum gallium nitride
InAlGaN
Figure 3 is a transmission electron microscopy (TEM) image illustrating a cross-sectional side view of an integrated circuit structure formed in accordance with an embodiment of the present disclosure.
| — |
Thickness | ≤ 50 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 20 nm | — |
GaN transistor on bulk Si with first and second fins and oxidized portion isolation
silicon germanium
SiGe
germanium
Ge
aluminum nitride
AlN
indium gallium nitride
InGaN
aluminum gallium nitride
AlGaN
indium aluminum nitride
InAlN
indium aluminum gallium nitride
InAlGaN
Figure 3 is a transmission electron microscopy (TEM) image illustrating a cross-sectional side view of an integrated circuit structure formed in accordance with an embodiment of the present disclosure.
| — |
Thickness | ≤ 50 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 20 nm | — |
GaN transistor on bulk Si with first and second fins and oxidized portion isolation
silicon germanium
SiGe
germanium
Ge
aluminum nitride
AlN
indium gallium nitride
InGaN
aluminum gallium nitride
AlGaN
indium aluminum nitride
InAlN
indium aluminum gallium nitride
InAlGaN
Figure 3 is a transmission electron microscopy (TEM) image illustrating a cross-sectional side view of an integrated circuit structure formed in accordance with an embodiment of the present disclosure.
| — |
Thickness | ≤ 50 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 20 nm | — |