Patent
US 10,600,787SILICON PMOS WITH GALLIUM NITRIDE NMOS FOR VOLTAGE REGULATION
Sansaptak Dasgupta
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,600,787Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a communications device that includes a gallium nitride transistor formed on a silicon 111 substrate in accordance with …
FIG. 2 is a schematic illustration of a stereographic representation of a silicon 111 wafer and notch locations in accordance with embodiments of the present …
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 4 is a schematic diagram of a perspective view of a silicon 111 substrate showing crystal structure directions in accordance with embodiments of the …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 6 is an interposer implementing one or more embodiments of the invention in accordance with embodiments of the present disclosure. [0009]
FIG. 7 is a computing device built in accordance with an embodiment of the invention in accordance with embodiments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An apparatus comprising: a silicon substrate comprising a trench; a gallium nitride material in the trench of the silicon substrate; a source electrode on the gallium nitride material; a drain electrode on the gallium nitride material; a gate electrode on the gallium nitride material between the source electrode and the drain electrode; and an island of oxide in the trench, the island of oxide having a long axis in a direction substantially parallel to a [11-2] direction of the silicon substrate and being ad i acent to a further trench, wherein the further trench exposes one or both of the silicon substrate and a gallium nitride seed layer on the silicon substrate, and wherein the further trench is filled with the gallium nitride material. Currently amended
The apparatus of claim 1, wherein the silicon substrate is a silicon 111 substrate. Previously presented
The apparatus of claim 1, further comprising a first polarization layer over a portion of the gallium nitride material between the source electrode and the gate electrode, and a second polarization layer over a portion of the ga ll ium nitride material between the gate electrode and the drain electrode. New
The apparatus of claim 1, wherein the gate electrode has a long axis in the direction substantially parallel to the [11-2] direction of the silicon substrate. New
The apparatus of claim 1, wherein the source electrode has a long axis in the direction substantially parallel to a [11-2] direction of the silicon substrate. New
The apparatus of claim 1, wherein the drain electrode has a long axis in the direction substantially parallel to a [11-2] direction of the silicon substrate. New
The apparatus of claim 1, wherein a sidewall of the trench is a silicon (110) sidewall. New
The apparatus of claim 1, wherein the island of oxide is one of a plurality of islands of oxide in the trench, each island of oxide having a long axis in the direction substantia lly parallel to the [11-2] direction of the silicon substrate. New
The apparatus of claim 1, wherein the apparatus is one of a voltage regulator, a power amplifier, a computing device, and a processor. New
The apparatus of claim [[1]] 26, further comprising an oxide layer over each of the source electrode, the drain electrode, the first polarization layer, and the second polarization layer. Currently amended
The apparatus of claim 2, further comprising a polysilicon layer [[on]]over the oxide layer. Currently amended
Canceled
The apparatus of claim 5, wherein the island of oxide comprises a shallow trench isolation oxide. Currently amended
The apparatus of claim [[5]] 1, wherein [[a]]the gallium nitride seed layer is on the silicon substrate in the further trench adjacent to the island of oxide, the gallium nitride material being on the seed layer. Currently amended
The apparatus of claim [[1]] 26, further comprising a two dimensional electron gas (2DEG) at an interface between the gallium nitride material and the first polarization layer; and a 2DEG at an interface between the gallium nitride material and the second polarization layer. Currently amended
10-25. Canceled
Canceled
An apparatus comprising: a silicon substrate comprising a trench; a gallium nitride material in the trench of the silicon substrate; a source electrode on the gallium nitride material; a drain electrode on the gallium nitride material; a gate electrode on the gallium nitride material between the source electrode and the drain electrode; a first polarization layer over a portion of the gallium nitride material between the source electrode and the gate electrode, and a second polarization layer over a portion of the gallium nitride material between the gate electrode and the drain electrode; and an oxide layer over each of the source electrode, the drain electrode, the first polarization layer, and the second polarization layer. New
The apparatus of claim 34, further comprising a polysilicon layer over the oxide layer. New
The apparatus of claim 34, wherein at least one of the gate electrode, the source electrode, and the drain electrode has a long axis in a direction substantially parallel to a [11-2] direction of the silicon substrate. New
The apparatus of claim 34, wherein a sidewall of the trench is a silicon (110) sidewall. New
The apparatus of claim 34, wherein the apparatus is one of a voltage regulator, a power amplifier, a computing device, and a processor. New
An apparatus comprising: a silicon substrate comprising a trench; a gallium nitride material in the trench of the silicon substrate; a source electrode on the gallium nitride material; a drain electrode on the gallium nitride material; and a gate electrode on the gallium nitride material between the source electrode and the drain electrode, wherein at least one of the gate electrode, the source electrode, and the drain electrode has a long axis in a direction substantially parallel to a [11-2] direction of the silicon substrate. New
The apparatus of claim 40, wherein the silicon substrate is a silicon 111 substrate. New
The apparatus of claim 40, wherein the apparatus is one of a voltage regulator, a power amplifier, a computing device, and a processor. New
Layer stacks claimed or described, ordered top of device to substrate.
GaN NMOS transistor in silicon trench
Materials described outside the worked examples.
gallium nitride material
GaN
silicon substrate
Si
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic diagram of a communications device that includes a gallium nitride transistor formed on a silicon 111 substrate in accordance with …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,600,787Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a communications device that includes a gallium nitride transistor formed on a silicon 111 substrate in accordance with …
FIG. 2 is a schematic illustration of a stereographic representation of a silicon 111 wafer and notch locations in accordance with embodiments of the present …
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 4 is a schematic diagram of a perspective view of a silicon 111 substrate showing crystal structure directions in accordance with embodiments of the …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 6 is an interposer implementing one or more embodiments of the invention in accordance with embodiments of the present disclosure. [0009]
FIG. 7 is a computing device built in accordance with an embodiment of the invention in accordance with embodiments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An apparatus comprising: a silicon substrate comprising a trench; a gallium nitride material in the trench of the silicon substrate; a source electrode on the gallium nitride material; a drain electrode on the gallium nitride material; a gate electrode on the gallium nitride material between the source electrode and the drain electrode; and an island of oxide in the trench, the island of oxide having a long axis in a direction substantially parallel to a [11-2] direction of the silicon substrate and being ad i acent to a further trench, wherein the further trench exposes one or both of the silicon substrate and a gallium nitride seed layer on the silicon substrate, and wherein the further trench is filled with the gallium nitride material. Currently amended
The apparatus of claim 1, wherein the silicon substrate is a silicon 111 substrate. Previously presented
The apparatus of claim 1, further comprising a first polarization layer over a portion of the gallium nitride material between the source electrode and the gate electrode, and a second polarization layer over a portion of the ga ll ium nitride material between the gate electrode and the drain electrode. New
The apparatus of claim 1, wherein the gate electrode has a long axis in the direction substantially parallel to the [11-2] direction of the silicon substrate. New
The apparatus of claim 1, wherein the source electrode has a long axis in the direction substantially parallel to a [11-2] direction of the silicon substrate. New
The apparatus of claim 1, wherein the drain electrode has a long axis in the direction substantially parallel to a [11-2] direction of the silicon substrate. New
The apparatus of claim 1, wherein a sidewall of the trench is a silicon (110) sidewall. New
The apparatus of claim 1, wherein the island of oxide is one of a plurality of islands of oxide in the trench, each island of oxide having a long axis in the direction substantia lly parallel to the [11-2] direction of the silicon substrate. New
The apparatus of claim 1, wherein the apparatus is one of a voltage regulator, a power amplifier, a computing device, and a processor. New
The apparatus of claim [[1]] 26, further comprising an oxide layer over each of the source electrode, the drain electrode, the first polarization layer, and the second polarization layer. Currently amended
The apparatus of claim 2, further comprising a polysilicon layer [[on]]over the oxide layer. Currently amended
Canceled
The apparatus of claim 5, wherein the island of oxide comprises a shallow trench isolation oxide. Currently amended
The apparatus of claim [[5]] 1, wherein [[a]]the gallium nitride seed layer is on the silicon substrate in the further trench adjacent to the island of oxide, the gallium nitride material being on the seed layer. Currently amended
The apparatus of claim [[1]] 26, further comprising a two dimensional electron gas (2DEG) at an interface between the gallium nitride material and the first polarization layer; and a 2DEG at an interface between the gallium nitride material and the second polarization layer. Currently amended
10-25. Canceled
Canceled
An apparatus comprising: a silicon substrate comprising a trench; a gallium nitride material in the trench of the silicon substrate; a source electrode on the gallium nitride material; a drain electrode on the gallium nitride material; a gate electrode on the gallium nitride material between the source electrode and the drain electrode; a first polarization layer over a portion of the gallium nitride material between the source electrode and the gate electrode, and a second polarization layer over a portion of the gallium nitride material between the gate electrode and the drain electrode; and an oxide layer over each of the source electrode, the drain electrode, the first polarization layer, and the second polarization layer. New
The apparatus of claim 34, further comprising a polysilicon layer over the oxide layer. New
The apparatus of claim 34, wherein at least one of the gate electrode, the source electrode, and the drain electrode has a long axis in a direction substantially parallel to a [11-2] direction of the silicon substrate. New
The apparatus of claim 34, wherein a sidewall of the trench is a silicon (110) sidewall. New
The apparatus of claim 34, wherein the apparatus is one of a voltage regulator, a power amplifier, a computing device, and a processor. New
An apparatus comprising: a silicon substrate comprising a trench; a gallium nitride material in the trench of the silicon substrate; a source electrode on the gallium nitride material; a drain electrode on the gallium nitride material; and a gate electrode on the gallium nitride material between the source electrode and the drain electrode, wherein at least one of the gate electrode, the source electrode, and the drain electrode has a long axis in a direction substantially parallel to a [11-2] direction of the silicon substrate. New
The apparatus of claim 40, wherein the silicon substrate is a silicon 111 substrate. New
The apparatus of claim 40, wherein the apparatus is one of a voltage regulator, a power amplifier, a computing device, and a processor. New
Layer stacks claimed or described, ordered top of device to substrate.
GaN NMOS transistor in silicon trench
Materials described outside the worked examples.
gallium nitride material
GaN
silicon substrate
Si
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic diagram of a communications device that includes a gallium nitride transistor formed on a silicon 111 substrate in accordance with …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,600,787Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a communications device that includes a gallium nitride transistor formed on a silicon 111 substrate in accordance with …
FIG. 2 is a schematic illustration of a stereographic representation of a silicon 111 wafer and notch locations in accordance with embodiments of the present …
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 4 is a schematic diagram of a perspective view of a silicon 111 substrate showing crystal structure directions in accordance with embodiments of the …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 6 is an interposer implementing one or more embodiments of the invention in accordance with embodiments of the present disclosure. [0009]
FIG. 7 is a computing device built in accordance with an embodiment of the invention in accordance with embodiments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An apparatus comprising: a silicon substrate comprising a trench; a gallium nitride material in the trench of the silicon substrate; a source electrode on the gallium nitride material; a drain electrode on the gallium nitride material; a gate electrode on the gallium nitride material between the source electrode and the drain electrode; and an island of oxide in the trench, the island of oxide having a long axis in a direction substantially parallel to a [11-2] direction of the silicon substrate and being ad i acent to a further trench, wherein the further trench exposes one or both of the silicon substrate and a gallium nitride seed layer on the silicon substrate, and wherein the further trench is filled with the gallium nitride material. Currently amended
The apparatus of claim 1, wherein the silicon substrate is a silicon 111 substrate. Previously presented
The apparatus of claim 1, further comprising a first polarization layer over a portion of the gallium nitride material between the source electrode and the gate electrode, and a second polarization layer over a portion of the ga ll ium nitride material between the gate electrode and the drain electrode. New
The apparatus of claim 1, wherein the gate electrode has a long axis in the direction substantially parallel to the [11-2] direction of the silicon substrate. New
The apparatus of claim 1, wherein the source electrode has a long axis in the direction substantially parallel to a [11-2] direction of the silicon substrate. New
The apparatus of claim 1, wherein the drain electrode has a long axis in the direction substantially parallel to a [11-2] direction of the silicon substrate. New
The apparatus of claim 1, wherein a sidewall of the trench is a silicon (110) sidewall. New
The apparatus of claim 1, wherein the island of oxide is one of a plurality of islands of oxide in the trench, each island of oxide having a long axis in the direction substantia lly parallel to the [11-2] direction of the silicon substrate. New
The apparatus of claim 1, wherein the apparatus is one of a voltage regulator, a power amplifier, a computing device, and a processor. New
The apparatus of claim [[1]] 26, further comprising an oxide layer over each of the source electrode, the drain electrode, the first polarization layer, and the second polarization layer. Currently amended
The apparatus of claim 2, further comprising a polysilicon layer [[on]]over the oxide layer. Currently amended
Canceled
The apparatus of claim 5, wherein the island of oxide comprises a shallow trench isolation oxide. Currently amended
The apparatus of claim [[5]] 1, wherein [[a]]the gallium nitride seed layer is on the silicon substrate in the further trench adjacent to the island of oxide, the gallium nitride material being on the seed layer. Currently amended
The apparatus of claim [[1]] 26, further comprising a two dimensional electron gas (2DEG) at an interface between the gallium nitride material and the first polarization layer; and a 2DEG at an interface between the gallium nitride material and the second polarization layer. Currently amended
10-25. Canceled
Canceled
An apparatus comprising: a silicon substrate comprising a trench; a gallium nitride material in the trench of the silicon substrate; a source electrode on the gallium nitride material; a drain electrode on the gallium nitride material; a gate electrode on the gallium nitride material between the source electrode and the drain electrode; a first polarization layer over a portion of the gallium nitride material between the source electrode and the gate electrode, and a second polarization layer over a portion of the gallium nitride material between the gate electrode and the drain electrode; and an oxide layer over each of the source electrode, the drain electrode, the first polarization layer, and the second polarization layer. New
The apparatus of claim 34, further comprising a polysilicon layer over the oxide layer. New
The apparatus of claim 34, wherein at least one of the gate electrode, the source electrode, and the drain electrode has a long axis in a direction substantially parallel to a [11-2] direction of the silicon substrate. New
The apparatus of claim 34, wherein a sidewall of the trench is a silicon (110) sidewall. New
The apparatus of claim 34, wherein the apparatus is one of a voltage regulator, a power amplifier, a computing device, and a processor. New
An apparatus comprising: a silicon substrate comprising a trench; a gallium nitride material in the trench of the silicon substrate; a source electrode on the gallium nitride material; a drain electrode on the gallium nitride material; and a gate electrode on the gallium nitride material between the source electrode and the drain electrode, wherein at least one of the gate electrode, the source electrode, and the drain electrode has a long axis in a direction substantially parallel to a [11-2] direction of the silicon substrate. New
The apparatus of claim 40, wherein the silicon substrate is a silicon 111 substrate. New
The apparatus of claim 40, wherein the apparatus is one of a voltage regulator, a power amplifier, a computing device, and a processor. New
Layer stacks claimed or described, ordered top of device to substrate.
GaN NMOS transistor in silicon trench
Materials described outside the worked examples.
gallium nitride material
GaN
silicon substrate
Si
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic diagram of a communications device that includes a gallium nitride transistor formed on a silicon 111 substrate in accordance with …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,600,787Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a communications device that includes a gallium nitride transistor formed on a silicon 111 substrate in accordance with …
FIG. 2 is a schematic illustration of a stereographic representation of a silicon 111 wafer and notch locations in accordance with embodiments of the present …
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 4 is a schematic diagram of a perspective view of a silicon 111 substrate showing crystal structure directions in accordance with embodiments of the …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 6 is an interposer implementing one or more embodiments of the invention in accordance with embodiments of the present disclosure. [0009]
FIG. 7 is a computing device built in accordance with an embodiment of the invention in accordance with embodiments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An apparatus comprising: a silicon substrate comprising a trench; a gallium nitride material in the trench of the silicon substrate; a source electrode on the gallium nitride material; a drain electrode on the gallium nitride material; a gate electrode on the gallium nitride material between the source electrode and the drain electrode; and an island of oxide in the trench, the island of oxide having a long axis in a direction substantially parallel to a [11-2] direction of the silicon substrate and being ad i acent to a further trench, wherein the further trench exposes one or both of the silicon substrate and a gallium nitride seed layer on the silicon substrate, and wherein the further trench is filled with the gallium nitride material. Currently amended
The apparatus of claim 1, wherein the silicon substrate is a silicon 111 substrate. Previously presented
The apparatus of claim 1, further comprising a first polarization layer over a portion of the gallium nitride material between the source electrode and the gate electrode, and a second polarization layer over a portion of the ga ll ium nitride material between the gate electrode and the drain electrode. New
The apparatus of claim 1, wherein the gate electrode has a long axis in the direction substantially parallel to the [11-2] direction of the silicon substrate. New
The apparatus of claim 1, wherein the source electrode has a long axis in the direction substantially parallel to a [11-2] direction of the silicon substrate. New
The apparatus of claim 1, wherein the drain electrode has a long axis in the direction substantially parallel to a [11-2] direction of the silicon substrate. New
The apparatus of claim 1, wherein a sidewall of the trench is a silicon (110) sidewall. New
The apparatus of claim 1, wherein the island of oxide is one of a plurality of islands of oxide in the trench, each island of oxide having a long axis in the direction substantia lly parallel to the [11-2] direction of the silicon substrate. New
The apparatus of claim 1, wherein the apparatus is one of a voltage regulator, a power amplifier, a computing device, and a processor. New
The apparatus of claim [[1]] 26, further comprising an oxide layer over each of the source electrode, the drain electrode, the first polarization layer, and the second polarization layer. Currently amended
The apparatus of claim 2, further comprising a polysilicon layer [[on]]over the oxide layer. Currently amended
Canceled
The apparatus of claim 5, wherein the island of oxide comprises a shallow trench isolation oxide. Currently amended
The apparatus of claim [[5]] 1, wherein [[a]]the gallium nitride seed layer is on the silicon substrate in the further trench adjacent to the island of oxide, the gallium nitride material being on the seed layer. Currently amended
The apparatus of claim [[1]] 26, further comprising a two dimensional electron gas (2DEG) at an interface between the gallium nitride material and the first polarization layer; and a 2DEG at an interface between the gallium nitride material and the second polarization layer. Currently amended
10-25. Canceled
Canceled
An apparatus comprising: a silicon substrate comprising a trench; a gallium nitride material in the trench of the silicon substrate; a source electrode on the gallium nitride material; a drain electrode on the gallium nitride material; a gate electrode on the gallium nitride material between the source electrode and the drain electrode; a first polarization layer over a portion of the gallium nitride material between the source electrode and the gate electrode, and a second polarization layer over a portion of the gallium nitride material between the gate electrode and the drain electrode; and an oxide layer over each of the source electrode, the drain electrode, the first polarization layer, and the second polarization layer. New
The apparatus of claim 34, further comprising a polysilicon layer over the oxide layer. New
The apparatus of claim 34, wherein at least one of the gate electrode, the source electrode, and the drain electrode has a long axis in a direction substantially parallel to a [11-2] direction of the silicon substrate. New
The apparatus of claim 34, wherein a sidewall of the trench is a silicon (110) sidewall. New
The apparatus of claim 34, wherein the apparatus is one of a voltage regulator, a power amplifier, a computing device, and a processor. New
An apparatus comprising: a silicon substrate comprising a trench; a gallium nitride material in the trench of the silicon substrate; a source electrode on the gallium nitride material; a drain electrode on the gallium nitride material; and a gate electrode on the gallium nitride material between the source electrode and the drain electrode, wherein at least one of the gate electrode, the source electrode, and the drain electrode has a long axis in a direction substantially parallel to a [11-2] direction of the silicon substrate. New
The apparatus of claim 40, wherein the silicon substrate is a silicon 111 substrate. New
The apparatus of claim 40, wherein the apparatus is one of a voltage regulator, a power amplifier, a computing device, and a processor. New
Layer stacks claimed or described, ordered top of device to substrate.
GaN NMOS transistor in silicon trench
Materials described outside the worked examples.
gallium nitride material
GaN
silicon substrate
Si
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic diagram of a communications device that includes a gallium nitride transistor formed on a silicon 111 substrate in accordance with …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV |
Related documents with shared materials, methods, properties, or citations.
silicon PMOS device on polysilicon layer
island of oxide
oxide layer
polysilicon layer
poly-Si
first polarization layer
second polarization layer
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
| — |
silicon PMOS device on polysilicon layer
island of oxide
oxide layer
polysilicon layer
poly-Si
first polarization layer
second polarization layer
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
| — |
silicon PMOS device on polysilicon layer
island of oxide
oxide layer
polysilicon layer
poly-Si
first polarization layer
second polarization layer
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
| — |
silicon PMOS device on polysilicon layer
island of oxide
oxide layer
polysilicon layer
poly-Si
first polarization layer
second polarization layer
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
| — |