Patent
US 8,358,005PACKAGED GALLIUM NITRIDE MATERIAL TRANSISTORS AND METHODS ASSOCIATED WITH THE SAME
Isik C. Kizilyalli
US
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US 8,358,005Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A-2C illustrate a transistor. However, it 5 should be understood that not all embodiments of the invention are limited to transistors and that other …
FIG. 2B, polymeric material portion 11 2a encapsulates the power transistor and associated matching network components. In this case, polymeric material …
FIGS. 3A and 3B respectively illustrate a cross-section of and top view of a transistor building block structure 10 according to one embodiment of the …
FIG. 4 is a plan view of a transistor unit cell 30 according to one embodiment of the invention. In this embodiment, the transistor unit cell includes ten …
FIG. 5 is a plan view of a power transistor 40 according to one embodiment of the invention. The power transistor includes multiple transistor unit cells 30 …
FIG. 6A. As described further above, other components (e.g., matching network components) may also be attached to the package. Bond wires 54 may be used to …
FIG. 7 illustrates a transistor 40 attached directly to a circuit board 120. In this figure, a polymeric material 122 is used to encapsulate the transistor on …
FIG. 8 shows drain efficiency and gain as a function of output power for a transistor of the invention as described in Example 1. 25 Detailed Description The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
/0 5/2012 T H U 18:34 FAX 949 282 1002 FARJA 51 I & FARJA Ml I LLP ->-*- USPTO @ j 003/016 Attorney Docket No.: 0400646 In the Claims: Claims 1-32 (canceled) Claim 33: A packaged semiconductor device he-deviee comprising:-a package comprising a polymeric material portion; at least two components each mounted directly on a support of said package, at least one of the components comprising a gallium nitride material and at least one of the components comprising silicon; at least one of said at least two components comprising a matching network component that is adapted to transform an impedance of said packaged semiconductor device; at least one bond wire connecting a top surface of said at least one of the components comprising a gallium nitride material to a top surface of said at least one of the components comprising silicon.
, wherein one component comprises gallium nitride material and silicon with the gallium nitride material being a region formed over a silicon substrate.
, wherein said at least one component comprising impedance matching for said at least one component
, further comprising another component impedance matching for said at least one component
Layer stacks claimed or described, ordered top of device to substrate.
packaged semiconductor device with GaN-on-Si component
packaged gallium nitride material transistor with polymeric package
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride material
GaN
silicon
Si
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1A-2C illustrate a transistor. However, it 5 should be understood that not all embodiments of the invention are limited to transistors and that other …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,358,005Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A-2C illustrate a transistor. However, it 5 should be understood that not all embodiments of the invention are limited to transistors and that other …
FIG. 2B, polymeric material portion 11 2a encapsulates the power transistor and associated matching network components. In this case, polymeric material …
FIGS. 3A and 3B respectively illustrate a cross-section of and top view of a transistor building block structure 10 according to one embodiment of the …
FIG. 4 is a plan view of a transistor unit cell 30 according to one embodiment of the invention. In this embodiment, the transistor unit cell includes ten …
FIG. 5 is a plan view of a power transistor 40 according to one embodiment of the invention. The power transistor includes multiple transistor unit cells 30 …
FIG. 6A. As described further above, other components (e.g., matching network components) may also be attached to the package. Bond wires 54 may be used to …
FIG. 7 illustrates a transistor 40 attached directly to a circuit board 120. In this figure, a polymeric material 122 is used to encapsulate the transistor on …
FIG. 8 shows drain efficiency and gain as a function of output power for a transistor of the invention as described in Example 1. 25 Detailed Description The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
/0 5/2012 T H U 18:34 FAX 949 282 1002 FARJA 51 I & FARJA Ml I LLP ->-*- USPTO @ j 003/016 Attorney Docket No.: 0400646 In the Claims: Claims 1-32 (canceled) Claim 33: A packaged semiconductor device he-deviee comprising:-a package comprising a polymeric material portion; at least two components each mounted directly on a support of said package, at least one of the components comprising a gallium nitride material and at least one of the components comprising silicon; at least one of said at least two components comprising a matching network component that is adapted to transform an impedance of said packaged semiconductor device; at least one bond wire connecting a top surface of said at least one of the components comprising a gallium nitride material to a top surface of said at least one of the components comprising silicon.
, wherein one component comprises gallium nitride material and silicon with the gallium nitride material being a region formed over a silicon substrate.
, wherein said at least one component comprising impedance matching for said at least one component
, further comprising another component impedance matching for said at least one component
Layer stacks claimed or described, ordered top of device to substrate.
packaged semiconductor device with GaN-on-Si component
packaged gallium nitride material transistor with polymeric package
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride material
GaN
silicon
Si
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1A-2C illustrate a transistor. However, it 5 should be understood that not all embodiments of the invention are limited to transistors and that other …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,358,005Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A-2C illustrate a transistor. However, it 5 should be understood that not all embodiments of the invention are limited to transistors and that other …
FIG. 2B, polymeric material portion 11 2a encapsulates the power transistor and associated matching network components. In this case, polymeric material …
FIGS. 3A and 3B respectively illustrate a cross-section of and top view of a transistor building block structure 10 according to one embodiment of the …
FIG. 4 is a plan view of a transistor unit cell 30 according to one embodiment of the invention. In this embodiment, the transistor unit cell includes ten …
FIG. 5 is a plan view of a power transistor 40 according to one embodiment of the invention. The power transistor includes multiple transistor unit cells 30 …
FIG. 6A. As described further above, other components (e.g., matching network components) may also be attached to the package. Bond wires 54 may be used to …
FIG. 7 illustrates a transistor 40 attached directly to a circuit board 120. In this figure, a polymeric material 122 is used to encapsulate the transistor on …
FIG. 8 shows drain efficiency and gain as a function of output power for a transistor of the invention as described in Example 1. 25 Detailed Description The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
/0 5/2012 T H U 18:34 FAX 949 282 1002 FARJA 51 I & FARJA Ml I LLP ->-*- USPTO @ j 003/016 Attorney Docket No.: 0400646 In the Claims: Claims 1-32 (canceled) Claim 33: A packaged semiconductor device he-deviee comprising:-a package comprising a polymeric material portion; at least two components each mounted directly on a support of said package, at least one of the components comprising a gallium nitride material and at least one of the components comprising silicon; at least one of said at least two components comprising a matching network component that is adapted to transform an impedance of said packaged semiconductor device; at least one bond wire connecting a top surface of said at least one of the components comprising a gallium nitride material to a top surface of said at least one of the components comprising silicon.
, wherein one component comprises gallium nitride material and silicon with the gallium nitride material being a region formed over a silicon substrate.
, wherein said at least one component comprising impedance matching for said at least one component
, further comprising another component impedance matching for said at least one component
Layer stacks claimed or described, ordered top of device to substrate.
packaged semiconductor device with GaN-on-Si component
packaged gallium nitride material transistor with polymeric package
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride material
GaN
silicon
Si
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1A-2C illustrate a transistor. However, it 5 should be understood that not all embodiments of the invention are limited to transistors and that other …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,358,005Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A-2C illustrate a transistor. However, it 5 should be understood that not all embodiments of the invention are limited to transistors and that other …
FIG. 2B, polymeric material portion 11 2a encapsulates the power transistor and associated matching network components. In this case, polymeric material …
FIGS. 3A and 3B respectively illustrate a cross-section of and top view of a transistor building block structure 10 according to one embodiment of the …
FIG. 4 is a plan view of a transistor unit cell 30 according to one embodiment of the invention. In this embodiment, the transistor unit cell includes ten …
FIG. 5 is a plan view of a power transistor 40 according to one embodiment of the invention. The power transistor includes multiple transistor unit cells 30 …
FIG. 6A. As described further above, other components (e.g., matching network components) may also be attached to the package. Bond wires 54 may be used to …
FIG. 7 illustrates a transistor 40 attached directly to a circuit board 120. In this figure, a polymeric material 122 is used to encapsulate the transistor on …
FIG. 8 shows drain efficiency and gain as a function of output power for a transistor of the invention as described in Example 1. 25 Detailed Description The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
/0 5/2012 T H U 18:34 FAX 949 282 1002 FARJA 51 I & FARJA Ml I LLP ->-*- USPTO @ j 003/016 Attorney Docket No.: 0400646 In the Claims: Claims 1-32 (canceled) Claim 33: A packaged semiconductor device he-deviee comprising:-a package comprising a polymeric material portion; at least two components each mounted directly on a support of said package, at least one of the components comprising a gallium nitride material and at least one of the components comprising silicon; at least one of said at least two components comprising a matching network component that is adapted to transform an impedance of said packaged semiconductor device; at least one bond wire connecting a top surface of said at least one of the components comprising a gallium nitride material to a top surface of said at least one of the components comprising silicon.
, wherein one component comprises gallium nitride material and silicon with the gallium nitride material being a region formed over a silicon substrate.
, wherein said at least one component comprising impedance matching for said at least one component
, further comprising another component impedance matching for said at least one component
Layer stacks claimed or described, ordered top of device to substrate.
packaged semiconductor device with GaN-on-Si component
packaged gallium nitride material transistor with polymeric package
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride material
GaN
silicon
Si
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1A-2C illustrate a transistor. However, it 5 should be understood that not all embodiments of the invention are limited to transistors and that other …
Related documents with shared materials, methods, properties, or citations.
polymeric material
aluminum gallium nitride
AlGaN
indium gallium nitride
InGaN
aluminum indium gallium nitride
AlInGaN
FIG. 2B, polymeric material portion 11 2a encapsulates the power transistor and associated matching network components. In this case, polymeric material …
FIGS. 3A and 3B respectively illustrate a cross-section of and top view of a transistor building block structure 10 according to one embodiment of the …
FIG. 4 is a plan view of a transistor unit cell 30 according to one embodiment of the invention. In this embodiment, the transistor unit cell includes ten …
FIG. 5 is a plan view of a power transistor 40 according to one embodiment of the invention. The power transistor includes multiple transistor unit cells 30 …
FIG. 6A. As described further above, other components (e.g., matching network components) may also be attached to the package. Bond wires 54 may be used to …
FIG. 7 illustrates a transistor 40 attached directly to a circuit board 120. In this figure, a polymeric material 122 is used to encapsulate the transistor on …
FIG. 8 shows drain efficiency and gain as a function of output power for a transistor of the invention as described in Example 1. 25 Detailed Description The …
polymeric material
aluminum gallium nitride
AlGaN
indium gallium nitride
InGaN
aluminum indium gallium nitride
AlInGaN
FIG. 2B, polymeric material portion 11 2a encapsulates the power transistor and associated matching network components. In this case, polymeric material …
FIGS. 3A and 3B respectively illustrate a cross-section of and top view of a transistor building block structure 10 according to one embodiment of the …
FIG. 4 is a plan view of a transistor unit cell 30 according to one embodiment of the invention. In this embodiment, the transistor unit cell includes ten …
FIG. 5 is a plan view of a power transistor 40 according to one embodiment of the invention. The power transistor includes multiple transistor unit cells 30 …
FIG. 6A. As described further above, other components (e.g., matching network components) may also be attached to the package. Bond wires 54 may be used to …
FIG. 7 illustrates a transistor 40 attached directly to a circuit board 120. In this figure, a polymeric material 122 is used to encapsulate the transistor on …
FIG. 8 shows drain efficiency and gain as a function of output power for a transistor of the invention as described in Example 1. 25 Detailed Description The …
polymeric material
aluminum gallium nitride
AlGaN
indium gallium nitride
InGaN
aluminum indium gallium nitride
AlInGaN
FIG. 2B, polymeric material portion 11 2a encapsulates the power transistor and associated matching network components. In this case, polymeric material …
FIGS. 3A and 3B respectively illustrate a cross-section of and top view of a transistor building block structure 10 according to one embodiment of the …
FIG. 4 is a plan view of a transistor unit cell 30 according to one embodiment of the invention. In this embodiment, the transistor unit cell includes ten …
FIG. 5 is a plan view of a power transistor 40 according to one embodiment of the invention. The power transistor includes multiple transistor unit cells 30 …
FIG. 6A. As described further above, other components (e.g., matching network components) may also be attached to the package. Bond wires 54 may be used to …
FIG. 7 illustrates a transistor 40 attached directly to a circuit board 120. In this figure, a polymeric material 122 is used to encapsulate the transistor on …
FIG. 8 shows drain efficiency and gain as a function of output power for a transistor of the invention as described in Example 1. 25 Detailed Description The …
polymeric material
aluminum gallium nitride
AlGaN
indium gallium nitride
InGaN
aluminum indium gallium nitride
AlInGaN
FIG. 2B, polymeric material portion 11 2a encapsulates the power transistor and associated matching network components. In this case, polymeric material …
FIGS. 3A and 3B respectively illustrate a cross-section of and top view of a transistor building block structure 10 according to one embodiment of the …
FIG. 4 is a plan view of a transistor unit cell 30 according to one embodiment of the invention. In this embodiment, the transistor unit cell includes ten …
FIG. 5 is a plan view of a power transistor 40 according to one embodiment of the invention. The power transistor includes multiple transistor unit cells 30 …
FIG. 6A. As described further above, other components (e.g., matching network components) may also be attached to the package. Bond wires 54 may be used to …
FIG. 7 illustrates a transistor 40 attached directly to a circuit board 120. In this figure, a polymeric material 122 is used to encapsulate the transistor on …
FIG. 8 shows drain efficiency and gain as a function of output power for a transistor of the invention as described in Example 1. 25 Detailed Description The …