Patent
US 9,240,474Enhanced GaN Transistor and the Forming Method Thereof
Yi CHANG
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 9,240,474Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates the cross-sectional view of the GaN epitaxy structure.
Figure 2 illustrates the cross-sectional view of form in g the dra in ohmic contact and the source ohmic contact on two sides of the p-element epitaxy growth layer. 4
Figure 3 illustrates the cross-sectional view of forming the gate structure on the p-element epitaxy growth layer.
Figure 4 illustrates the cross-sectional view of forming the surface passivation layer on the structure shown in
Figure 5 illustrates the flow chart of forming the enhanced GaN transistor disclosed by the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. An enhanced GaN transistor by using having an InxAli. N/A I N heterostructure to raise an output current and having a p-InxAlI,.N layer to raise a threshold voltage, comprising: a substrate, wherein the substrate is selected from the group consisting of silicon carbide (SiC) and silicon; a InxAli.N/AIN heterostructure being disposed on the substrate, wherein the heterostructure is a In AVa N/AIN heterostructure in order to raise an output current; a p-In xAli. N layer being disposed on the InxA 1.xN/AIN heterostructure to form a P-N junction in order to raise a threshold voltage; a drain ohmic contact is disposed on the In x Ati.N/AIN heterostructure, and a source ohmic contact is disposed on the In x Al 1.xN/AIN heterostructure, formed on two sides of the p-In xAl11. N layer; a gate structure being disposed on the p-In xAli. N layer and separated from the drain ohmic contact and the source ohmic contact; and a surface passivation layer covers the drain ohmic contact, the source ohmic contact, the p-In xAli. N layer and a portion of the gate structure, wherein the surface passivation layer comprises silicon nitride (SiN).
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A forming method for the enhanced GaN transistor by using having an In xAli. N/A I N heterostructure to raise an output current and having a p- InxA 1.xN layer to raise a threshold voltage, comprising; -2- App l. No. 14/050,534 Amendment dated: Reply to O A of: providing a substrate, wherein the substrate is selected from the group consisting of silicon carbide (SiC) and silicon; forming a In x Al 1.xN/AIN heterostructure on the substrate, wherein the heterostructure is In AVa N/AIN in order to raise an output current; forming a p-In xAli. N layer on the InxAtI l.N/AIN heterostructure to form a P-N junction in order to raise a threshold voltage; forming a first photoresist layer on the p-In xAli. N layer and forming a drain region and a source region on two sides of the p-In xAl₁ 1. N layer; etching to remove a portion of the p-In xAli. N depositing a first metal layer on two sides of the p-In xAli. N growth layer to form a drain ohmic contact and a source ohmic contact; forming a second photoresist layer on the p-In xAli. N layer, and defining a gate region on the p-In xA₁ l. N layer; depositing a second metal layer on the p-In xAli. N layer; etching to remove a portion of the second metal layer by using an inductively coupled plasma (ICP) to form a gate structure on the p-In xAli. N layer, separating the gate structure from the drain ohmic contact and the source ohmic contact; and depositing a surface passivation layer to cover the drain ohmic contact, the source ohmic contact, the p-In x A₁ l1 x N layer and a portion of the gate structure.
The method according to claim 7, wherein the plasma enhanced chemical vapor deposition (PECVD) is used to deposit the surface passivation layer.
11. The method according to claim 7, wherein the surface passivation layer comprises silicon nitride (SiN). -3-
8-9. canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
enhanced GaN transistor (E-mode HEMT)
Materials described outside the worked examples.
InxAl₁-xN/AlN heterostructure
InxAl₁-xN/AlN
p-InxAl₁-xN
silicon carbide (SiC)
SiC
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 5 illustrates the flow chart of forming the enhanced GaN transistor disclosed by the present invention.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,240,474Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates the cross-sectional view of the GaN epitaxy structure.
Figure 2 illustrates the cross-sectional view of form in g the dra in ohmic contact and the source ohmic contact on two sides of the p-element epitaxy growth layer. 4
Figure 3 illustrates the cross-sectional view of forming the gate structure on the p-element epitaxy growth layer.
Figure 4 illustrates the cross-sectional view of forming the surface passivation layer on the structure shown in
Figure 5 illustrates the flow chart of forming the enhanced GaN transistor disclosed by the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. An enhanced GaN transistor by using having an InxAli. N/A I N heterostructure to raise an output current and having a p-InxAlI,.N layer to raise a threshold voltage, comprising: a substrate, wherein the substrate is selected from the group consisting of silicon carbide (SiC) and silicon; a InxAli.N/AIN heterostructure being disposed on the substrate, wherein the heterostructure is a In AVa N/AIN heterostructure in order to raise an output current; a p-In xAli. N layer being disposed on the InxA 1.xN/AIN heterostructure to form a P-N junction in order to raise a threshold voltage; a drain ohmic contact is disposed on the In x Ati.N/AIN heterostructure, and a source ohmic contact is disposed on the In x Al 1.xN/AIN heterostructure, formed on two sides of the p-In xAl11. N layer; a gate structure being disposed on the p-In xAli. N layer and separated from the drain ohmic contact and the source ohmic contact; and a surface passivation layer covers the drain ohmic contact, the source ohmic contact, the p-In xAli. N layer and a portion of the gate structure, wherein the surface passivation layer comprises silicon nitride (SiN).
2-6. canceled
canceled
canceled
canceled
canceled
A forming method for the enhanced GaN transistor by using having an In xAli. N/A I N heterostructure to raise an output current and having a p- InxA 1.xN layer to raise a threshold voltage, comprising; -2- App l. No. 14/050,534 Amendment dated: Reply to O A of: providing a substrate, wherein the substrate is selected from the group consisting of silicon carbide (SiC) and silicon; forming a In x Al 1.xN/AIN heterostructure on the substrate, wherein the heterostructure is In AVa N/AIN in order to raise an output current; forming a p-In xAli. N layer on the InxAtI l.N/AIN heterostructure to form a P-N junction in order to raise a threshold voltage; forming a first photoresist layer on the p-In xAli. N layer and forming a drain region and a source region on two sides of the p-In xAl₁ 1. N layer; etching to remove a portion of the p-In xAli. N depositing a first metal layer on two sides of the p-In xAli. N growth layer to form a drain ohmic contact and a source ohmic contact; forming a second photoresist layer on the p-In xAli. N layer, and defining a gate region on the p-In xA₁ l. N layer; depositing a second metal layer on the p-In xAli. N layer; etching to remove a portion of the second metal layer by using an inductively coupled plasma (ICP) to form a gate structure on the p-In xAli. N layer, separating the gate structure from the drain ohmic contact and the source ohmic contact; and depositing a surface passivation layer to cover the drain ohmic contact, the source ohmic contact, the p-In x A₁ l1 x N layer and a portion of the gate structure.
The method according to claim 7, wherein the plasma enhanced chemical vapor deposition (PECVD) is used to deposit the surface passivation layer.
11. The method according to claim 7, wherein the surface passivation layer comprises silicon nitride (SiN). -3-
8-9. canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
enhanced GaN transistor (E-mode HEMT)
Materials described outside the worked examples.
InxAl₁-xN/AlN heterostructure
InxAl₁-xN/AlN
p-InxAl₁-xN
silicon carbide (SiC)
SiC
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 5 illustrates the flow chart of forming the enhanced GaN transistor disclosed by the present invention.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,240,474Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates the cross-sectional view of the GaN epitaxy structure.
Figure 2 illustrates the cross-sectional view of form in g the dra in ohmic contact and the source ohmic contact on two sides of the p-element epitaxy growth layer. 4
Figure 3 illustrates the cross-sectional view of forming the gate structure on the p-element epitaxy growth layer.
Figure 4 illustrates the cross-sectional view of forming the surface passivation layer on the structure shown in
Figure 5 illustrates the flow chart of forming the enhanced GaN transistor disclosed by the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. An enhanced GaN transistor by using having an InxAli. N/A I N heterostructure to raise an output current and having a p-InxAlI,.N layer to raise a threshold voltage, comprising: a substrate, wherein the substrate is selected from the group consisting of silicon carbide (SiC) and silicon; a InxAli.N/AIN heterostructure being disposed on the substrate, wherein the heterostructure is a In AVa N/AIN heterostructure in order to raise an output current; a p-In xAli. N layer being disposed on the InxA 1.xN/AIN heterostructure to form a P-N junction in order to raise a threshold voltage; a drain ohmic contact is disposed on the In x Ati.N/AIN heterostructure, and a source ohmic contact is disposed on the In x Al 1.xN/AIN heterostructure, formed on two sides of the p-In xAl11. N layer; a gate structure being disposed on the p-In xAli. N layer and separated from the drain ohmic contact and the source ohmic contact; and a surface passivation layer covers the drain ohmic contact, the source ohmic contact, the p-In xAli. N layer and a portion of the gate structure, wherein the surface passivation layer comprises silicon nitride (SiN).
2-6. canceled
canceled
canceled
canceled
canceled
A forming method for the enhanced GaN transistor by using having an In xAli. N/A I N heterostructure to raise an output current and having a p- InxA 1.xN layer to raise a threshold voltage, comprising; -2- App l. No. 14/050,534 Amendment dated: Reply to O A of: providing a substrate, wherein the substrate is selected from the group consisting of silicon carbide (SiC) and silicon; forming a In x Al 1.xN/AIN heterostructure on the substrate, wherein the heterostructure is In AVa N/AIN in order to raise an output current; forming a p-In xAli. N layer on the InxAtI l.N/AIN heterostructure to form a P-N junction in order to raise a threshold voltage; forming a first photoresist layer on the p-In xAli. N layer and forming a drain region and a source region on two sides of the p-In xAl₁ 1. N layer; etching to remove a portion of the p-In xAli. N depositing a first metal layer on two sides of the p-In xAli. N growth layer to form a drain ohmic contact and a source ohmic contact; forming a second photoresist layer on the p-In xAli. N layer, and defining a gate region on the p-In xA₁ l. N layer; depositing a second metal layer on the p-In xAli. N layer; etching to remove a portion of the second metal layer by using an inductively coupled plasma (ICP) to form a gate structure on the p-In xAli. N layer, separating the gate structure from the drain ohmic contact and the source ohmic contact; and depositing a surface passivation layer to cover the drain ohmic contact, the source ohmic contact, the p-In x A₁ l1 x N layer and a portion of the gate structure.
The method according to claim 7, wherein the plasma enhanced chemical vapor deposition (PECVD) is used to deposit the surface passivation layer.
11. The method according to claim 7, wherein the surface passivation layer comprises silicon nitride (SiN). -3-
8-9. canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
enhanced GaN transistor (E-mode HEMT)
Materials described outside the worked examples.
InxAl₁-xN/AlN heterostructure
InxAl₁-xN/AlN
p-InxAl₁-xN
silicon carbide (SiC)
SiC
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 5 illustrates the flow chart of forming the enhanced GaN transistor disclosed by the present invention.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,240,474Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates the cross-sectional view of the GaN epitaxy structure.
Figure 2 illustrates the cross-sectional view of form in g the dra in ohmic contact and the source ohmic contact on two sides of the p-element epitaxy growth layer. 4
Figure 3 illustrates the cross-sectional view of forming the gate structure on the p-element epitaxy growth layer.
Figure 4 illustrates the cross-sectional view of forming the surface passivation layer on the structure shown in
Figure 5 illustrates the flow chart of forming the enhanced GaN transistor disclosed by the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. An enhanced GaN transistor by using having an InxAli. N/A I N heterostructure to raise an output current and having a p-InxAlI,.N layer to raise a threshold voltage, comprising: a substrate, wherein the substrate is selected from the group consisting of silicon carbide (SiC) and silicon; a InxAli.N/AIN heterostructure being disposed on the substrate, wherein the heterostructure is a In AVa N/AIN heterostructure in order to raise an output current; a p-In xAli. N layer being disposed on the InxA 1.xN/AIN heterostructure to form a P-N junction in order to raise a threshold voltage; a drain ohmic contact is disposed on the In x Ati.N/AIN heterostructure, and a source ohmic contact is disposed on the In x Al 1.xN/AIN heterostructure, formed on two sides of the p-In xAl11. N layer; a gate structure being disposed on the p-In xAli. N layer and separated from the drain ohmic contact and the source ohmic contact; and a surface passivation layer covers the drain ohmic contact, the source ohmic contact, the p-In xAli. N layer and a portion of the gate structure, wherein the surface passivation layer comprises silicon nitride (SiN).
2-6. canceled
canceled
canceled
canceled
canceled
A forming method for the enhanced GaN transistor by using having an In xAli. N/A I N heterostructure to raise an output current and having a p- InxA 1.xN layer to raise a threshold voltage, comprising; -2- App l. No. 14/050,534 Amendment dated: Reply to O A of: providing a substrate, wherein the substrate is selected from the group consisting of silicon carbide (SiC) and silicon; forming a In x Al 1.xN/AIN heterostructure on the substrate, wherein the heterostructure is In AVa N/AIN in order to raise an output current; forming a p-In xAli. N layer on the InxAtI l.N/AIN heterostructure to form a P-N junction in order to raise a threshold voltage; forming a first photoresist layer on the p-In xAli. N layer and forming a drain region and a source region on two sides of the p-In xAl₁ 1. N layer; etching to remove a portion of the p-In xAli. N depositing a first metal layer on two sides of the p-In xAli. N growth layer to form a drain ohmic contact and a source ohmic contact; forming a second photoresist layer on the p-In xAli. N layer, and defining a gate region on the p-In xA₁ l. N layer; depositing a second metal layer on the p-In xAli. N layer; etching to remove a portion of the second metal layer by using an inductively coupled plasma (ICP) to form a gate structure on the p-In xAli. N layer, separating the gate structure from the drain ohmic contact and the source ohmic contact; and depositing a surface passivation layer to cover the drain ohmic contact, the source ohmic contact, the p-In x A₁ l1 x N layer and a portion of the gate structure.
The method according to claim 7, wherein the plasma enhanced chemical vapor deposition (PECVD) is used to deposit the surface passivation layer.
11. The method according to claim 7, wherein the surface passivation layer comprises silicon nitride (SiN). -3-
8-9. canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
enhanced GaN transistor (E-mode HEMT)
Materials described outside the worked examples.
InxAl₁-xN/AlN heterostructure
InxAl₁-xN/AlN
p-InxAl₁-xN
silicon carbide (SiC)
SiC
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 5 illustrates the flow chart of forming the enhanced GaN transistor disclosed by the present invention.
Related documents with shared materials, methods, properties, or citations.
silicon
Si
silicon nitride
SiN
GaN
silicon
Si
silicon nitride
SiN
GaN
silicon
Si
silicon nitride
SiN
GaN
silicon
Si
silicon nitride
SiN
GaN