Patent
Atlas literature
Patent
US 12,302,618 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1B-1E illustrate cross-sectional views representing 35 various operations in a method of fabricating differing aspect ratio GaN islands in trenches in a …
FIG. 2 illustrates a cross-sectional view of a transistor having a drain field plate, in accordance with embodiments 40 of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIG. 4 illustrates a cross-sectional view of a high voltage 45 scaled GaN device with multi-gate technology, in accor- dance with an embodiment of the present …
FIG. 5 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with an …
FIG. 6 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIG. 7 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIGS. 8A-8C illustrate a GaN transistor in accordance 60 with embodiments of the present disclosure.
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar 65 or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of …
FIG. 11 illustrates a computing device in accordance with one implementation of the disclosure.
FIG. 12 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 13 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or …
FIG. 30 2. In an embodiment, drain field plate 220 may be biased separately from a gate voltage (Vg) applied to gate structure 208. In an embodiment, drain field …
FIGS. 50 8B and 8C. In embodiments of the present disclosure, source polarization layer 846 and drain polarization layer 848 have a thickness greater than the …
FIG. 65 8A. In an embodiment, the gate width of transistor 800 is between 10 and 100 microns. B₂ Transistor 800 includes a polarization layer 840. In an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: a substrate comprising silicon, the substrate having a top surface; a first trench in the substrate, the first trench having a first width and a first height; a second trench in the substrate, the second trench having a second width and a second height, the second width greater than the first width, and the second height greater than the first height; 60 a first island in the first trench, the first island comprising gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate, wherein the first island has a bottommost surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the upper-most surface; and B₂ a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate, wherein the second island has a bottom-most surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface.
The integrated circuit structure of claim 1, wherein the first island and the second island comprise a top heterostruc-ture layer.
The integrated circuit structure of claim 1, wherein the first island has the uppermost surface co-planar with the top surface of the substrate, and wherein the second island has the uppermost surface co-planar with the top surface of the substrate.
The integrated circuit structure of claim 1, further comprising: a plurality of gate structures over the first island or the second island; a source region on a first side of the plurality of gate structures; a drain region on a second side of the plurality of gate structures, the second side opposite the first side; and a drain field plate above the drain region wherein the drain field plate is coupled to the source region.
A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a substrate comprising silicon, the substrate having a top surface; a first trench in the substrate, the first trench having a first width and a first height; a second trench in the substrate, the second trench having a second width and a second height, the second width greater than the first width, and the second height greater than the first height; a first island in the first trench, the first island com-prising gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate, wherein the first island has a bottommost surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface; and a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate, wherein the second island has a bottommost surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface.
The computing device of claim 6, further comprising: a memory coupled to the board.
The computing device of claim 6, further comprising: a communication chip coupled to the board.
The computing device of claim 6, further comprising: a camera coupled to the board.
The computing device of claim 6, wherein the com-ponent is a packaged integrated circuit die.
The computing device of claim 6, wherein the first island and the second island comprise a top heterostructure layer.
The computing device of claim 6, wherein the first island has the uppermost surface co-planar with the top surface of the substrate, and wherein the second island has the uppermost surface co-planar with the top surface of the substrate.
The computing device of claim 6, the integrated circuit structure further comprising: 10 a plurality of gate structures over the first island or the second island; a source region on a first side of the plurality of gate structures; a drain region on a second side of the plurality of gate structures, the second side opposite the first side; and a drain field plate above the drain region wherein the drain field plate is coupled to the source region.
A method of fabricating an integrated circuit structure, the method comprising: forming a first trench in the substrate comprising silicon, the substrate having a top surface, and the first trench having a first width and a first height; forming a second trench in the substrate, the second trench having a second width and a second height, the 25 second width greater than the first width, and the second height greater than the first height; forming a first island in the first trench, the first island comprising gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate, wherein the first island has a bottommost B₂ surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface; and forming a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate, wherein the second island has a bottommost surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface.
The method of claim 15, wherein the first island and the second island are formed during a same growth process.
The method of claim 15, wherein the first island and the second island comprise a top heterostructure layer.
The method of claim 15, wherein the first island has the uppermost surface co-planar with the top surface of the substrate, and wherein the second island has the uppermost surface co-planar with the top surface of the substrate.
The method of claim 15, further comprising: forming a plurality of gate structures over the first island or the second island; forming a source region on a first side of the plurality of gate structures; forming a drain region on a second side of the plurality of gate structures, the second side opposite the first side; and forming a drain field plate above the drain region wherein the drain field plate is coupled to the source region. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN island integrated circuit structure
GaN transistor with gate structures, source, drain, and drain field plate
Materials described outside the worked examples.
gallium nitride
GaN
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor having a drain field plate, in accordance with embodiments 40 of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 µm | — |
— | 4.9–5.2 eV |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Cited non-patent literature · 1
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,302,618 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1B-1E illustrate cross-sectional views representing 35 various operations in a method of fabricating differing aspect ratio GaN islands in trenches in a …
FIG. 2 illustrates a cross-sectional view of a transistor having a drain field plate, in accordance with embodiments 40 of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIG. 4 illustrates a cross-sectional view of a high voltage 45 scaled GaN device with multi-gate technology, in accor- dance with an embodiment of the present …
FIG. 5 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with an …
FIG. 6 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIG. 7 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIGS. 8A-8C illustrate a GaN transistor in accordance 60 with embodiments of the present disclosure.
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar 65 or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of …
FIG. 11 illustrates a computing device in accordance with one implementation of the disclosure.
FIG. 12 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 13 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or …
FIG. 30 2. In an embodiment, drain field plate 220 may be biased separately from a gate voltage (Vg) applied to gate structure 208. In an embodiment, drain field …
FIGS. 50 8B and 8C. In embodiments of the present disclosure, source polarization layer 846 and drain polarization layer 848 have a thickness greater than the …
FIG. 65 8A. In an embodiment, the gate width of transistor 800 is between 10 and 100 microns. B₂ Transistor 800 includes a polarization layer 840. In an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: a substrate comprising silicon, the substrate having a top surface; a first trench in the substrate, the first trench having a first width and a first height; a second trench in the substrate, the second trench having a second width and a second height, the second width greater than the first width, and the second height greater than the first height; 60 a first island in the first trench, the first island comprising gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate, wherein the first island has a bottommost surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the upper-most surface; and B₂ a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate, wherein the second island has a bottom-most surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface.
The integrated circuit structure of claim 1, wherein the first island and the second island comprise a top heterostruc-ture layer.
The integrated circuit structure of claim 1, wherein the first island has the uppermost surface co-planar with the top surface of the substrate, and wherein the second island has the uppermost surface co-planar with the top surface of the substrate.
The integrated circuit structure of claim 1, further comprising: a plurality of gate structures over the first island or the second island; a source region on a first side of the plurality of gate structures; a drain region on a second side of the plurality of gate structures, the second side opposite the first side; and a drain field plate above the drain region wherein the drain field plate is coupled to the source region.
A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a substrate comprising silicon, the substrate having a top surface; a first trench in the substrate, the first trench having a first width and a first height; a second trench in the substrate, the second trench having a second width and a second height, the second width greater than the first width, and the second height greater than the first height; a first island in the first trench, the first island com-prising gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate, wherein the first island has a bottommost surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface; and a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate, wherein the second island has a bottommost surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface.
The computing device of claim 6, further comprising: a memory coupled to the board.
The computing device of claim 6, further comprising: a communication chip coupled to the board.
The computing device of claim 6, further comprising: a camera coupled to the board.
The computing device of claim 6, wherein the com-ponent is a packaged integrated circuit die.
The computing device of claim 6, wherein the first island and the second island comprise a top heterostructure layer.
The computing device of claim 6, wherein the first island has the uppermost surface co-planar with the top surface of the substrate, and wherein the second island has the uppermost surface co-planar with the top surface of the substrate.
The computing device of claim 6, the integrated circuit structure further comprising: 10 a plurality of gate structures over the first island or the second island; a source region on a first side of the plurality of gate structures; a drain region on a second side of the plurality of gate structures, the second side opposite the first side; and a drain field plate above the drain region wherein the drain field plate is coupled to the source region.
A method of fabricating an integrated circuit structure, the method comprising: forming a first trench in the substrate comprising silicon, the substrate having a top surface, and the first trench having a first width and a first height; forming a second trench in the substrate, the second trench having a second width and a second height, the 25 second width greater than the first width, and the second height greater than the first height; forming a first island in the first trench, the first island comprising gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate, wherein the first island has a bottommost B₂ surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface; and forming a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate, wherein the second island has a bottommost surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface.
The method of claim 15, wherein the first island and the second island are formed during a same growth process.
The method of claim 15, wherein the first island and the second island comprise a top heterostructure layer.
The method of claim 15, wherein the first island has the uppermost surface co-planar with the top surface of the substrate, and wherein the second island has the uppermost surface co-planar with the top surface of the substrate.
The method of claim 15, further comprising: forming a plurality of gate structures over the first island or the second island; forming a source region on a first side of the plurality of gate structures; forming a drain region on a second side of the plurality of gate structures, the second side opposite the first side; and forming a drain field plate above the drain region wherein the drain field plate is coupled to the source region. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN island integrated circuit structure
GaN transistor with gate structures, source, drain, and drain field plate
Materials described outside the worked examples.
gallium nitride
GaN
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor having a drain field plate, in accordance with embodiments 40 of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 µm | — |
— | 4.9–5.2 eV |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Cited non-patent literature · 1
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,302,618 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1B-1E illustrate cross-sectional views representing 35 various operations in a method of fabricating differing aspect ratio GaN islands in trenches in a …
FIG. 2 illustrates a cross-sectional view of a transistor having a drain field plate, in accordance with embodiments 40 of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIG. 4 illustrates a cross-sectional view of a high voltage 45 scaled GaN device with multi-gate technology, in accor- dance with an embodiment of the present …
FIG. 5 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with an …
FIG. 6 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIG. 7 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIGS. 8A-8C illustrate a GaN transistor in accordance 60 with embodiments of the present disclosure.
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar 65 or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of …
FIG. 11 illustrates a computing device in accordance with one implementation of the disclosure.
FIG. 12 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 13 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or …
FIG. 30 2. In an embodiment, drain field plate 220 may be biased separately from a gate voltage (Vg) applied to gate structure 208. In an embodiment, drain field …
FIGS. 50 8B and 8C. In embodiments of the present disclosure, source polarization layer 846 and drain polarization layer 848 have a thickness greater than the …
FIG. 65 8A. In an embodiment, the gate width of transistor 800 is between 10 and 100 microns. B₂ Transistor 800 includes a polarization layer 840. In an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: a substrate comprising silicon, the substrate having a top surface; a first trench in the substrate, the first trench having a first width and a first height; a second trench in the substrate, the second trench having a second width and a second height, the second width greater than the first width, and the second height greater than the first height; 60 a first island in the first trench, the first island comprising gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate, wherein the first island has a bottommost surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the upper-most surface; and B₂ a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate, wherein the second island has a bottom-most surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface.
The integrated circuit structure of claim 1, wherein the first island and the second island comprise a top heterostruc-ture layer.
The integrated circuit structure of claim 1, wherein the first island has the uppermost surface co-planar with the top surface of the substrate, and wherein the second island has the uppermost surface co-planar with the top surface of the substrate.
The integrated circuit structure of claim 1, further comprising: a plurality of gate structures over the first island or the second island; a source region on a first side of the plurality of gate structures; a drain region on a second side of the plurality of gate structures, the second side opposite the first side; and a drain field plate above the drain region wherein the drain field plate is coupled to the source region.
A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a substrate comprising silicon, the substrate having a top surface; a first trench in the substrate, the first trench having a first width and a first height; a second trench in the substrate, the second trench having a second width and a second height, the second width greater than the first width, and the second height greater than the first height; a first island in the first trench, the first island com-prising gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate, wherein the first island has a bottommost surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface; and a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate, wherein the second island has a bottommost surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface.
The computing device of claim 6, further comprising: a memory coupled to the board.
The computing device of claim 6, further comprising: a communication chip coupled to the board.
The computing device of claim 6, further comprising: a camera coupled to the board.
The computing device of claim 6, wherein the com-ponent is a packaged integrated circuit die.
The computing device of claim 6, wherein the first island and the second island comprise a top heterostructure layer.
The computing device of claim 6, wherein the first island has the uppermost surface co-planar with the top surface of the substrate, and wherein the second island has the uppermost surface co-planar with the top surface of the substrate.
The computing device of claim 6, the integrated circuit structure further comprising: 10 a plurality of gate structures over the first island or the second island; a source region on a first side of the plurality of gate structures; a drain region on a second side of the plurality of gate structures, the second side opposite the first side; and a drain field plate above the drain region wherein the drain field plate is coupled to the source region.
A method of fabricating an integrated circuit structure, the method comprising: forming a first trench in the substrate comprising silicon, the substrate having a top surface, and the first trench having a first width and a first height; forming a second trench in the substrate, the second trench having a second width and a second height, the 25 second width greater than the first width, and the second height greater than the first height; forming a first island in the first trench, the first island comprising gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate, wherein the first island has a bottommost B₂ surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface; and forming a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate, wherein the second island has a bottommost surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface.
The method of claim 15, wherein the first island and the second island are formed during a same growth process.
The method of claim 15, wherein the first island and the second island comprise a top heterostructure layer.
The method of claim 15, wherein the first island has the uppermost surface co-planar with the top surface of the substrate, and wherein the second island has the uppermost surface co-planar with the top surface of the substrate.
The method of claim 15, further comprising: forming a plurality of gate structures over the first island or the second island; forming a source region on a first side of the plurality of gate structures; forming a drain region on a second side of the plurality of gate structures, the second side opposite the first side; and forming a drain field plate above the drain region wherein the drain field plate is coupled to the source region. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN island integrated circuit structure
GaN transistor with gate structures, source, drain, and drain field plate
Materials described outside the worked examples.
gallium nitride
GaN
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor having a drain field plate, in accordance with embodiments 40 of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 µm | — |
— | 4.9–5.2 eV |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Cited non-patent literature · 1
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,302,618 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1B-1E illustrate cross-sectional views representing 35 various operations in a method of fabricating differing aspect ratio GaN islands in trenches in a …
FIG. 2 illustrates a cross-sectional view of a transistor having a drain field plate, in accordance with embodiments 40 of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIG. 4 illustrates a cross-sectional view of a high voltage 45 scaled GaN device with multi-gate technology, in accor- dance with an embodiment of the present …
FIG. 5 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with an …
FIG. 6 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIG. 7 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIGS. 8A-8C illustrate a GaN transistor in accordance 60 with embodiments of the present disclosure.
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar 65 or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of …
FIG. 11 illustrates a computing device in accordance with one implementation of the disclosure.
FIG. 12 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 13 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or …
FIG. 30 2. In an embodiment, drain field plate 220 may be biased separately from a gate voltage (Vg) applied to gate structure 208. In an embodiment, drain field …
FIGS. 50 8B and 8C. In embodiments of the present disclosure, source polarization layer 846 and drain polarization layer 848 have a thickness greater than the …
FIG. 65 8A. In an embodiment, the gate width of transistor 800 is between 10 and 100 microns. B₂ Transistor 800 includes a polarization layer 840. In an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: a substrate comprising silicon, the substrate having a top surface; a first trench in the substrate, the first trench having a first width and a first height; a second trench in the substrate, the second trench having a second width and a second height, the second width greater than the first width, and the second height greater than the first height; 60 a first island in the first trench, the first island comprising gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate, wherein the first island has a bottommost surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the upper-most surface; and B₂ a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate, wherein the second island has a bottom-most surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface.
The integrated circuit structure of claim 1, wherein the first island and the second island comprise a top heterostruc-ture layer.
The integrated circuit structure of claim 1, wherein the first island has the uppermost surface co-planar with the top surface of the substrate, and wherein the second island has the uppermost surface co-planar with the top surface of the substrate.
The integrated circuit structure of claim 1, further comprising: a plurality of gate structures over the first island or the second island; a source region on a first side of the plurality of gate structures; a drain region on a second side of the plurality of gate structures, the second side opposite the first side; and a drain field plate above the drain region wherein the drain field plate is coupled to the source region.
A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a substrate comprising silicon, the substrate having a top surface; a first trench in the substrate, the first trench having a first width and a first height; a second trench in the substrate, the second trench having a second width and a second height, the second width greater than the first width, and the second height greater than the first height; a first island in the first trench, the first island com-prising gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate, wherein the first island has a bottommost surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface; and a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate, wherein the second island has a bottommost surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface.
The computing device of claim 6, further comprising: a memory coupled to the board.
The computing device of claim 6, further comprising: a communication chip coupled to the board.
The computing device of claim 6, further comprising: a camera coupled to the board.
The computing device of claim 6, wherein the com-ponent is a packaged integrated circuit die.
The computing device of claim 6, wherein the first island and the second island comprise a top heterostructure layer.
The computing device of claim 6, wherein the first island has the uppermost surface co-planar with the top surface of the substrate, and wherein the second island has the uppermost surface co-planar with the top surface of the substrate.
The computing device of claim 6, the integrated circuit structure further comprising: 10 a plurality of gate structures over the first island or the second island; a source region on a first side of the plurality of gate structures; a drain region on a second side of the plurality of gate structures, the second side opposite the first side; and a drain field plate above the drain region wherein the drain field plate is coupled to the source region.
A method of fabricating an integrated circuit structure, the method comprising: forming a first trench in the substrate comprising silicon, the substrate having a top surface, and the first trench having a first width and a first height; forming a second trench in the substrate, the second trench having a second width and a second height, the 25 second width greater than the first width, and the second height greater than the first height; forming a first island in the first trench, the first island comprising gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate, wherein the first island has a bottommost B₂ surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface; and forming a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate, wherein the second island has a bottommost surface and an uppermost surface, the bottommost surface having a lateral width greater than a lateral width of the uppermost surface.
The method of claim 15, wherein the first island and the second island are formed during a same growth process.
The method of claim 15, wherein the first island and the second island comprise a top heterostructure layer.
The method of claim 15, wherein the first island has the uppermost surface co-planar with the top surface of the substrate, and wherein the second island has the uppermost surface co-planar with the top surface of the substrate.
The method of claim 15, further comprising: forming a plurality of gate structures over the first island or the second island; forming a source region on a first side of the plurality of gate structures; forming a drain region on a second side of the plurality of gate structures, the second side opposite the first side; and forming a drain field plate above the drain region wherein the drain field plate is coupled to the source region. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN island integrated circuit structure
GaN transistor with gate structures, source, drain, and drain field plate
Materials described outside the worked examples.
gallium nitride
GaN
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor having a drain field plate, in accordance with embodiments 40 of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 µm | — |
— | 4.9–5.2 eV |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Cited non-patent literature · 1
Related documents with shared materials, methods, properties, or citations.
aluminum gallium nitride
AlGaN
FIGS. 8A-8C illustrate a GaN transistor in accordance 60 with embodiments of the present disclosure.
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar 65 or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of …
FIG. 30 2. In an embodiment, drain field plate 220 may be biased separately from a gate voltage (Vg) applied to gate structure 208. In an embodiment, drain field …
FIGS. 50 8B and 8C. In embodiments of the present disclosure, source polarization layer 846 and drain polarization layer 848 have a thickness greater than the …
FIG. 65 8A. In an embodiment, the gate width of transistor 800 is between 10 and 100 microns. B₂ Transistor 800 includes a polarization layer 840. In an …
| — |
— | 3.9–4.2 eV | — |
Voltage | 48–72 V | — |
Voltage | 0.5–3.3 V | — |
Voltage | ≥ 2 V | — |
aluminum gallium nitride
AlGaN
FIGS. 8A-8C illustrate a GaN transistor in accordance 60 with embodiments of the present disclosure.
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar 65 or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of …
FIG. 30 2. In an embodiment, drain field plate 220 may be biased separately from a gate voltage (Vg) applied to gate structure 208. In an embodiment, drain field …
FIGS. 50 8B and 8C. In embodiments of the present disclosure, source polarization layer 846 and drain polarization layer 848 have a thickness greater than the …
FIG. 65 8A. In an embodiment, the gate width of transistor 800 is between 10 and 100 microns. B₂ Transistor 800 includes a polarization layer 840. In an …
| — |
— | 3.9–4.2 eV | — |
Voltage | 48–72 V | — |
Voltage | 0.5–3.3 V | — |
Voltage | ≥ 2 V | — |
aluminum gallium nitride
AlGaN
FIGS. 8A-8C illustrate a GaN transistor in accordance 60 with embodiments of the present disclosure.
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar 65 or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of …
FIG. 30 2. In an embodiment, drain field plate 220 may be biased separately from a gate voltage (Vg) applied to gate structure 208. In an embodiment, drain field …
FIGS. 50 8B and 8C. In embodiments of the present disclosure, source polarization layer 846 and drain polarization layer 848 have a thickness greater than the …
FIG. 65 8A. In an embodiment, the gate width of transistor 800 is between 10 and 100 microns. B₂ Transistor 800 includes a polarization layer 840. In an …
| — |
— | 3.9–4.2 eV | — |
Voltage | 48–72 V | — |
Voltage | 0.5–3.3 V | — |
Voltage | ≥ 2 V | — |
aluminum gallium nitride
AlGaN
FIGS. 8A-8C illustrate a GaN transistor in accordance 60 with embodiments of the present disclosure.
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar 65 or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of …
FIG. 30 2. In an embodiment, drain field plate 220 may be biased separately from a gate voltage (Vg) applied to gate structure 208. In an embodiment, drain field …
FIGS. 50 8B and 8C. In embodiments of the present disclosure, source polarization layer 846 and drain polarization layer 848 have a thickness greater than the …
FIG. 65 8A. In an embodiment, the gate width of transistor 800 is between 10 and 100 microns. B₂ Transistor 800 includes a polarization layer 840. In an …
| — |
— | 3.9–4.2 eV | — |
Voltage | 48–72 V | — |
Voltage | 0.5–3.3 V | — |
Voltage | ≥ 2 V | — |
