Patent
US 10,943,836GALLIUM NITRIDE NMOS ON SI (111) CO-INTEGRATED WITH A SILICON PMOS
Marko Radosavljevic
US
Copyright © 2026 Matter42. All rights reserved.
silicon or polysilicon layer
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 6A is a schematic diagram of a cross sectional view of a gallium nitride NMOS transistor on a silicon substrate and two silicon PMOS transistors formed on …
FIG. 7A-7C are schematic diagrams for forming trench contacts for the gallium nitride transistor and for forming trench contacts to form a silicon PMOS …
FIGS. 8A-8D are schematic diagrams for a process flow for forming trench contacts on silicon 111 for the silicon transistor. [14]
| — |
Thickness | 130–150 nm | — |
Thickness | 60–80 nm | — |
Thickness | 400–440 nm | — |
Thickness | 70–90 nm | — |
Thickness | 30–50 nm | — |
Thickness | 85–115 nm | — |
Thickness | 180–220 nm | — |
Thickness | 20–40 nm | — |
Thickness | 125–175 nm | — |
Thickness | 35–65 nm | — |
silicon or polysilicon layer
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 6A is a schematic diagram of a cross sectional view of a gallium nitride NMOS transistor on a silicon substrate and two silicon PMOS transistors formed on …
FIG. 7A-7C are schematic diagrams for forming trench contacts for the gallium nitride transistor and for forming trench contacts to form a silicon PMOS …
FIGS. 8A-8D are schematic diagrams for a process flow for forming trench contacts on silicon 111 for the silicon transistor. [14]
| — |
Thickness | 130–150 nm | — |
Thickness | 60–80 nm | — |
Thickness | 400–440 nm | — |
Thickness | 70–90 nm | — |
Thickness | 30–50 nm | — |
Thickness | 85–115 nm | — |
Thickness | 180–220 nm | — |
Thickness | 20–40 nm | — |
Thickness | 125–175 nm | — |
Thickness | 35–65 nm | — |
silicon or polysilicon layer
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 6A is a schematic diagram of a cross sectional view of a gallium nitride NMOS transistor on a silicon substrate and two silicon PMOS transistors formed on …
FIG. 7A-7C are schematic diagrams for forming trench contacts for the gallium nitride transistor and for forming trench contacts to form a silicon PMOS …
FIGS. 8A-8D are schematic diagrams for a process flow for forming trench contacts on silicon 111 for the silicon transistor. [14]
| — |
Thickness | 130–150 nm | — |
Thickness | 60–80 nm | — |
Thickness | 400–440 nm | — |
Thickness | 70–90 nm | — |
Thickness | 30–50 nm | — |
Thickness | 85–115 nm | — |
Thickness | 180–220 nm | — |
Thickness | 20–40 nm | — |
Thickness | 125–175 nm | — |
Thickness | 35–65 nm | — |
silicon or polysilicon layer
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 6A is a schematic diagram of a cross sectional view of a gallium nitride NMOS transistor on a silicon substrate and two silicon PMOS transistors formed on …
FIG. 7A-7C are schematic diagrams for forming trench contacts for the gallium nitride transistor and for forming trench contacts to form a silicon PMOS …
FIGS. 8A-8D are schematic diagrams for a process flow for forming trench contacts on silicon 111 for the silicon transistor. [14]
| — |
Thickness | 130–150 nm | — |
Thickness | 60–80 nm | — |
Thickness | 400–440 nm | — |
Thickness | 70–90 nm | — |
Thickness | 30–50 nm | — |
Thickness | 85–115 nm | — |
Thickness | 180–220 nm | — |
Thickness | 20–40 nm | — |
Thickness | 125–175 nm | — |
Thickness | 35–65 nm | — |