COINTEGRATION OF GALLIUM NITRIDE AND SILICON

Amey Mahadev Walke

Patent

Atlas literature

Patent

US 11,322,390

COINTEGRATION OF GALLIUM NITRIDE AND SILICON

Amey Mahadev Walke

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

5 independent · 13 dependent

1
IndependentGaNIII-V semiconductor layer stackSifirst wafer III-V/GaN on Si with bonding layer
A method of forming a semiconductor device, the method comprising: forming a ﬁrst wafer comprising, on a front side thereof, a I II -V semiconductor layer stack formed on a ﬁrst substrate, [[and]] a ﬁrst bonding layer, and a barrier layer structure between the I II -V semiconductor layer stack and the ﬁrst bonding layer, the III- V semiconductor layer stack comprising a GaN-based device layer structure formed on the ﬁrst substrate and comprising a GaN channel layer; subsequent to forming the ﬁrst wafer, bonding the ﬁrst bonding layer to a second bonding layer of a second wafer, the second wafer comprising a second substrate supporting an active device layer, a back-end of line (BEOL) interconnect structure and the second bonding layer; and subsequent to bonding, thinning the ﬁrst wafer from a backside thereof, wherein thinning comprises removing at least the ﬁrst substrate. Currently amended
1. 2
  Dependent← claim 1GaNIII-V semiconductor layer stackfirst wafer III-V/GaN on Si with bonding layer
  The method of claim 1, wherein the I II -V semiconductor layer stack comprises a buﬀer layer structure between the ﬁrst substrate and the GaN-based device layer structure, and wherein thinning includes removing the buﬀer layer structure. Original
2. 4
  Dependent← claim 1GaNfirst wafer III-V/GaN on Si with bonding layerN-polar GaN HEMT
  The method of claim 1, wherein the method further comprises, subsequent to thinning, processing the GaN-based device layer structure to form a transistor device. Original
3. 7
  Dependent← claim 1AlGaNfirst wafer III-V/GaN on Si with bonding layer
  The method of claim 1 [[6]], wherein the barrier layer structure comprises at least an AlGaN layer. Currently amended
4. 8
  Dependent← claim 1InAlNfirst wafer III-V/GaN on Si with bonding layer
  The method of claim 1 [[6]], wherein the barrier layer structure comprises at least an InAl N layer. Currently amended
5. 9
  Dependent← claim 1GaNfirst wafer III-V/GaN on Si with bonding layer
  The method of claim 1 [[6]], wherein the ﬁrst wafer includes a stress layer structure between the barrier layer structure and the ﬁrst bonding layer, the stress layer structure comprising a GaN layer. Currently amended
6. 10
  Dependent← claim 1GaNdoped source-drain contacting layerfirst wafer III-V/GaN on Si with bonding layer
  The method of claim 1 [[5]], wherein the GaN-based device layer structure comprises a doped source-drain contacting layer in contact with the GaN channel layer, and wherein thinning comprises exposing the doped source-drain contacting layer. Currently amended
7. 11
  Dependent← claim 1GaNmetal layerelectrically insulating layerfirst wafer III-V/GaN on Si with bonding layer
  The method of claim 1, wherein the ﬁrst wafer comprises a metal layer between the GaN-based device layer structure and the ﬁrst bonding layer, and further comprises an electrically insulating layer between the metal layer and the GaN-based device layer structure. Original
8. 13
  Dependent← claim 1first wafer III-V/GaN on Si with bonding layer
  The method of claim 1, wherein the method further comprises, subsequent to bonding, forming one or more vias connecting to the BEOL interconnect structure. Original
9. 14
  Dependent← claim 1Sifirst wafer III-V/GaN on Si with bonding layer
  The method of claim 1, wherein the ﬁrst substrate comprises a Si substrate having a (111) surface orientation. Original
5
Independent
Canceled
6
Independent
Canceled
15
IndependentGaNIII-V semiconductor layer stackmetal layerelectrically insulating layerSiN-polar GaN HEMTco-integrated semiconductor device (Si CMOS + N-polar GaN HEMT)
A semiconductor device, comprising: a silicon substrate; an active device layer formed on the substrate; a back-end-of-line (BEOL) interconnect structure formed on the active device layer; [[and]] an N-polar high-electron-mobility transistor (HEMT) bonded via a bonding stack to the interconnect structure and comprising an N-polar GaN channel; [[.]] a metal layer between the bonding stack and the HEMT; and an electrically insulating layer between the metal layer and the HEMT. Currently amended
1. 17
  Dependent← claim 15N-polar GaN HEMT
  The semiconductor device of claim 15, wherein HEMT. Original
2. 18
  Dependent← claim 15GaNN-polar GaN HEMT
  The semiconductor device of claim 15, wherein polar GaN channel. Original the HEMT is a metal-oxide- semiconductor a gate of the HEMT is recessed into the N-
16
Independent
Canceled

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

first wafer III-V/GaN on Si with bonding layer

first_bonding_layerfirst bonding layer

metal layermetal layer

electrically insulating layerinsulating layer

AlGaNbarrier layer structure

GaNGaN channel layer

III-V semiconductor layer stack

Materials

Materials described outside the worked examples.

GaN

Channel Layer

Buffer Stress Layer

III-V semiconductor layer stack

Device Layer Stack

Process steps

Additional fabrication and treatment steps described in the patent.

Epitaxial Growth

Step 1

Process details

notes:III-V semiconductor layer stack including GaN-based device layer structure grown on front side of first Si substrate

substrate:Si (111)

techniques:MOCVD, MBE, PVD

Reported properties

Performance values and ranges asserted in the specification or claims.

Property	Value	Material
Thickness	10–100 nm	—
Thickness	50–200 nm

Why these are connected

Related documents with shared materials, methods, properties, or citations.

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