Patent
US 10,991,722ULTRA LOW PARASITIC INDUCTANCE INTEGRATED CASCODE GaN DEVICES
Ko-Tao Lee
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,991,722Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1B is a circuit schematic depicting a second ultra low parasitic inductance cascode GaN structure integrated in a single integrated circuit chip die; SVG …
FIG. 2A the die area 21 having the GaN HEMT device is laterally adjacent an area 22 having the integrated Si MOSFET. The short physical distance of a …
FIG. 3A is a cross sectional view of the exemplary semiconductor structure corr esponding to the circuit of FIG. IA; [0013]
FIG. 4 shows a further cross-sectional view of a cascode connection of a GaN HEMT device to at least two Si MOSFET devices in the same Silicon die.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a single integrated circuit die formed on top a semiconductor-on-insulator substrate, the integrated circuit die comprising: a first field effect transistor (FET); and a second field effect transistor comprising a Group I II nitride material connected in cascode to the first transistor, the second FET transistor having a first dielectric sidewall liner structure extending along a sidewall surface of said second field effect transistor and a second dielectric sidewall liner structure extending along an opposite sidewall surface of said second field effect transistor, said first and second sidewall liner structures insulating said second field effect transistor from said cascode connected first FET, the first transistor having a gate terminal receiving an input signal, the first transistor having a drain terminal driving a source terminal of the cascode connected second transistor, the second transistor having a drain terminal providing an output signal; and an integrated conductive structure formed at an interconnect layer above said semiconductor-on-insulator substrate for connecting said drain terminal of said first transistor to the source terminal of said integrated cascode connected second transistor; said conductive structure of a length configured to reduce a parasitic resistance and inductance between said first FET and cascode connected second FET, wherein said semiconductor-on-insulator substrate includes, from bottom to top, a (111) silicon layer, a buried insulator layer and a (100) silicon layer, the second FET transistor comprising: at least one Group III nitride material layer embedded within a trench that extends through the (100) silicon layer and the buried insulator layer and into an upper portion of the (111) silicon layer. Currently amended
The semiconductor structure as claimed in Claim 1, wherein a further conductive structure formed at said one or more interconnect layers connects a gate terminal of said cascode connected second transistor to a source terminal of said first transistor. Original
The semiconductor structure as claimed in Claim 1, wherein the integrated conductive structure for connecting said drain terminal of said first transistor to the source terminal of said integrated cascode connected second transistor is formed at a back-end-of-line (BEOL) metallization interlevel or combination of metallization interlevels. Original
The semiconductor structure as claimed in Claim 1, wherein the received input signal is a first input signal, a gate terminal of said cascode connected second transistor configured to receive a second input signal, different than said first input signal. Original
The semiconductor structure as claimed in Claim 1, wherein said first FET transistor is a metal oxide semiconductor FET (MOSFET) in a normally off state and includes a channel of a polarity adapted for enhancement mode FET operation. Original
The semiconductor structure as claimed in Claim 1, wherein said Group III nitride material includes material selected from GaN, A l N, InN, Ga I nN, AlGaN, and GaAlInN, said second FET transistor to be in a normally on state and includes a channel of a polarity adapted for a depletion mode FET operation. Original
The semiconductor structure of Claim 1, wherein the at least one Group I II nitride material is located atop a sub-surface of the (111) silicon layer. Original
The semiconductor structure of Claim 1, wherein the at least one Group III nitride material layer has a topmost surface that is above, coplanar with, or below a top surface of the (100) silicon layer. Original
The semiconductor structure of Claim 1, wherein the Group III nitride material layer comprises a Group III nitride buffer layer and a Group I II nitride channel layer located on the Group I II nitride buffer layer, wherein the Group I II nitride channel layer has a top surface that is above, coplanar with, or below a top surface of the (100) silicon layer. Original
Canceled
A method of forming a semiconductor structure comprising: forming, within a single silicon die on top a semiconductor-on-insulator substrate, a first field effect transistor (FET); forming, adjacent the first FET within the single silicon die, a trench; forming a first dielectric sidewall liner structure extending along a length of an interior sidewall surface of said trench and a second dielectric sidewall liner structure extending along a length of an opposing interior sidewall surface of said trench; forming, within the trench, between the first and second dielectric sidewall liner structures a second field effect transistor formed of a Group III nitride material, the second FET connected in cascode to the first transistor, the first transistor having a gate terminal receiving an input signal, the first transistor having a drain terminal driving a source terminal of the cascode connected second transistor, the second transistor having a drain terminal providing an output signal; and forming an integrated conductive structure at an interconnect layer above said first and second FET transistors formed in said single silicon die, said formed integrated conductive structure for connecting said drain terminal of said first transistor to the source terminal of said integrated cascode connected second transistor, wherein the first and second dielectric sidewalls insulate said second field effect transistor from said cascode connected first FET, and said conductive structure of a length configured to reduce a parasitic resistance and inductance between said first FET and cascode connected second FET, wherein said forming within the single die an adjacent second FET transistor further comprises: forming the trench to extend through a (100) silicon layer and a buried insulator layer and into an upper portion of a (111) silicon layer of the semiconductor-on-insulator (SO I) substrate, and forming a Group I II nitride buffer layer within the trench. Currently amended
The method as claimed in Claim 12, wherein the integrated conductive structure for connecting said drain terminal of said first transistor to the source terminal of said integrated cascode connected second transistor includes forming a back-end-of-line (BEOL) metallization interlevel conductor at a single or multiple metallization interlevels. Original
The method as claimed in Claim 12, wherein the received input signal is a first input signal, a gate terminal of said cascode connected second transistor configured to receive a second input signal, different than said first input signal. Original
The method as claimed in Claim 12, wherein said first FET transistor is a metal oxide semiconductor FET (MOSFET) in a normally off state and includes a channel of a polarity adapted for enhancement mode FET operation. Original
The method as claimed in Claim 12, wherein said Group III nitride material includes material selected from GaN, A I N, InN, Ga I nN, A I GaN, and GaA lh1 N, said second FET transistor to be in a normally on state and includes a channel of a polarity adapted for a depletion mode FET operation. Original
Canceled
(Cu rr ently Amended) The method of Claim 11191] 12, wherein the forming the Group III nitride buffer layer comprises epitaxially growing a Group III nitride material from a sub-surface
Layer stacks claimed or described, ordered top of device to substrate.
integrated cascode GaN HEMT/Si MOSFET on SOI
Materials described outside the worked examples.
Group III nitride material
buried insulator layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2A the die area 21 having the GaN HEMT device is laterally adjacent an area 22 having the integrated Si MOSFET. The short physical distance of a …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–500000 nm | — |
Thickness | 5–1000 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,991,722Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1B is a circuit schematic depicting a second ultra low parasitic inductance cascode GaN structure integrated in a single integrated circuit chip die; SVG …
FIG. 2A the die area 21 having the GaN HEMT device is laterally adjacent an area 22 having the integrated Si MOSFET. The short physical distance of a …
FIG. 3A is a cross sectional view of the exemplary semiconductor structure corr esponding to the circuit of FIG. IA; [0013]
FIG. 4 shows a further cross-sectional view of a cascode connection of a GaN HEMT device to at least two Si MOSFET devices in the same Silicon die.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a single integrated circuit die formed on top a semiconductor-on-insulator substrate, the integrated circuit die comprising: a first field effect transistor (FET); and a second field effect transistor comprising a Group I II nitride material connected in cascode to the first transistor, the second FET transistor having a first dielectric sidewall liner structure extending along a sidewall surface of said second field effect transistor and a second dielectric sidewall liner structure extending along an opposite sidewall surface of said second field effect transistor, said first and second sidewall liner structures insulating said second field effect transistor from said cascode connected first FET, the first transistor having a gate terminal receiving an input signal, the first transistor having a drain terminal driving a source terminal of the cascode connected second transistor, the second transistor having a drain terminal providing an output signal; and an integrated conductive structure formed at an interconnect layer above said semiconductor-on-insulator substrate for connecting said drain terminal of said first transistor to the source terminal of said integrated cascode connected second transistor; said conductive structure of a length configured to reduce a parasitic resistance and inductance between said first FET and cascode connected second FET, wherein said semiconductor-on-insulator substrate includes, from bottom to top, a (111) silicon layer, a buried insulator layer and a (100) silicon layer, the second FET transistor comprising: at least one Group III nitride material layer embedded within a trench that extends through the (100) silicon layer and the buried insulator layer and into an upper portion of the (111) silicon layer. Currently amended
The semiconductor structure as claimed in Claim 1, wherein a further conductive structure formed at said one or more interconnect layers connects a gate terminal of said cascode connected second transistor to a source terminal of said first transistor. Original
The semiconductor structure as claimed in Claim 1, wherein the integrated conductive structure for connecting said drain terminal of said first transistor to the source terminal of said integrated cascode connected second transistor is formed at a back-end-of-line (BEOL) metallization interlevel or combination of metallization interlevels. Original
The semiconductor structure as claimed in Claim 1, wherein the received input signal is a first input signal, a gate terminal of said cascode connected second transistor configured to receive a second input signal, different than said first input signal. Original
The semiconductor structure as claimed in Claim 1, wherein said first FET transistor is a metal oxide semiconductor FET (MOSFET) in a normally off state and includes a channel of a polarity adapted for enhancement mode FET operation. Original
The semiconductor structure as claimed in Claim 1, wherein said Group III nitride material includes material selected from GaN, A l N, InN, Ga I nN, AlGaN, and GaAlInN, said second FET transistor to be in a normally on state and includes a channel of a polarity adapted for a depletion mode FET operation. Original
The semiconductor structure of Claim 1, wherein the at least one Group I II nitride material is located atop a sub-surface of the (111) silicon layer. Original
The semiconductor structure of Claim 1, wherein the at least one Group III nitride material layer has a topmost surface that is above, coplanar with, or below a top surface of the (100) silicon layer. Original
The semiconductor structure of Claim 1, wherein the Group III nitride material layer comprises a Group III nitride buffer layer and a Group I II nitride channel layer located on the Group I II nitride buffer layer, wherein the Group I II nitride channel layer has a top surface that is above, coplanar with, or below a top surface of the (100) silicon layer. Original
Canceled
A method of forming a semiconductor structure comprising: forming, within a single silicon die on top a semiconductor-on-insulator substrate, a first field effect transistor (FET); forming, adjacent the first FET within the single silicon die, a trench; forming a first dielectric sidewall liner structure extending along a length of an interior sidewall surface of said trench and a second dielectric sidewall liner structure extending along a length of an opposing interior sidewall surface of said trench; forming, within the trench, between the first and second dielectric sidewall liner structures a second field effect transistor formed of a Group III nitride material, the second FET connected in cascode to the first transistor, the first transistor having a gate terminal receiving an input signal, the first transistor having a drain terminal driving a source terminal of the cascode connected second transistor, the second transistor having a drain terminal providing an output signal; and forming an integrated conductive structure at an interconnect layer above said first and second FET transistors formed in said single silicon die, said formed integrated conductive structure for connecting said drain terminal of said first transistor to the source terminal of said integrated cascode connected second transistor, wherein the first and second dielectric sidewalls insulate said second field effect transistor from said cascode connected first FET, and said conductive structure of a length configured to reduce a parasitic resistance and inductance between said first FET and cascode connected second FET, wherein said forming within the single die an adjacent second FET transistor further comprises: forming the trench to extend through a (100) silicon layer and a buried insulator layer and into an upper portion of a (111) silicon layer of the semiconductor-on-insulator (SO I) substrate, and forming a Group I II nitride buffer layer within the trench. Currently amended
The method as claimed in Claim 12, wherein the integrated conductive structure for connecting said drain terminal of said first transistor to the source terminal of said integrated cascode connected second transistor includes forming a back-end-of-line (BEOL) metallization interlevel conductor at a single or multiple metallization interlevels. Original
The method as claimed in Claim 12, wherein the received input signal is a first input signal, a gate terminal of said cascode connected second transistor configured to receive a second input signal, different than said first input signal. Original
The method as claimed in Claim 12, wherein said first FET transistor is a metal oxide semiconductor FET (MOSFET) in a normally off state and includes a channel of a polarity adapted for enhancement mode FET operation. Original
The method as claimed in Claim 12, wherein said Group III nitride material includes material selected from GaN, A I N, InN, Ga I nN, A I GaN, and GaA lh1 N, said second FET transistor to be in a normally on state and includes a channel of a polarity adapted for a depletion mode FET operation. Original
Canceled
(Cu rr ently Amended) The method of Claim 11191] 12, wherein the forming the Group III nitride buffer layer comprises epitaxially growing a Group III nitride material from a sub-surface
Layer stacks claimed or described, ordered top of device to substrate.
integrated cascode GaN HEMT/Si MOSFET on SOI
Materials described outside the worked examples.
Group III nitride material
buried insulator layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2A the die area 21 having the GaN HEMT device is laterally adjacent an area 22 having the integrated Si MOSFET. The short physical distance of a …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–500000 nm | — |
Thickness | 5–1000 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,991,722Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1B is a circuit schematic depicting a second ultra low parasitic inductance cascode GaN structure integrated in a single integrated circuit chip die; SVG …
FIG. 2A the die area 21 having the GaN HEMT device is laterally adjacent an area 22 having the integrated Si MOSFET. The short physical distance of a …
FIG. 3A is a cross sectional view of the exemplary semiconductor structure corr esponding to the circuit of FIG. IA; [0013]
FIG. 4 shows a further cross-sectional view of a cascode connection of a GaN HEMT device to at least two Si MOSFET devices in the same Silicon die.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a single integrated circuit die formed on top a semiconductor-on-insulator substrate, the integrated circuit die comprising: a first field effect transistor (FET); and a second field effect transistor comprising a Group I II nitride material connected in cascode to the first transistor, the second FET transistor having a first dielectric sidewall liner structure extending along a sidewall surface of said second field effect transistor and a second dielectric sidewall liner structure extending along an opposite sidewall surface of said second field effect transistor, said first and second sidewall liner structures insulating said second field effect transistor from said cascode connected first FET, the first transistor having a gate terminal receiving an input signal, the first transistor having a drain terminal driving a source terminal of the cascode connected second transistor, the second transistor having a drain terminal providing an output signal; and an integrated conductive structure formed at an interconnect layer above said semiconductor-on-insulator substrate for connecting said drain terminal of said first transistor to the source terminal of said integrated cascode connected second transistor; said conductive structure of a length configured to reduce a parasitic resistance and inductance between said first FET and cascode connected second FET, wherein said semiconductor-on-insulator substrate includes, from bottom to top, a (111) silicon layer, a buried insulator layer and a (100) silicon layer, the second FET transistor comprising: at least one Group III nitride material layer embedded within a trench that extends through the (100) silicon layer and the buried insulator layer and into an upper portion of the (111) silicon layer. Currently amended
The semiconductor structure as claimed in Claim 1, wherein a further conductive structure formed at said one or more interconnect layers connects a gate terminal of said cascode connected second transistor to a source terminal of said first transistor. Original
The semiconductor structure as claimed in Claim 1, wherein the integrated conductive structure for connecting said drain terminal of said first transistor to the source terminal of said integrated cascode connected second transistor is formed at a back-end-of-line (BEOL) metallization interlevel or combination of metallization interlevels. Original
The semiconductor structure as claimed in Claim 1, wherein the received input signal is a first input signal, a gate terminal of said cascode connected second transistor configured to receive a second input signal, different than said first input signal. Original
The semiconductor structure as claimed in Claim 1, wherein said first FET transistor is a metal oxide semiconductor FET (MOSFET) in a normally off state and includes a channel of a polarity adapted for enhancement mode FET operation. Original
The semiconductor structure as claimed in Claim 1, wherein said Group III nitride material includes material selected from GaN, A l N, InN, Ga I nN, AlGaN, and GaAlInN, said second FET transistor to be in a normally on state and includes a channel of a polarity adapted for a depletion mode FET operation. Original
The semiconductor structure of Claim 1, wherein the at least one Group I II nitride material is located atop a sub-surface of the (111) silicon layer. Original
The semiconductor structure of Claim 1, wherein the at least one Group III nitride material layer has a topmost surface that is above, coplanar with, or below a top surface of the (100) silicon layer. Original
The semiconductor structure of Claim 1, wherein the Group III nitride material layer comprises a Group III nitride buffer layer and a Group I II nitride channel layer located on the Group I II nitride buffer layer, wherein the Group I II nitride channel layer has a top surface that is above, coplanar with, or below a top surface of the (100) silicon layer. Original
Canceled
A method of forming a semiconductor structure comprising: forming, within a single silicon die on top a semiconductor-on-insulator substrate, a first field effect transistor (FET); forming, adjacent the first FET within the single silicon die, a trench; forming a first dielectric sidewall liner structure extending along a length of an interior sidewall surface of said trench and a second dielectric sidewall liner structure extending along a length of an opposing interior sidewall surface of said trench; forming, within the trench, between the first and second dielectric sidewall liner structures a second field effect transistor formed of a Group III nitride material, the second FET connected in cascode to the first transistor, the first transistor having a gate terminal receiving an input signal, the first transistor having a drain terminal driving a source terminal of the cascode connected second transistor, the second transistor having a drain terminal providing an output signal; and forming an integrated conductive structure at an interconnect layer above said first and second FET transistors formed in said single silicon die, said formed integrated conductive structure for connecting said drain terminal of said first transistor to the source terminal of said integrated cascode connected second transistor, wherein the first and second dielectric sidewalls insulate said second field effect transistor from said cascode connected first FET, and said conductive structure of a length configured to reduce a parasitic resistance and inductance between said first FET and cascode connected second FET, wherein said forming within the single die an adjacent second FET transistor further comprises: forming the trench to extend through a (100) silicon layer and a buried insulator layer and into an upper portion of a (111) silicon layer of the semiconductor-on-insulator (SO I) substrate, and forming a Group I II nitride buffer layer within the trench. Currently amended
The method as claimed in Claim 12, wherein the integrated conductive structure for connecting said drain terminal of said first transistor to the source terminal of said integrated cascode connected second transistor includes forming a back-end-of-line (BEOL) metallization interlevel conductor at a single or multiple metallization interlevels. Original
The method as claimed in Claim 12, wherein the received input signal is a first input signal, a gate terminal of said cascode connected second transistor configured to receive a second input signal, different than said first input signal. Original
The method as claimed in Claim 12, wherein said first FET transistor is a metal oxide semiconductor FET (MOSFET) in a normally off state and includes a channel of a polarity adapted for enhancement mode FET operation. Original
The method as claimed in Claim 12, wherein said Group III nitride material includes material selected from GaN, A I N, InN, Ga I nN, A I GaN, and GaA lh1 N, said second FET transistor to be in a normally on state and includes a channel of a polarity adapted for a depletion mode FET operation. Original
Canceled
(Cu rr ently Amended) The method of Claim 11191] 12, wherein the forming the Group III nitride buffer layer comprises epitaxially growing a Group III nitride material from a sub-surface
Layer stacks claimed or described, ordered top of device to substrate.
integrated cascode GaN HEMT/Si MOSFET on SOI
Materials described outside the worked examples.
Group III nitride material
buried insulator layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2A the die area 21 having the GaN HEMT device is laterally adjacent an area 22 having the integrated Si MOSFET. The short physical distance of a …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–500000 nm | — |
Thickness | 5–1000 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,991,722Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1B is a circuit schematic depicting a second ultra low parasitic inductance cascode GaN structure integrated in a single integrated circuit chip die; SVG …
FIG. 2A the die area 21 having the GaN HEMT device is laterally adjacent an area 22 having the integrated Si MOSFET. The short physical distance of a …
FIG. 3A is a cross sectional view of the exemplary semiconductor structure corr esponding to the circuit of FIG. IA; [0013]
FIG. 4 shows a further cross-sectional view of a cascode connection of a GaN HEMT device to at least two Si MOSFET devices in the same Silicon die.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a single integrated circuit die formed on top a semiconductor-on-insulator substrate, the integrated circuit die comprising: a first field effect transistor (FET); and a second field effect transistor comprising a Group I II nitride material connected in cascode to the first transistor, the second FET transistor having a first dielectric sidewall liner structure extending along a sidewall surface of said second field effect transistor and a second dielectric sidewall liner structure extending along an opposite sidewall surface of said second field effect transistor, said first and second sidewall liner structures insulating said second field effect transistor from said cascode connected first FET, the first transistor having a gate terminal receiving an input signal, the first transistor having a drain terminal driving a source terminal of the cascode connected second transistor, the second transistor having a drain terminal providing an output signal; and an integrated conductive structure formed at an interconnect layer above said semiconductor-on-insulator substrate for connecting said drain terminal of said first transistor to the source terminal of said integrated cascode connected second transistor; said conductive structure of a length configured to reduce a parasitic resistance and inductance between said first FET and cascode connected second FET, wherein said semiconductor-on-insulator substrate includes, from bottom to top, a (111) silicon layer, a buried insulator layer and a (100) silicon layer, the second FET transistor comprising: at least one Group III nitride material layer embedded within a trench that extends through the (100) silicon layer and the buried insulator layer and into an upper portion of the (111) silicon layer. Currently amended
The semiconductor structure as claimed in Claim 1, wherein a further conductive structure formed at said one or more interconnect layers connects a gate terminal of said cascode connected second transistor to a source terminal of said first transistor. Original
The semiconductor structure as claimed in Claim 1, wherein the integrated conductive structure for connecting said drain terminal of said first transistor to the source terminal of said integrated cascode connected second transistor is formed at a back-end-of-line (BEOL) metallization interlevel or combination of metallization interlevels. Original
The semiconductor structure as claimed in Claim 1, wherein the received input signal is a first input signal, a gate terminal of said cascode connected second transistor configured to receive a second input signal, different than said first input signal. Original
The semiconductor structure as claimed in Claim 1, wherein said first FET transistor is a metal oxide semiconductor FET (MOSFET) in a normally off state and includes a channel of a polarity adapted for enhancement mode FET operation. Original
The semiconductor structure as claimed in Claim 1, wherein said Group III nitride material includes material selected from GaN, A l N, InN, Ga I nN, AlGaN, and GaAlInN, said second FET transistor to be in a normally on state and includes a channel of a polarity adapted for a depletion mode FET operation. Original
The semiconductor structure of Claim 1, wherein the at least one Group I II nitride material is located atop a sub-surface of the (111) silicon layer. Original
The semiconductor structure of Claim 1, wherein the at least one Group III nitride material layer has a topmost surface that is above, coplanar with, or below a top surface of the (100) silicon layer. Original
The semiconductor structure of Claim 1, wherein the Group III nitride material layer comprises a Group III nitride buffer layer and a Group I II nitride channel layer located on the Group I II nitride buffer layer, wherein the Group I II nitride channel layer has a top surface that is above, coplanar with, or below a top surface of the (100) silicon layer. Original
Canceled
A method of forming a semiconductor structure comprising: forming, within a single silicon die on top a semiconductor-on-insulator substrate, a first field effect transistor (FET); forming, adjacent the first FET within the single silicon die, a trench; forming a first dielectric sidewall liner structure extending along a length of an interior sidewall surface of said trench and a second dielectric sidewall liner structure extending along a length of an opposing interior sidewall surface of said trench; forming, within the trench, between the first and second dielectric sidewall liner structures a second field effect transistor formed of a Group III nitride material, the second FET connected in cascode to the first transistor, the first transistor having a gate terminal receiving an input signal, the first transistor having a drain terminal driving a source terminal of the cascode connected second transistor, the second transistor having a drain terminal providing an output signal; and forming an integrated conductive structure at an interconnect layer above said first and second FET transistors formed in said single silicon die, said formed integrated conductive structure for connecting said drain terminal of said first transistor to the source terminal of said integrated cascode connected second transistor, wherein the first and second dielectric sidewalls insulate said second field effect transistor from said cascode connected first FET, and said conductive structure of a length configured to reduce a parasitic resistance and inductance between said first FET and cascode connected second FET, wherein said forming within the single die an adjacent second FET transistor further comprises: forming the trench to extend through a (100) silicon layer and a buried insulator layer and into an upper portion of a (111) silicon layer of the semiconductor-on-insulator (SO I) substrate, and forming a Group I II nitride buffer layer within the trench. Currently amended
The method as claimed in Claim 12, wherein the integrated conductive structure for connecting said drain terminal of said first transistor to the source terminal of said integrated cascode connected second transistor includes forming a back-end-of-line (BEOL) metallization interlevel conductor at a single or multiple metallization interlevels. Original
The method as claimed in Claim 12, wherein the received input signal is a first input signal, a gate terminal of said cascode connected second transistor configured to receive a second input signal, different than said first input signal. Original
The method as claimed in Claim 12, wherein said first FET transistor is a metal oxide semiconductor FET (MOSFET) in a normally off state and includes a channel of a polarity adapted for enhancement mode FET operation. Original
The method as claimed in Claim 12, wherein said Group III nitride material includes material selected from GaN, A I N, InN, Ga I nN, A I GaN, and GaA lh1 N, said second FET transistor to be in a normally on state and includes a channel of a polarity adapted for a depletion mode FET operation. Original
Canceled
(Cu rr ently Amended) The method of Claim 11191] 12, wherein the forming the Group III nitride buffer layer comprises epitaxially growing a Group III nitride material from a sub-surface
Layer stacks claimed or described, ordered top of device to substrate.
integrated cascode GaN HEMT/Si MOSFET on SOI
Materials described outside the worked examples.
Group III nitride material
buried insulator layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2A the die area 21 having the GaN HEMT device is laterally adjacent an area 22 having the integrated Si MOSFET. The short physical distance of a …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–500000 nm | — |
Thickness | 5–1000 nm |
Related documents with shared materials, methods, properties, or citations.
(111) silicon layer
Si
GaN
AlN
InN
GaInN
AlGaN
GaAlInN
Group III nitride buffer layer
FIG. 2A the die area 21 having the GaN HEMT device is laterally adjacent an area 22 having the integrated Si MOSFET. The short physical distance of a …
| — |
Thickness | 200–1500 µm | — |
Thickness | 5–100 nm | — |
Thickness | 1–2 cm | — |
Thickness | ≤ 1 mm | — |
Thickness | ≤ 500 nm | — |
(111) silicon layer
Si
GaN
AlN
InN
GaInN
AlGaN
GaAlInN
Group III nitride buffer layer
FIG. 2A the die area 21 having the GaN HEMT device is laterally adjacent an area 22 having the integrated Si MOSFET. The short physical distance of a …
| — |
Thickness | 200–1500 µm | — |
Thickness | 5–100 nm | — |
Thickness | 1–2 cm | — |
Thickness | ≤ 1 mm | — |
Thickness | ≤ 500 nm | — |
(111) silicon layer
Si
GaN
AlN
InN
GaInN
AlGaN
GaAlInN
Group III nitride buffer layer
FIG. 2A the die area 21 having the GaN HEMT device is laterally adjacent an area 22 having the integrated Si MOSFET. The short physical distance of a …
| — |
Thickness | 200–1500 µm | — |
Thickness | 5–100 nm | — |
Thickness | 1–2 cm | — |
Thickness | ≤ 1 mm | — |
Thickness | ≤ 500 nm | — |
(111) silicon layer
Si
GaN
AlN
InN
GaInN
AlGaN
GaAlInN
Group III nitride buffer layer
FIG. 2A the die area 21 having the GaN HEMT device is laterally adjacent an area 22 having the integrated Si MOSFET. The short physical distance of a …
| — |
Thickness | 200–1500 µm | — |
Thickness | 5–100 nm | — |
Thickness | 1–2 cm | — |
Thickness | ≤ 1 mm | — |
Thickness | ≤ 500 nm | — |