Patent
US 11,050,339INTEGRATED CIRCUIT WITH MULTIPLE GALLIUM NITRIDE TRANSISTOR SETS
David C. Reusch
US
Copyright © 2026 Matter42. All rights reserved.
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US 11,050,339Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As shown, GaN transistor 200 includes a semiconductor substrate 202 (e.g., silicon) and an isolation layer 204 (e.g., aluminum nitride) over the …
FIG. 2 shows a GaN transistor topology 200 in accordance with various embodiments. In at least some embodiments, the GaN transistor topology 200 is used to …
FIG. 3 shows a block diagram of a multi-stage DC-DC converter 300 in accordance with various embodiments. As shown, the multi-stage DC-DC converter 300 …
FIG. 4A shows a schematic diagram of an inductor/inductor/capacitor (LLC) resonant converter topology 400. As shown, the LLC resonant converter topology 400 …
FIG. 5 B, a single transistor forward converter topology 510 is represented. As shown, the single transistor forward converter topology 510 includes an input …
FIG. 6A shows a schematic diagram of a stage 3 DC-DC converter topology 600 in accordance with various embodiments. Specifically, the stage 3 DC-DC converter …
FIG. 7 shows a perspective view 700 of a system on chip (SoC) device 702 and related P C B 710. The SoC device 702 inc l udes a single integrated circuit with …
FIG. 8. Alternatively, if signals (e.g., V 1OU T, V₂ ou T, V₃ ouT) are not output from the device 802 for each of the integrated circuit portions 812, 822, …
FIG. 9. Alternatively, if signals (e.g., V2ou T) are not to be output from the device 930 for each of the integrated circuit portions 932 and 942, then the …
FIG. 10. Alternatively, if signals (e.g., V 1ou T) are not to be output from the device 1010 for each of the integrated circuit portions 1012 and 1022, then …
FIG. 11. Alternatively, if signals (e.g., V₂ ouT, V3ou T) are not output from the device 1130 for each of the integrated circuit portions 1132, 1142, and 1152, …
FIG. 12. In different embodiments, the multi-stage converter SoC device 1210 is used in other DC-DC converter scenarios. F or example, in one DC-DC converter …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit, comprising: a plurality of G aN transistor sets formed on a substrate, wherein a first set of the plurality of G aN transistor sets includes transistors with a first drain-to-source distance, and wherein a second set of the plurality of G aN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance; and substrate well isolation between each of the plurality of G aN transistor sets. Original
The integrated circuit of claim 1, wherein a third set of the plurality of GaN transistor sets includes transistors with a third drain-to-source distance that is greater than the second drain-to-source distance. Original
An integrated circuit, comprising: a plurality of G aN transistor sets formed on a substrate, wherein a first set of the plurality of G aN transistor sets includes transistors with a first drain-to-source distance, and wherein a second set of the plurality of G aN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance; and silicon on insulator (SO I) isolation between each of the plurality of G aN transistor sets. Original
The integrated circuit of claim 5, wherein a third set of the plurality of GaN transistor sets includes transistors with a third drain-to-source distance that is greater than the second drain-to-source distance. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaN integrated circuit with substrate well isolation
GaN integrated circuit with SOI isolation
Materials described outside the worked examples.
GaN
silicon on insulator (SOI)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. As shown, GaN transistor 200 includes a semiconductor substrate 202 (e.g., silicon) and an isolation layer 204 (e.g., aluminum nitride) over the …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,050,339Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As shown, GaN transistor 200 includes a semiconductor substrate 202 (e.g., silicon) and an isolation layer 204 (e.g., aluminum nitride) over the …
FIG. 2 shows a GaN transistor topology 200 in accordance with various embodiments. In at least some embodiments, the GaN transistor topology 200 is used to …
FIG. 3 shows a block diagram of a multi-stage DC-DC converter 300 in accordance with various embodiments. As shown, the multi-stage DC-DC converter 300 …
FIG. 4A shows a schematic diagram of an inductor/inductor/capacitor (LLC) resonant converter topology 400. As shown, the LLC resonant converter topology 400 …
FIG. 5 B, a single transistor forward converter topology 510 is represented. As shown, the single transistor forward converter topology 510 includes an input …
FIG. 6A shows a schematic diagram of a stage 3 DC-DC converter topology 600 in accordance with various embodiments. Specifically, the stage 3 DC-DC converter …
FIG. 7 shows a perspective view 700 of a system on chip (SoC) device 702 and related P C B 710. The SoC device 702 inc l udes a single integrated circuit with …
FIG. 8. Alternatively, if signals (e.g., V 1OU T, V₂ ou T, V₃ ouT) are not output from the device 802 for each of the integrated circuit portions 812, 822, …
FIG. 9. Alternatively, if signals (e.g., V2ou T) are not to be output from the device 930 for each of the integrated circuit portions 932 and 942, then the …
FIG. 10. Alternatively, if signals (e.g., V 1ou T) are not to be output from the device 1010 for each of the integrated circuit portions 1012 and 1022, then …
FIG. 11. Alternatively, if signals (e.g., V₂ ouT, V3ou T) are not output from the device 1130 for each of the integrated circuit portions 1132, 1142, and 1152, …
FIG. 12. In different embodiments, the multi-stage converter SoC device 1210 is used in other DC-DC converter scenarios. F or example, in one DC-DC converter …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit, comprising: a plurality of G aN transistor sets formed on a substrate, wherein a first set of the plurality of G aN transistor sets includes transistors with a first drain-to-source distance, and wherein a second set of the plurality of G aN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance; and substrate well isolation between each of the plurality of G aN transistor sets. Original
The integrated circuit of claim 1, wherein a third set of the plurality of GaN transistor sets includes transistors with a third drain-to-source distance that is greater than the second drain-to-source distance. Original
An integrated circuit, comprising: a plurality of G aN transistor sets formed on a substrate, wherein a first set of the plurality of G aN transistor sets includes transistors with a first drain-to-source distance, and wherein a second set of the plurality of G aN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance; and silicon on insulator (SO I) isolation between each of the plurality of G aN transistor sets. Original
The integrated circuit of claim 5, wherein a third set of the plurality of GaN transistor sets includes transistors with a third drain-to-source distance that is greater than the second drain-to-source distance. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaN integrated circuit with substrate well isolation
GaN integrated circuit with SOI isolation
Materials described outside the worked examples.
GaN
silicon on insulator (SOI)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. As shown, GaN transistor 200 includes a semiconductor substrate 202 (e.g., silicon) and an isolation layer 204 (e.g., aluminum nitride) over the …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,050,339Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As shown, GaN transistor 200 includes a semiconductor substrate 202 (e.g., silicon) and an isolation layer 204 (e.g., aluminum nitride) over the …
FIG. 2 shows a GaN transistor topology 200 in accordance with various embodiments. In at least some embodiments, the GaN transistor topology 200 is used to …
FIG. 3 shows a block diagram of a multi-stage DC-DC converter 300 in accordance with various embodiments. As shown, the multi-stage DC-DC converter 300 …
FIG. 4A shows a schematic diagram of an inductor/inductor/capacitor (LLC) resonant converter topology 400. As shown, the LLC resonant converter topology 400 …
FIG. 5 B, a single transistor forward converter topology 510 is represented. As shown, the single transistor forward converter topology 510 includes an input …
FIG. 6A shows a schematic diagram of a stage 3 DC-DC converter topology 600 in accordance with various embodiments. Specifically, the stage 3 DC-DC converter …
FIG. 7 shows a perspective view 700 of a system on chip (SoC) device 702 and related P C B 710. The SoC device 702 inc l udes a single integrated circuit with …
FIG. 8. Alternatively, if signals (e.g., V 1OU T, V₂ ou T, V₃ ouT) are not output from the device 802 for each of the integrated circuit portions 812, 822, …
FIG. 9. Alternatively, if signals (e.g., V2ou T) are not to be output from the device 930 for each of the integrated circuit portions 932 and 942, then the …
FIG. 10. Alternatively, if signals (e.g., V 1ou T) are not to be output from the device 1010 for each of the integrated circuit portions 1012 and 1022, then …
FIG. 11. Alternatively, if signals (e.g., V₂ ouT, V3ou T) are not output from the device 1130 for each of the integrated circuit portions 1132, 1142, and 1152, …
FIG. 12. In different embodiments, the multi-stage converter SoC device 1210 is used in other DC-DC converter scenarios. F or example, in one DC-DC converter …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit, comprising: a plurality of G aN transistor sets formed on a substrate, wherein a first set of the plurality of G aN transistor sets includes transistors with a first drain-to-source distance, and wherein a second set of the plurality of G aN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance; and substrate well isolation between each of the plurality of G aN transistor sets. Original
The integrated circuit of claim 1, wherein a third set of the plurality of GaN transistor sets includes transistors with a third drain-to-source distance that is greater than the second drain-to-source distance. Original
An integrated circuit, comprising: a plurality of G aN transistor sets formed on a substrate, wherein a first set of the plurality of G aN transistor sets includes transistors with a first drain-to-source distance, and wherein a second set of the plurality of G aN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance; and silicon on insulator (SO I) isolation between each of the plurality of G aN transistor sets. Original
The integrated circuit of claim 5, wherein a third set of the plurality of GaN transistor sets includes transistors with a third drain-to-source distance that is greater than the second drain-to-source distance. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaN integrated circuit with substrate well isolation
GaN integrated circuit with SOI isolation
Materials described outside the worked examples.
GaN
silicon on insulator (SOI)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. As shown, GaN transistor 200 includes a semiconductor substrate 202 (e.g., silicon) and an isolation layer 204 (e.g., aluminum nitride) over the …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,050,339Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As shown, GaN transistor 200 includes a semiconductor substrate 202 (e.g., silicon) and an isolation layer 204 (e.g., aluminum nitride) over the …
FIG. 2 shows a GaN transistor topology 200 in accordance with various embodiments. In at least some embodiments, the GaN transistor topology 200 is used to …
FIG. 3 shows a block diagram of a multi-stage DC-DC converter 300 in accordance with various embodiments. As shown, the multi-stage DC-DC converter 300 …
FIG. 4A shows a schematic diagram of an inductor/inductor/capacitor (LLC) resonant converter topology 400. As shown, the LLC resonant converter topology 400 …
FIG. 5 B, a single transistor forward converter topology 510 is represented. As shown, the single transistor forward converter topology 510 includes an input …
FIG. 6A shows a schematic diagram of a stage 3 DC-DC converter topology 600 in accordance with various embodiments. Specifically, the stage 3 DC-DC converter …
FIG. 7 shows a perspective view 700 of a system on chip (SoC) device 702 and related P C B 710. The SoC device 702 inc l udes a single integrated circuit with …
FIG. 8. Alternatively, if signals (e.g., V 1OU T, V₂ ou T, V₃ ouT) are not output from the device 802 for each of the integrated circuit portions 812, 822, …
FIG. 9. Alternatively, if signals (e.g., V2ou T) are not to be output from the device 930 for each of the integrated circuit portions 932 and 942, then the …
FIG. 10. Alternatively, if signals (e.g., V 1ou T) are not to be output from the device 1010 for each of the integrated circuit portions 1012 and 1022, then …
FIG. 11. Alternatively, if signals (e.g., V₂ ouT, V3ou T) are not output from the device 1130 for each of the integrated circuit portions 1132, 1142, and 1152, …
FIG. 12. In different embodiments, the multi-stage converter SoC device 1210 is used in other DC-DC converter scenarios. F or example, in one DC-DC converter …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit, comprising: a plurality of G aN transistor sets formed on a substrate, wherein a first set of the plurality of G aN transistor sets includes transistors with a first drain-to-source distance, and wherein a second set of the plurality of G aN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance; and substrate well isolation between each of the plurality of G aN transistor sets. Original
The integrated circuit of claim 1, wherein a third set of the plurality of GaN transistor sets includes transistors with a third drain-to-source distance that is greater than the second drain-to-source distance. Original
An integrated circuit, comprising: a plurality of G aN transistor sets formed on a substrate, wherein a first set of the plurality of G aN transistor sets includes transistors with a first drain-to-source distance, and wherein a second set of the plurality of G aN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance; and silicon on insulator (SO I) isolation between each of the plurality of G aN transistor sets. Original
The integrated circuit of claim 5, wherein a third set of the plurality of GaN transistor sets includes transistors with a third drain-to-source distance that is greater than the second drain-to-source distance. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaN integrated circuit with substrate well isolation
GaN integrated circuit with SOI isolation
Materials described outside the worked examples.
GaN
silicon on insulator (SOI)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. As shown, GaN transistor 200 includes a semiconductor substrate 202 (e.g., silicon) and an isolation layer 204 (e.g., aluminum nitride) over the …
Related documents with shared materials, methods, properties, or citations.
FIG. 2 shows a GaN transistor topology 200 in accordance with various embodiments. In at least some embodiments, the GaN transistor topology 200 is used to …
FIG. 5 B, a single transistor forward converter topology 510 is represented. As shown, the single transistor forward converter topology 510 includes an input …
FIG. 6A shows a schematic diagram of a stage 3 DC-DC converter topology 600 in accordance with various embodiments. Specifically, the stage 3 DC-DC converter …
FIG. 7 shows a perspective view 700 of a system on chip (SoC) device 702 and related P C B 710. The SoC device 702 inc l udes a single integrated circuit with …
FIG. 8. Alternatively, if signals (e.g., V 1OU T, V₂ ou T, V₃ ouT) are not output from the device 802 for each of the integrated circuit portions 812, 822, …
FIG. 2 shows a GaN transistor topology 200 in accordance with various embodiments. In at least some embodiments, the GaN transistor topology 200 is used to …
FIG. 5 B, a single transistor forward converter topology 510 is represented. As shown, the single transistor forward converter topology 510 includes an input …
FIG. 6A shows a schematic diagram of a stage 3 DC-DC converter topology 600 in accordance with various embodiments. Specifically, the stage 3 DC-DC converter …
FIG. 7 shows a perspective view 700 of a system on chip (SoC) device 702 and related P C B 710. The SoC device 702 inc l udes a single integrated circuit with …
FIG. 8. Alternatively, if signals (e.g., V 1OU T, V₂ ou T, V₃ ouT) are not output from the device 802 for each of the integrated circuit portions 812, 822, …
FIG. 2 shows a GaN transistor topology 200 in accordance with various embodiments. In at least some embodiments, the GaN transistor topology 200 is used to …
FIG. 5 B, a single transistor forward converter topology 510 is represented. As shown, the single transistor forward converter topology 510 includes an input …
FIG. 6A shows a schematic diagram of a stage 3 DC-DC converter topology 600 in accordance with various embodiments. Specifically, the stage 3 DC-DC converter …
FIG. 7 shows a perspective view 700 of a system on chip (SoC) device 702 and related P C B 710. The SoC device 702 inc l udes a single integrated circuit with …
FIG. 8. Alternatively, if signals (e.g., V 1OU T, V₂ ou T, V₃ ouT) are not output from the device 802 for each of the integrated circuit portions 812, 822, …
FIG. 2 shows a GaN transistor topology 200 in accordance with various embodiments. In at least some embodiments, the GaN transistor topology 200 is used to …
FIG. 5 B, a single transistor forward converter topology 510 is represented. As shown, the single transistor forward converter topology 510 includes an input …
FIG. 6A shows a schematic diagram of a stage 3 DC-DC converter topology 600 in accordance with various embodiments. Specifically, the stage 3 DC-DC converter …
FIG. 7 shows a perspective view 700 of a system on chip (SoC) device 702 and related P C B 710. The SoC device 702 inc l udes a single integrated circuit with …
FIG. 8. Alternatively, if signals (e.g., V 1OU T, V₂ ou T, V₃ ouT) are not output from the device 802 for each of the integrated circuit portions 812, 822, …