Patent
US 9,093,509GRAPHENE ELECTRONIC DEVICES
Jin-seong Heo
US
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Patent
Atlas literature
Patent
US 9,093,509Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional diagram illustrating graphene electronic devices according to some example embodiments; [0014]
FIG. 2 is a plan diagram illustrating a graphene electronic device of
FIGS. 3 and 4 are plan diagrams illustrating graphene channel layers according to other example embodiments; [0016]
FIG. 4, nanoholes 134 may be arranged in a zigzag pattern in a width W direction of the graphene channel layer 130. Example embodiments include any …
FIG. 5 is a graph illustrating a performance curve of a field effect transistor according to at least one example embodiment; [0017]
FIG. 6. [0019] It should be noted that these figures are intended to illustrate the general characteristics of methods, structure and/or materials utilized in …
FIG. 7 is a plan diagram illustrating a graphene electronic device of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene electronic device, comprising: a gate electrode; a gate insulating layer on the gate electrode; a graphene channel layer on the gate insulating layer, the graphene channel layer including a plurality of nanoholes arranged in a line pattern that extends along a width direction of the graphene channel layer and is substantially perpendicular to a length direction of the graphene channel layer, the plurality of nanoholes being entire nanoholes of substantially a same size included in the graphene channel layer; and a source electrode and a drain electrode spaced apart in the length direction on the graphene channel layer.
The graphene electronic device of claim 1, wherein the gate electrode is a silicon substrate.
The graphene electronic device of claim 1, wherein a width of the graphene channel layer is about 100 nm to about 5 pm. 4-7..
The graphene electronic device of claim 1, wherein a diameter of each of the plurality of the nanoholes is about 1 nm to about 20 nm.
The graphene electronic device of claim 1, wherein the graphene channel layer includes one of a single layer of graphene and bi-layers of
The graphene electronic device of claim 1, spaced apart from the source electrode by a same
The graphene electronic device of claim 1, center region of the graphene channel layer. 25. -
canceled
canceled
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canceled
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canceled
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canceled
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canceled graphene. 11.-21. wherein each one of the plurality of nanoholes is distance. previously presented wherein the entire nanoholes are aligned in a
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (bottom-gate)
graphene field-effect transistor (top-gate)
Materials described outside the worked examples.
graphene
C
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a graph illustrating a performance curve of a field effect transistor according to at least one example embodiment; [0017]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
nanohole diameter | 1–20 nm | C |
graphene channel layer width | 100–5000 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,093,509Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional diagram illustrating graphene electronic devices according to some example embodiments; [0014]
FIG. 2 is a plan diagram illustrating a graphene electronic device of
FIGS. 3 and 4 are plan diagrams illustrating graphene channel layers according to other example embodiments; [0016]
FIG. 4, nanoholes 134 may be arranged in a zigzag pattern in a width W direction of the graphene channel layer 130. Example embodiments include any …
FIG. 5 is a graph illustrating a performance curve of a field effect transistor according to at least one example embodiment; [0017]
FIG. 6. [0019] It should be noted that these figures are intended to illustrate the general characteristics of methods, structure and/or materials utilized in …
FIG. 7 is a plan diagram illustrating a graphene electronic device of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene electronic device, comprising: a gate electrode; a gate insulating layer on the gate electrode; a graphene channel layer on the gate insulating layer, the graphene channel layer including a plurality of nanoholes arranged in a line pattern that extends along a width direction of the graphene channel layer and is substantially perpendicular to a length direction of the graphene channel layer, the plurality of nanoholes being entire nanoholes of substantially a same size included in the graphene channel layer; and a source electrode and a drain electrode spaced apart in the length direction on the graphene channel layer.
The graphene electronic device of claim 1, wherein the gate electrode is a silicon substrate.
The graphene electronic device of claim 1, wherein a width of the graphene channel layer is about 100 nm to about 5 pm. 4-7..
The graphene electronic device of claim 1, wherein a diameter of each of the plurality of the nanoholes is about 1 nm to about 20 nm.
The graphene electronic device of claim 1, wherein the graphene channel layer includes one of a single layer of graphene and bi-layers of
The graphene electronic device of claim 1, spaced apart from the source electrode by a same
The graphene electronic device of claim 1, center region of the graphene channel layer. 25. -
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled graphene. 11.-21. wherein each one of the plurality of nanoholes is distance. previously presented wherein the entire nanoholes are aligned in a
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (bottom-gate)
graphene field-effect transistor (top-gate)
Materials described outside the worked examples.
graphene
C
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a graph illustrating a performance curve of a field effect transistor according to at least one example embodiment; [0017]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
nanohole diameter | 1–20 nm | C |
graphene channel layer width | 100–5000 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,093,509Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional diagram illustrating graphene electronic devices according to some example embodiments; [0014]
FIG. 2 is a plan diagram illustrating a graphene electronic device of
FIGS. 3 and 4 are plan diagrams illustrating graphene channel layers according to other example embodiments; [0016]
FIG. 4, nanoholes 134 may be arranged in a zigzag pattern in a width W direction of the graphene channel layer 130. Example embodiments include any …
FIG. 5 is a graph illustrating a performance curve of a field effect transistor according to at least one example embodiment; [0017]
FIG. 6. [0019] It should be noted that these figures are intended to illustrate the general characteristics of methods, structure and/or materials utilized in …
FIG. 7 is a plan diagram illustrating a graphene electronic device of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene electronic device, comprising: a gate electrode; a gate insulating layer on the gate electrode; a graphene channel layer on the gate insulating layer, the graphene channel layer including a plurality of nanoholes arranged in a line pattern that extends along a width direction of the graphene channel layer and is substantially perpendicular to a length direction of the graphene channel layer, the plurality of nanoholes being entire nanoholes of substantially a same size included in the graphene channel layer; and a source electrode and a drain electrode spaced apart in the length direction on the graphene channel layer.
The graphene electronic device of claim 1, wherein the gate electrode is a silicon substrate.
The graphene electronic device of claim 1, wherein a width of the graphene channel layer is about 100 nm to about 5 pm. 4-7..
The graphene electronic device of claim 1, wherein a diameter of each of the plurality of the nanoholes is about 1 nm to about 20 nm.
The graphene electronic device of claim 1, wherein the graphene channel layer includes one of a single layer of graphene and bi-layers of
The graphene electronic device of claim 1, spaced apart from the source electrode by a same
The graphene electronic device of claim 1, center region of the graphene channel layer. 25. -
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled graphene. 11.-21. wherein each one of the plurality of nanoholes is distance. previously presented wherein the entire nanoholes are aligned in a
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (bottom-gate)
graphene field-effect transistor (top-gate)
Materials described outside the worked examples.
graphene
C
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a graph illustrating a performance curve of a field effect transistor according to at least one example embodiment; [0017]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
nanohole diameter | 1–20 nm | C |
graphene channel layer width | 100–5000 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,093,509Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional diagram illustrating graphene electronic devices according to some example embodiments; [0014]
FIG. 2 is a plan diagram illustrating a graphene electronic device of
FIGS. 3 and 4 are plan diagrams illustrating graphene channel layers according to other example embodiments; [0016]
FIG. 4, nanoholes 134 may be arranged in a zigzag pattern in a width W direction of the graphene channel layer 130. Example embodiments include any …
FIG. 5 is a graph illustrating a performance curve of a field effect transistor according to at least one example embodiment; [0017]
FIG. 6. [0019] It should be noted that these figures are intended to illustrate the general characteristics of methods, structure and/or materials utilized in …
FIG. 7 is a plan diagram illustrating a graphene electronic device of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene electronic device, comprising: a gate electrode; a gate insulating layer on the gate electrode; a graphene channel layer on the gate insulating layer, the graphene channel layer including a plurality of nanoholes arranged in a line pattern that extends along a width direction of the graphene channel layer and is substantially perpendicular to a length direction of the graphene channel layer, the plurality of nanoholes being entire nanoholes of substantially a same size included in the graphene channel layer; and a source electrode and a drain electrode spaced apart in the length direction on the graphene channel layer.
The graphene electronic device of claim 1, wherein the gate electrode is a silicon substrate.
The graphene electronic device of claim 1, wherein a width of the graphene channel layer is about 100 nm to about 5 pm. 4-7..
The graphene electronic device of claim 1, wherein a diameter of each of the plurality of the nanoholes is about 1 nm to about 20 nm.
The graphene electronic device of claim 1, wherein the graphene channel layer includes one of a single layer of graphene and bi-layers of
The graphene electronic device of claim 1, spaced apart from the source electrode by a same
The graphene electronic device of claim 1, center region of the graphene channel layer. 25. -
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled graphene. 11.-21. wherein each one of the plurality of nanoholes is distance. previously presented wherein the entire nanoholes are aligned in a
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (bottom-gate)
graphene field-effect transistor (top-gate)
Materials described outside the worked examples.
graphene
C
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a graph illustrating a performance curve of a field effect transistor according to at least one example embodiment; [0017]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
nanohole diameter | 1–20 nm | C |
graphene channel layer width | 100–5000 nm |
Related documents with shared materials, methods, properties, or citations.
gate insulating layer/gate oxide
silicon oxide
SiO₂
FIG. 5 is a graph illustrating a performance curve of a field effect transistor according to at least one example embodiment; [0017]
distance between nanoholes | 1–20 nm | C |
gate insulating layer (silicon oxide) thickness | 100–300 nm | SiO₂ |
Thickness | 5–30 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 20 nm | — |
gate insulating layer/gate oxide
silicon oxide
SiO₂
FIG. 5 is a graph illustrating a performance curve of a field effect transistor according to at least one example embodiment; [0017]
distance between nanoholes | 1–20 nm | C |
gate insulating layer (silicon oxide) thickness | 100–300 nm | SiO₂ |
Thickness | 5–30 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 20 nm | — |
gate insulating layer/gate oxide
silicon oxide
SiO₂
FIG. 5 is a graph illustrating a performance curve of a field effect transistor according to at least one example embodiment; [0017]
distance between nanoholes | 1–20 nm | C |
gate insulating layer (silicon oxide) thickness | 100–300 nm | SiO₂ |
Thickness | 5–30 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 20 nm | — |
gate insulating layer/gate oxide
silicon oxide
SiO₂
FIG. 5 is a graph illustrating a performance curve of a field effect transistor according to at least one example embodiment; [0017]
distance between nanoholes | 1–20 nm | C |
gate insulating layer (silicon oxide) thickness | 100–300 nm | SiO₂ |
Thickness | 5–30 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 20 nm | — |