Patent
US 9,515,222Gallium Nitride on 3C-SiC Composite Wafer
Peter WARD
US
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Patent
Atlas literature
Patent
US 9,515,222Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a monocrystalline silicon wafer; 5 spaced apart monocrystalline silicon carbide layers disposed directly on the silicon wafer; amorphous and/or polycrystalline silicon carbide layers disposed directly on the silicon wafer between the monocrystalline silicon carbide layers; first gallium nitride layers disposed on the monocrystalline silicon carbide 10 layers; and second gallium nitride layers disposed on the amorphous and/or polycrystalline silicon carbide layers.
A semiconductor structure according to claim 1, wherein the silicon carbide 15 layers comprise 3-step cubic silicon carbide.
A semiconductor structure according to claim 1, wherein the first gallium nitride layers comprise monocrystalline cubic gallium nitride.
20 4. A semiconductor structure according to claim 1, wherein the second gallium nitride layers comprise amorphous and/or polycrystalline gallium nitride.
A semiconductor structure according to claim 1, wherein the first gallium nitride layers are disposed directly on the monocrystalline silicon carbide layers, and the second gallium nitride layers are disposed directly on the amorphous and/or 30 polycrystalline silicon carbide layers.
A semiconductor structure according to claim 1, wherein the second gallium nitride layers are configured to reduce wafer stress and bow-causing forces.
0228-1-MHIQBAL M&C PC₉₂₇₀₅₉USB 15
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-SiC-on-Si composite semiconductor structure
Materials described outside the worked examples.
monocrystalline silicon wafer
Si
monocrystalline silicon carbide
SiC
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
silicon wafer initial bow | ≤ 25 um | Si |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,515,222Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a monocrystalline silicon wafer; 5 spaced apart monocrystalline silicon carbide layers disposed directly on the silicon wafer; amorphous and/or polycrystalline silicon carbide layers disposed directly on the silicon wafer between the monocrystalline silicon carbide layers; first gallium nitride layers disposed on the monocrystalline silicon carbide 10 layers; and second gallium nitride layers disposed on the amorphous and/or polycrystalline silicon carbide layers.
A semiconductor structure according to claim 1, wherein the silicon carbide 15 layers comprise 3-step cubic silicon carbide.
A semiconductor structure according to claim 1, wherein the first gallium nitride layers comprise monocrystalline cubic gallium nitride.
20 4. A semiconductor structure according to claim 1, wherein the second gallium nitride layers comprise amorphous and/or polycrystalline gallium nitride.
A semiconductor structure according to claim 1, wherein the first gallium nitride layers are disposed directly on the monocrystalline silicon carbide layers, and the second gallium nitride layers are disposed directly on the amorphous and/or 30 polycrystalline silicon carbide layers.
A semiconductor structure according to claim 1, wherein the second gallium nitride layers are configured to reduce wafer stress and bow-causing forces.
0228-1-MHIQBAL M&C PC₉₂₇₀₅₉USB 15
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-SiC-on-Si composite semiconductor structure
Materials described outside the worked examples.
monocrystalline silicon wafer
Si
monocrystalline silicon carbide
SiC
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
silicon wafer initial bow | ≤ 25 um | Si |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,515,222Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a monocrystalline silicon wafer; 5 spaced apart monocrystalline silicon carbide layers disposed directly on the silicon wafer; amorphous and/or polycrystalline silicon carbide layers disposed directly on the silicon wafer between the monocrystalline silicon carbide layers; first gallium nitride layers disposed on the monocrystalline silicon carbide 10 layers; and second gallium nitride layers disposed on the amorphous and/or polycrystalline silicon carbide layers.
A semiconductor structure according to claim 1, wherein the silicon carbide 15 layers comprise 3-step cubic silicon carbide.
A semiconductor structure according to claim 1, wherein the first gallium nitride layers comprise monocrystalline cubic gallium nitride.
20 4. A semiconductor structure according to claim 1, wherein the second gallium nitride layers comprise amorphous and/or polycrystalline gallium nitride.
A semiconductor structure according to claim 1, wherein the first gallium nitride layers are disposed directly on the monocrystalline silicon carbide layers, and the second gallium nitride layers are disposed directly on the amorphous and/or 30 polycrystalline silicon carbide layers.
A semiconductor structure according to claim 1, wherein the second gallium nitride layers are configured to reduce wafer stress and bow-causing forces.
0228-1-MHIQBAL M&C PC₉₂₇₀₅₉USB 15
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-SiC-on-Si composite semiconductor structure
Materials described outside the worked examples.
monocrystalline silicon wafer
Si
monocrystalline silicon carbide
SiC
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
silicon wafer initial bow | ≤ 25 um | Si |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,515,222Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a monocrystalline silicon wafer; 5 spaced apart monocrystalline silicon carbide layers disposed directly on the silicon wafer; amorphous and/or polycrystalline silicon carbide layers disposed directly on the silicon wafer between the monocrystalline silicon carbide layers; first gallium nitride layers disposed on the monocrystalline silicon carbide 10 layers; and second gallium nitride layers disposed on the amorphous and/or polycrystalline silicon carbide layers.
A semiconductor structure according to claim 1, wherein the silicon carbide 15 layers comprise 3-step cubic silicon carbide.
A semiconductor structure according to claim 1, wherein the first gallium nitride layers comprise monocrystalline cubic gallium nitride.
20 4. A semiconductor structure according to claim 1, wherein the second gallium nitride layers comprise amorphous and/or polycrystalline gallium nitride.
A semiconductor structure according to claim 1, wherein the first gallium nitride layers are disposed directly on the monocrystalline silicon carbide layers, and the second gallium nitride layers are disposed directly on the amorphous and/or 30 polycrystalline silicon carbide layers.
A semiconductor structure according to claim 1, wherein the second gallium nitride layers are configured to reduce wafer stress and bow-causing forces.
0228-1-MHIQBAL M&C PC₉₂₇₀₅₉USB 15
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-SiC-on-Si composite semiconductor structure
Materials described outside the worked examples.
monocrystalline silicon wafer
Si
monocrystalline silicon carbide
SiC
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
silicon wafer initial bow | ≤ 25 um | Si |
Thickness |
Related documents with shared materials, methods, properties, or citations.
first gallium nitride (monocrystalline cubic GaN)
GaN
silicon dioxide masking layer
SiO₂
| — |
Thickness | 50–200 nm | — |
Thickness | ≤ 1 mm | — |
first gallium nitride (monocrystalline cubic GaN)
GaN
silicon dioxide masking layer
SiO₂
| — |
Thickness | 50–200 nm | — |
Thickness | ≤ 1 mm | — |
first gallium nitride (monocrystalline cubic GaN)
GaN
silicon dioxide masking layer
SiO₂
| — |
Thickness | 50–200 nm | — |
Thickness | ≤ 1 mm | — |
first gallium nitride (monocrystalline cubic GaN)
GaN
silicon dioxide masking layer
SiO₂
| — |
Thickness | 50–200 nm | — |
Thickness | ≤ 1 mm | — |