Patent
US 8,785,261MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER
Sean King
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,785,261Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a side cross-sectional view of a silicon substrate. [0004]
FIG. 2 illustrates a side cross-sectional view of a silicon carbide buffer layer formed by chemical of a carbon-containing gas and the substrate of
FIG. 3 illustrates a side cross-sectional view of a silicon carbide buffer layer formed by implantation of carbon into the silicon substrate of
FIG. 4. As shown, the silicon carbide buffer layer 106 may be subsumed into the silicon carbide layer 114. The silicon carbide layer 114 may be formed by …
FIG. 5 illustrates a side cross-sectional view of doping impurities into the silicon carbide layer of
FIG. 6 illustrates a side cross-sectional view of a thin silicon carbide wafer to be attached to the silicon substrate to form the silicon carbide/silicon …
FIG. 7. The graphene layer 132 may be formed by either volatizing/sublimating silicon from the silicon carbide layer outer surface 118 or by reaction of the …
FIG. 8 illustrates a side cross-sectional view of a silicon carbide layer formed on the silicon carbide buffer layer, thereby forming a silicon carbide/silicon …
FIG. 9 illustrates a side cross-sectional view of annealing the structure of
FIG. 10 illustrates a side cross-sectional view of plasma treating the structure of
FIG. 11. As shown in
FIG. 12. [0016] FIG s. 14-17 illustrates a method of forming a graphene layer by decomposition of thermodynamically unstable carbide. [0017]
FIG. 13. This embodiment may allow for the formation of the graphene layer 132 at temperatures of about 200-400 ° C lower than methods previously described. …
FIG. 14, a substrate 202 may be provided. The substrate 202 may be a semiconductor such as silicon, germanium, diamond, gallium arsenide, indium phosphide, and …
FIG. 15, a thermodynamically unstable XC carbide layer 210 may be deposited on the formation substrate 204. In one embodiment, the XC carbide layer 210 may be …
FIG. 16. The decomposed XC carbide layer 212 may be further heated to a temperature of about 600 ° C where magnesium sublimates leaving behind carbon, which …
FIG. 17. In another embodiment, the X component may be discongruently volatized from the XC carbide layer 210 to leave behind only carbon (C) which forms the …
FIG. 18, a field effect transistor 300 maybe be formed on the graphene layer, which may be formed by any processes previously discussed. Numerous methods exist …
FIG. 19. As defined in block 410, a structural substrate, such as silicon, may be provided. A formation substrate, such as silicon carbide, may be formed on the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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A method of fabricating a transistor comprising: providing a structural substrate comprising silicon; forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide la yer; forming a graphene layer on the formation substrate comprising annealing the silicon carbide la y er in a g as selected from the grou p comprising g all ium gas, g ermanium gas, g ermane, and di g ermane to reduce and desorb surface oxides at temperatures of about 700-900 ° C and formin g the gra phene la yer b y silicon volatization at temperature of about 950 °C; forming a source region abutting the graphene layer; forming a drain region abutting the graphene layer; forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and forming a gate abutting the gate dielectric. currently amended
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The method of claim [[9]] 8, wherein forming the silicon carbide layer comprises reacting a carbon-containing gas with the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim [[9]] 8, wherein forming the silicon carbide layer comprises implanting carbon into the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer. SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822282.1.301.232.2247.298.svg 0.22 6.487 Graph Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER
The method of claim [[9]] 8, wherein forming the silicon carbide layer comprises bonding a silicon carbide wafer to the structural substrate.
The method of claim [[9]] 8, fu rther including doping an impurity into the silicon carbide layer.
The method of claim 13, wherein the impurity comprises iron or vanadium. 15.-20.
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A method of forming a transistor comprising: depositing a thermodynamically unstable XC carbide layer on a formation substrate com p risin g dep ositin g a mor p hous germanium carbide on a (000 1)6H-SiC substrate; decomposing the XC carbide layer into an X component and carbon; volatilizing the X component; forming a graphene layer from the carbon; forming a source region abutting the graphene layer; forming a drain region abutting the graphene layer; forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and forming a gate abutting the gate dielectric. currently amended
The m ethod of claim 21, A method of forming a transistor comprising: depositing a thermodynamically unstable XC carbide la y er on a formation substrate; decomposing the XC carbide la y er into an X component and carbon; volatilizing the X component; formin g a gra phene la y er from the carbon; forming a source region abuttin g the gra phene la ver; forming a drain region abutting the g raphene la ver; formin g a g ate dielectric abuttin g the gra phene la y er between the source region and the drain region, wherein the source region and the drain region abut the g ate dielectric; formin g a g ate abuttin g the g ate dielectric; and wherein depositing the XC carbide layer on a formation substrate comprises depositing amorphous tin carbide on a (0001) hexagonal boron nitride substrate.
Thc mcthcd cf claim 21, A method of forming a transistor comprising: depositing a thermodynamically unstable XC carbide la y er on a formation substrate; decomposing the XC carbide la y er into an X component and carbon; volatilizing the X component; formin g a gra phene la y er from the carbon; forming a source region abutting the g raphene la ver; forming a drain region abuttin g the gra phene la ver; formin g a g ate dielectric abuttin g the gra phene la y er between the source region and the drain region, wherein the source region and the drain region abut the g ate dielectric; forming a g ate abutting the g ate dielectric; and SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822284.1.301.232.2247.298.svg 0.22 6.487 Graph Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER wherein depositing the XC carbide layer on a formation substrate comprises depositing an epitaxial Geo.9 5Co.os layer on a (111) silicon carbide substrate.
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The method of claim [[23]] 21, wherein decomposing the XC carbide layer comprises heating under vacuum to a temperature of about 400 ° C, and wherein volatilizing the X component comprises sublimating germanium by heating to a temperature of about 980 °C. SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822283.1.301.232.2247.298.svg 0.22 6.487 Chemistry Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER
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The m ethod of claim 29, A method of forming a transistor comp ri sing: depositing a thermodynamically unstable XC carbide la y er on a formation substrate comprisin g de positin g mag nesium carbide on a (111) silicon carbide substrate; decomposing the XC carbide la y er into an X component and carbo n; volatilizing the X component; formin g a gra phene la y er from the carbo n; forming a source region abuttin g the gra phene la yer forming a drain region abutting the g raphene la yer formin g a g ate dielectric abuttin g the gra phene la y er between the source region and the drain region, wherein the source region and the drain region abut the g ate dielectric; formin g a g ate abuttin g the g ate dielectric; and wherein decomposing the XC eempenent- carbide la yer into an X component and carbon comprises heating the XC e empenent-carbide la yer to a temperature of about 400 ° C, wherein volatilizing the X component comprises heating to a temperature of about 600 ° C, and wherein forming the graphene layer comprises flash annealing at a temperature of about 850 °C.
A method of fabricating a transistor comprising: providing a structural substrate comprising silicon; forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide layer; SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822285.1.301.232.2247.298.svg 0.22 6.487 Graph Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER forming a graphene layer on the formation substrate, wherein forming the graphene layer comprises annealing the silicon carbide layer in a gas selected from the group comprising gallium gas, germanium gas, germane, and digermane at temperatures of about 700-900 ° C and forming the graphene layer by hydrocarbon chemical vapor deposition; forming a source region abutting the graphene layer; forming a drain region abutting the graphene layer; forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and forming a gate abutting the gate dielectric.
The method of claim 31, wherein forming the silicon carbide layer comprises reacting a carbon-containing gas with the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim 31, wherein forming the silicon carbide layer comprises implanting carbon into the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim 31, wherein forming the silicon carbide layer comprises bonding a silicon carbide wafer to the structural substrate.
The method of claim 31, further including doping an impurity into the silicon carbide layer.
A method of fabricating a transistor comprising: providing a structural substrate comprising silicon; forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide layer; SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822286.1.301.232.2247.298.svg 0.22 6.487 Graph Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER forming a graphene layer on the formation substrate, wherein forming the graphene layer comp ri ses: annealing the silicon carbide layer in a gas selected from the group comprising gallium gas, germanium gas, germane, and digermane at temperatures of about 700- 900 °C; treating with a hydrogen gas plasma at temperatures of about 1 00 -400 ° C to selectively remove surface silicon from a silicon carbide layer outer surface and produce a hydrogen terminated carbon rich surface; and annealing at temperatures of about 850 ° C or lower to desorb the hydrogen from the silicon carbide layer outer surface and form the graphene layer remaining carbon; forming a source region abutting the graphene layer; forming a drain region abutting the graphene layer; forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and forming a gate abutting the gate dielectric.
The method of claim 37, wherein forming the silicon carbide layer comprises reacting a carbon-containing gas with the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim 37, wherein forming the silicon carbide layer comprises implanting carbon into the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim 37, wherein forming the silicon carbide layer comprises bonding a silicon carbide wafer to the structural substrate.
The method of claim 37, further including doping an impurity into the silicon carbide layer. RESPONSE TO ADVISORY ACTION Page 8 Seri al Number: 12/888,979 Dkt: P₃₅₇₂₇ Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL
Layer stacks claimed or described, ordered top of device to substrate.
graphene channel field-effect transistor
Materials described outside the worked examples.
graphene
C
silicon carbide
SiC
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 18, a field effect transistor 300 maybe be formed on the graphene layer, which may be formed by any processes previously discussed. Numerous methods exist …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene on SiC channel mobility (description background) | 5000-10000 cm2/V·s | C |
silicon carrier mobility (description background comparison) | 70 cm2/V·s |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,785,261Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a side cross-sectional view of a silicon substrate. [0004]
FIG. 2 illustrates a side cross-sectional view of a silicon carbide buffer layer formed by chemical of a carbon-containing gas and the substrate of
FIG. 3 illustrates a side cross-sectional view of a silicon carbide buffer layer formed by implantation of carbon into the silicon substrate of
FIG. 4. As shown, the silicon carbide buffer layer 106 may be subsumed into the silicon carbide layer 114. The silicon carbide layer 114 may be formed by …
FIG. 5 illustrates a side cross-sectional view of doping impurities into the silicon carbide layer of
FIG. 6 illustrates a side cross-sectional view of a thin silicon carbide wafer to be attached to the silicon substrate to form the silicon carbide/silicon …
FIG. 7. The graphene layer 132 may be formed by either volatizing/sublimating silicon from the silicon carbide layer outer surface 118 or by reaction of the …
FIG. 8 illustrates a side cross-sectional view of a silicon carbide layer formed on the silicon carbide buffer layer, thereby forming a silicon carbide/silicon …
FIG. 9 illustrates a side cross-sectional view of annealing the structure of
FIG. 10 illustrates a side cross-sectional view of plasma treating the structure of
FIG. 11. As shown in
FIG. 12. [0016] FIG s. 14-17 illustrates a method of forming a graphene layer by decomposition of thermodynamically unstable carbide. [0017]
FIG. 13. This embodiment may allow for the formation of the graphene layer 132 at temperatures of about 200-400 ° C lower than methods previously described. …
FIG. 14, a substrate 202 may be provided. The substrate 202 may be a semiconductor such as silicon, germanium, diamond, gallium arsenide, indium phosphide, and …
FIG. 15, a thermodynamically unstable XC carbide layer 210 may be deposited on the formation substrate 204. In one embodiment, the XC carbide layer 210 may be …
FIG. 16. The decomposed XC carbide layer 212 may be further heated to a temperature of about 600 ° C where magnesium sublimates leaving behind carbon, which …
FIG. 17. In another embodiment, the X component may be discongruently volatized from the XC carbide layer 210 to leave behind only carbon (C) which forms the …
FIG. 18, a field effect transistor 300 maybe be formed on the graphene layer, which may be formed by any processes previously discussed. Numerous methods exist …
FIG. 19. As defined in block 410, a structural substrate, such as silicon, may be provided. A formation substrate, such as silicon carbide, may be formed on the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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A method of fabricating a transistor comprising: providing a structural substrate comprising silicon; forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide la yer; forming a graphene layer on the formation substrate comprising annealing the silicon carbide la y er in a g as selected from the grou p comprising g all ium gas, g ermanium gas, g ermane, and di g ermane to reduce and desorb surface oxides at temperatures of about 700-900 ° C and formin g the gra phene la yer b y silicon volatization at temperature of about 950 °C; forming a source region abutting the graphene layer; forming a drain region abutting the graphene layer; forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and forming a gate abutting the gate dielectric. currently amended
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The method of claim [[9]] 8, wherein forming the silicon carbide layer comprises reacting a carbon-containing gas with the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim [[9]] 8, wherein forming the silicon carbide layer comprises implanting carbon into the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer. SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822282.1.301.232.2247.298.svg 0.22 6.487 Graph Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER
The method of claim [[9]] 8, wherein forming the silicon carbide layer comprises bonding a silicon carbide wafer to the structural substrate.
The method of claim [[9]] 8, fu rther including doping an impurity into the silicon carbide layer.
The method of claim 13, wherein the impurity comprises iron or vanadium. 15.-20.
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A method of forming a transistor comprising: depositing a thermodynamically unstable XC carbide layer on a formation substrate com p risin g dep ositin g a mor p hous germanium carbide on a (000 1)6H-SiC substrate; decomposing the XC carbide layer into an X component and carbon; volatilizing the X component; forming a graphene layer from the carbon; forming a source region abutting the graphene layer; forming a drain region abutting the graphene layer; forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and forming a gate abutting the gate dielectric. currently amended
The m ethod of claim 21, A method of forming a transistor comprising: depositing a thermodynamically unstable XC carbide la y er on a formation substrate; decomposing the XC carbide la y er into an X component and carbon; volatilizing the X component; formin g a gra phene la y er from the carbon; forming a source region abuttin g the gra phene la ver; forming a drain region abutting the g raphene la ver; formin g a g ate dielectric abuttin g the gra phene la y er between the source region and the drain region, wherein the source region and the drain region abut the g ate dielectric; formin g a g ate abuttin g the g ate dielectric; and wherein depositing the XC carbide layer on a formation substrate comprises depositing amorphous tin carbide on a (0001) hexagonal boron nitride substrate.
Thc mcthcd cf claim 21, A method of forming a transistor comprising: depositing a thermodynamically unstable XC carbide la y er on a formation substrate; decomposing the XC carbide la y er into an X component and carbon; volatilizing the X component; formin g a gra phene la y er from the carbon; forming a source region abutting the g raphene la ver; forming a drain region abuttin g the gra phene la ver; formin g a g ate dielectric abuttin g the gra phene la y er between the source region and the drain region, wherein the source region and the drain region abut the g ate dielectric; forming a g ate abutting the g ate dielectric; and SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822284.1.301.232.2247.298.svg 0.22 6.487 Graph Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER wherein depositing the XC carbide layer on a formation substrate comprises depositing an epitaxial Geo.9 5Co.os layer on a (111) silicon carbide substrate.
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The method of claim [[23]] 21, wherein decomposing the XC carbide layer comprises heating under vacuum to a temperature of about 400 ° C, and wherein volatilizing the X component comprises sublimating germanium by heating to a temperature of about 980 °C. SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822283.1.301.232.2247.298.svg 0.22 6.487 Chemistry Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER
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The m ethod of claim 29, A method of forming a transistor comp ri sing: depositing a thermodynamically unstable XC carbide la y er on a formation substrate comprisin g de positin g mag nesium carbide on a (111) silicon carbide substrate; decomposing the XC carbide la y er into an X component and carbo n; volatilizing the X component; formin g a gra phene la y er from the carbo n; forming a source region abuttin g the gra phene la yer forming a drain region abutting the g raphene la yer formin g a g ate dielectric abuttin g the gra phene la y er between the source region and the drain region, wherein the source region and the drain region abut the g ate dielectric; formin g a g ate abuttin g the g ate dielectric; and wherein decomposing the XC eempenent- carbide la yer into an X component and carbon comprises heating the XC e empenent-carbide la yer to a temperature of about 400 ° C, wherein volatilizing the X component comprises heating to a temperature of about 600 ° C, and wherein forming the graphene layer comprises flash annealing at a temperature of about 850 °C.
A method of fabricating a transistor comprising: providing a structural substrate comprising silicon; forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide layer; SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822285.1.301.232.2247.298.svg 0.22 6.487 Graph Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER forming a graphene layer on the formation substrate, wherein forming the graphene layer comprises annealing the silicon carbide layer in a gas selected from the group comprising gallium gas, germanium gas, germane, and digermane at temperatures of about 700-900 ° C and forming the graphene layer by hydrocarbon chemical vapor deposition; forming a source region abutting the graphene layer; forming a drain region abutting the graphene layer; forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and forming a gate abutting the gate dielectric.
The method of claim 31, wherein forming the silicon carbide layer comprises reacting a carbon-containing gas with the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim 31, wherein forming the silicon carbide layer comprises implanting carbon into the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim 31, wherein forming the silicon carbide layer comprises bonding a silicon carbide wafer to the structural substrate.
The method of claim 31, further including doping an impurity into the silicon carbide layer.
A method of fabricating a transistor comprising: providing a structural substrate comprising silicon; forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide layer; SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822286.1.301.232.2247.298.svg 0.22 6.487 Graph Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER forming a graphene layer on the formation substrate, wherein forming the graphene layer comp ri ses: annealing the silicon carbide layer in a gas selected from the group comprising gallium gas, germanium gas, germane, and digermane at temperatures of about 700- 900 °C; treating with a hydrogen gas plasma at temperatures of about 1 00 -400 ° C to selectively remove surface silicon from a silicon carbide layer outer surface and produce a hydrogen terminated carbon rich surface; and annealing at temperatures of about 850 ° C or lower to desorb the hydrogen from the silicon carbide layer outer surface and form the graphene layer remaining carbon; forming a source region abutting the graphene layer; forming a drain region abutting the graphene layer; forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and forming a gate abutting the gate dielectric.
The method of claim 37, wherein forming the silicon carbide layer comprises reacting a carbon-containing gas with the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim 37, wherein forming the silicon carbide layer comprises implanting carbon into the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim 37, wherein forming the silicon carbide layer comprises bonding a silicon carbide wafer to the structural substrate.
The method of claim 37, further including doping an impurity into the silicon carbide layer. RESPONSE TO ADVISORY ACTION Page 8 Seri al Number: 12/888,979 Dkt: P₃₅₇₂₇ Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL
Layer stacks claimed or described, ordered top of device to substrate.
graphene channel field-effect transistor
Materials described outside the worked examples.
graphene
C
silicon carbide
SiC
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 18, a field effect transistor 300 maybe be formed on the graphene layer, which may be formed by any processes previously discussed. Numerous methods exist …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene on SiC channel mobility (description background) | 5000-10000 cm2/V·s | C |
silicon carrier mobility (description background comparison) | 70 cm2/V·s |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,785,261Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a side cross-sectional view of a silicon substrate. [0004]
FIG. 2 illustrates a side cross-sectional view of a silicon carbide buffer layer formed by chemical of a carbon-containing gas and the substrate of
FIG. 3 illustrates a side cross-sectional view of a silicon carbide buffer layer formed by implantation of carbon into the silicon substrate of
FIG. 4. As shown, the silicon carbide buffer layer 106 may be subsumed into the silicon carbide layer 114. The silicon carbide layer 114 may be formed by …
FIG. 5 illustrates a side cross-sectional view of doping impurities into the silicon carbide layer of
FIG. 6 illustrates a side cross-sectional view of a thin silicon carbide wafer to be attached to the silicon substrate to form the silicon carbide/silicon …
FIG. 7. The graphene layer 132 may be formed by either volatizing/sublimating silicon from the silicon carbide layer outer surface 118 or by reaction of the …
FIG. 8 illustrates a side cross-sectional view of a silicon carbide layer formed on the silicon carbide buffer layer, thereby forming a silicon carbide/silicon …
FIG. 9 illustrates a side cross-sectional view of annealing the structure of
FIG. 10 illustrates a side cross-sectional view of plasma treating the structure of
FIG. 11. As shown in
FIG. 12. [0016] FIG s. 14-17 illustrates a method of forming a graphene layer by decomposition of thermodynamically unstable carbide. [0017]
FIG. 13. This embodiment may allow for the formation of the graphene layer 132 at temperatures of about 200-400 ° C lower than methods previously described. …
FIG. 14, a substrate 202 may be provided. The substrate 202 may be a semiconductor such as silicon, germanium, diamond, gallium arsenide, indium phosphide, and …
FIG. 15, a thermodynamically unstable XC carbide layer 210 may be deposited on the formation substrate 204. In one embodiment, the XC carbide layer 210 may be …
FIG. 16. The decomposed XC carbide layer 212 may be further heated to a temperature of about 600 ° C where magnesium sublimates leaving behind carbon, which …
FIG. 17. In another embodiment, the X component may be discongruently volatized from the XC carbide layer 210 to leave behind only carbon (C) which forms the …
FIG. 18, a field effect transistor 300 maybe be formed on the graphene layer, which may be formed by any processes previously discussed. Numerous methods exist …
FIG. 19. As defined in block 410, a structural substrate, such as silicon, may be provided. A formation substrate, such as silicon carbide, may be formed on the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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A method of fabricating a transistor comprising: providing a structural substrate comprising silicon; forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide la yer; forming a graphene layer on the formation substrate comprising annealing the silicon carbide la y er in a g as selected from the grou p comprising g all ium gas, g ermanium gas, g ermane, and di g ermane to reduce and desorb surface oxides at temperatures of about 700-900 ° C and formin g the gra phene la yer b y silicon volatization at temperature of about 950 °C; forming a source region abutting the graphene layer; forming a drain region abutting the graphene layer; forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and forming a gate abutting the gate dielectric. currently amended
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The method of claim [[9]] 8, wherein forming the silicon carbide layer comprises reacting a carbon-containing gas with the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim [[9]] 8, wherein forming the silicon carbide layer comprises implanting carbon into the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer. SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822282.1.301.232.2247.298.svg 0.22 6.487 Graph Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER
The method of claim [[9]] 8, wherein forming the silicon carbide layer comprises bonding a silicon carbide wafer to the structural substrate.
The method of claim [[9]] 8, fu rther including doping an impurity into the silicon carbide layer.
The method of claim 13, wherein the impurity comprises iron or vanadium. 15.-20.
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A method of forming a transistor comprising: depositing a thermodynamically unstable XC carbide layer on a formation substrate com p risin g dep ositin g a mor p hous germanium carbide on a (000 1)6H-SiC substrate; decomposing the XC carbide layer into an X component and carbon; volatilizing the X component; forming a graphene layer from the carbon; forming a source region abutting the graphene layer; forming a drain region abutting the graphene layer; forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and forming a gate abutting the gate dielectric. currently amended
The m ethod of claim 21, A method of forming a transistor comprising: depositing a thermodynamically unstable XC carbide la y er on a formation substrate; decomposing the XC carbide la y er into an X component and carbon; volatilizing the X component; formin g a gra phene la y er from the carbon; forming a source region abuttin g the gra phene la ver; forming a drain region abutting the g raphene la ver; formin g a g ate dielectric abuttin g the gra phene la y er between the source region and the drain region, wherein the source region and the drain region abut the g ate dielectric; formin g a g ate abuttin g the g ate dielectric; and wherein depositing the XC carbide layer on a formation substrate comprises depositing amorphous tin carbide on a (0001) hexagonal boron nitride substrate.
Thc mcthcd cf claim 21, A method of forming a transistor comprising: depositing a thermodynamically unstable XC carbide la y er on a formation substrate; decomposing the XC carbide la y er into an X component and carbon; volatilizing the X component; formin g a gra phene la y er from the carbon; forming a source region abutting the g raphene la ver; forming a drain region abuttin g the gra phene la ver; formin g a g ate dielectric abuttin g the gra phene la y er between the source region and the drain region, wherein the source region and the drain region abut the g ate dielectric; forming a g ate abutting the g ate dielectric; and SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822284.1.301.232.2247.298.svg 0.22 6.487 Graph Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER wherein depositing the XC carbide layer on a formation substrate comprises depositing an epitaxial Geo.9 5Co.os layer on a (111) silicon carbide substrate.
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The method of claim [[23]] 21, wherein decomposing the XC carbide layer comprises heating under vacuum to a temperature of about 400 ° C, and wherein volatilizing the X component comprises sublimating germanium by heating to a temperature of about 980 °C. SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822283.1.301.232.2247.298.svg 0.22 6.487 Chemistry Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER
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The m ethod of claim 29, A method of forming a transistor comp ri sing: depositing a thermodynamically unstable XC carbide la y er on a formation substrate comprisin g de positin g mag nesium carbide on a (111) silicon carbide substrate; decomposing the XC carbide la y er into an X component and carbo n; volatilizing the X component; formin g a gra phene la y er from the carbo n; forming a source region abuttin g the gra phene la yer forming a drain region abutting the g raphene la yer formin g a g ate dielectric abuttin g the gra phene la y er between the source region and the drain region, wherein the source region and the drain region abut the g ate dielectric; formin g a g ate abuttin g the g ate dielectric; and wherein decomposing the XC eempenent- carbide la yer into an X component and carbon comprises heating the XC e empenent-carbide la yer to a temperature of about 400 ° C, wherein volatilizing the X component comprises heating to a temperature of about 600 ° C, and wherein forming the graphene layer comprises flash annealing at a temperature of about 850 °C.
A method of fabricating a transistor comprising: providing a structural substrate comprising silicon; forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide layer; SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822285.1.301.232.2247.298.svg 0.22 6.487 Graph Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER forming a graphene layer on the formation substrate, wherein forming the graphene layer comprises annealing the silicon carbide layer in a gas selected from the group comprising gallium gas, germanium gas, germane, and digermane at temperatures of about 700-900 ° C and forming the graphene layer by hydrocarbon chemical vapor deposition; forming a source region abutting the graphene layer; forming a drain region abutting the graphene layer; forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and forming a gate abutting the gate dielectric.
The method of claim 31, wherein forming the silicon carbide layer comprises reacting a carbon-containing gas with the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim 31, wherein forming the silicon carbide layer comprises implanting carbon into the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim 31, wherein forming the silicon carbide layer comprises bonding a silicon carbide wafer to the structural substrate.
The method of claim 31, further including doping an impurity into the silicon carbide layer.
A method of fabricating a transistor comprising: providing a structural substrate comprising silicon; forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide layer; SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822286.1.301.232.2247.298.svg 0.22 6.487 Graph Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER forming a graphene layer on the formation substrate, wherein forming the graphene layer comp ri ses: annealing the silicon carbide layer in a gas selected from the group comprising gallium gas, germanium gas, germane, and digermane at temperatures of about 700- 900 °C; treating with a hydrogen gas plasma at temperatures of about 1 00 -400 ° C to selectively remove surface silicon from a silicon carbide layer outer surface and produce a hydrogen terminated carbon rich surface; and annealing at temperatures of about 850 ° C or lower to desorb the hydrogen from the silicon carbide layer outer surface and form the graphene layer remaining carbon; forming a source region abutting the graphene layer; forming a drain region abutting the graphene layer; forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and forming a gate abutting the gate dielectric.
The method of claim 37, wherein forming the silicon carbide layer comprises reacting a carbon-containing gas with the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim 37, wherein forming the silicon carbide layer comprises implanting carbon into the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim 37, wherein forming the silicon carbide layer comprises bonding a silicon carbide wafer to the structural substrate.
The method of claim 37, further including doping an impurity into the silicon carbide layer. RESPONSE TO ADVISORY ACTION Page 8 Seri al Number: 12/888,979 Dkt: P₃₅₇₂₇ Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL
Layer stacks claimed or described, ordered top of device to substrate.
graphene channel field-effect transistor
Materials described outside the worked examples.
graphene
C
silicon carbide
SiC
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 18, a field effect transistor 300 maybe be formed on the graphene layer, which may be formed by any processes previously discussed. Numerous methods exist …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene on SiC channel mobility (description background) | 5000-10000 cm2/V·s | C |
silicon carrier mobility (description background comparison) | 70 cm2/V·s |
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Patent
Atlas literature
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US 8,785,261Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a side cross-sectional view of a silicon substrate. [0004]
FIG. 2 illustrates a side cross-sectional view of a silicon carbide buffer layer formed by chemical of a carbon-containing gas and the substrate of
FIG. 3 illustrates a side cross-sectional view of a silicon carbide buffer layer formed by implantation of carbon into the silicon substrate of
FIG. 4. As shown, the silicon carbide buffer layer 106 may be subsumed into the silicon carbide layer 114. The silicon carbide layer 114 may be formed by …
FIG. 5 illustrates a side cross-sectional view of doping impurities into the silicon carbide layer of
FIG. 6 illustrates a side cross-sectional view of a thin silicon carbide wafer to be attached to the silicon substrate to form the silicon carbide/silicon …
FIG. 7. The graphene layer 132 may be formed by either volatizing/sublimating silicon from the silicon carbide layer outer surface 118 or by reaction of the …
FIG. 8 illustrates a side cross-sectional view of a silicon carbide layer formed on the silicon carbide buffer layer, thereby forming a silicon carbide/silicon …
FIG. 9 illustrates a side cross-sectional view of annealing the structure of
FIG. 10 illustrates a side cross-sectional view of plasma treating the structure of
FIG. 11. As shown in
FIG. 12. [0016] FIG s. 14-17 illustrates a method of forming a graphene layer by decomposition of thermodynamically unstable carbide. [0017]
FIG. 13. This embodiment may allow for the formation of the graphene layer 132 at temperatures of about 200-400 ° C lower than methods previously described. …
FIG. 14, a substrate 202 may be provided. The substrate 202 may be a semiconductor such as silicon, germanium, diamond, gallium arsenide, indium phosphide, and …
FIG. 15, a thermodynamically unstable XC carbide layer 210 may be deposited on the formation substrate 204. In one embodiment, the XC carbide layer 210 may be …
FIG. 16. The decomposed XC carbide layer 212 may be further heated to a temperature of about 600 ° C where magnesium sublimates leaving behind carbon, which …
FIG. 17. In another embodiment, the X component may be discongruently volatized from the XC carbide layer 210 to leave behind only carbon (C) which forms the …
FIG. 18, a field effect transistor 300 maybe be formed on the graphene layer, which may be formed by any processes previously discussed. Numerous methods exist …
FIG. 19. As defined in block 410, a structural substrate, such as silicon, may be provided. A formation substrate, such as silicon carbide, may be formed on the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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A method of fabricating a transistor comprising: providing a structural substrate comprising silicon; forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide la yer; forming a graphene layer on the formation substrate comprising annealing the silicon carbide la y er in a g as selected from the grou p comprising g all ium gas, g ermanium gas, g ermane, and di g ermane to reduce and desorb surface oxides at temperatures of about 700-900 ° C and formin g the gra phene la yer b y silicon volatization at temperature of about 950 °C; forming a source region abutting the graphene layer; forming a drain region abutting the graphene layer; forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and forming a gate abutting the gate dielectric. currently amended
canceled
The method of claim [[9]] 8, wherein forming the silicon carbide layer comprises reacting a carbon-containing gas with the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim [[9]] 8, wherein forming the silicon carbide layer comprises implanting carbon into the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer. SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822282.1.301.232.2247.298.svg 0.22 6.487 Graph Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER
The method of claim [[9]] 8, wherein forming the silicon carbide layer comprises bonding a silicon carbide wafer to the structural substrate.
The method of claim [[9]] 8, fu rther including doping an impurity into the silicon carbide layer.
The method of claim 13, wherein the impurity comprises iron or vanadium. 15.-20.
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A method of forming a transistor comprising: depositing a thermodynamically unstable XC carbide layer on a formation substrate com p risin g dep ositin g a mor p hous germanium carbide on a (000 1)6H-SiC substrate; decomposing the XC carbide layer into an X component and carbon; volatilizing the X component; forming a graphene layer from the carbon; forming a source region abutting the graphene layer; forming a drain region abutting the graphene layer; forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and forming a gate abutting the gate dielectric. currently amended
The m ethod of claim 21, A method of forming a transistor comprising: depositing a thermodynamically unstable XC carbide la y er on a formation substrate; decomposing the XC carbide la y er into an X component and carbon; volatilizing the X component; formin g a gra phene la y er from the carbon; forming a source region abuttin g the gra phene la ver; forming a drain region abutting the g raphene la ver; formin g a g ate dielectric abuttin g the gra phene la y er between the source region and the drain region, wherein the source region and the drain region abut the g ate dielectric; formin g a g ate abuttin g the g ate dielectric; and wherein depositing the XC carbide layer on a formation substrate comprises depositing amorphous tin carbide on a (0001) hexagonal boron nitride substrate.
Thc mcthcd cf claim 21, A method of forming a transistor comprising: depositing a thermodynamically unstable XC carbide la y er on a formation substrate; decomposing the XC carbide la y er into an X component and carbon; volatilizing the X component; formin g a gra phene la y er from the carbon; forming a source region abutting the g raphene la ver; forming a drain region abuttin g the gra phene la ver; formin g a g ate dielectric abuttin g the gra phene la y er between the source region and the drain region, wherein the source region and the drain region abut the g ate dielectric; forming a g ate abutting the g ate dielectric; and SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822284.1.301.232.2247.298.svg 0.22 6.487 Graph Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER wherein depositing the XC carbide layer on a formation substrate comprises depositing an epitaxial Geo.9 5Co.os layer on a (111) silicon carbide substrate.
canceled
canceled
The method of claim [[23]] 21, wherein decomposing the XC carbide layer comprises heating under vacuum to a temperature of about 400 ° C, and wherein volatilizing the X component comprises sublimating germanium by heating to a temperature of about 980 °C. SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822283.1.301.232.2247.298.svg 0.22 6.487 Chemistry Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER
canceled
The m ethod of claim 29, A method of forming a transistor comp ri sing: depositing a thermodynamically unstable XC carbide la y er on a formation substrate comprisin g de positin g mag nesium carbide on a (111) silicon carbide substrate; decomposing the XC carbide la y er into an X component and carbo n; volatilizing the X component; formin g a gra phene la y er from the carbo n; forming a source region abuttin g the gra phene la yer forming a drain region abutting the g raphene la yer formin g a g ate dielectric abuttin g the gra phene la y er between the source region and the drain region, wherein the source region and the drain region abut the g ate dielectric; formin g a g ate abuttin g the g ate dielectric; and wherein decomposing the XC eempenent- carbide la yer into an X component and carbon comprises heating the XC e empenent-carbide la yer to a temperature of about 400 ° C, wherein volatilizing the X component comprises heating to a temperature of about 600 ° C, and wherein forming the graphene layer comprises flash annealing at a temperature of about 850 °C.
A method of fabricating a transistor comprising: providing a structural substrate comprising silicon; forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide layer; SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822285.1.301.232.2247.298.svg 0.22 6.487 Graph Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER forming a graphene layer on the formation substrate, wherein forming the graphene layer comprises annealing the silicon carbide layer in a gas selected from the group comprising gallium gas, germanium gas, germane, and digermane at temperatures of about 700-900 ° C and forming the graphene layer by hydrocarbon chemical vapor deposition; forming a source region abutting the graphene layer; forming a drain region abutting the graphene layer; forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and forming a gate abutting the gate dielectric.
The method of claim 31, wherein forming the silicon carbide layer comprises reacting a carbon-containing gas with the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim 31, wherein forming the silicon carbide layer comprises implanting carbon into the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim 31, wherein forming the silicon carbide layer comprises bonding a silicon carbide wafer to the structural substrate.
The method of claim 31, further including doping an impurity into the silicon carbide layer.
A method of fabricating a transistor comprising: providing a structural substrate comprising silicon; forming a formation substrate on the structural substrate, wherein the formation substrate comprises a silicon carbide layer; SVG 12888979.03-04-2014.HSDQEJQJPXXIFW3.CLM13822286.1.301.232.2247.298.svg 0.22 6.487 Graph Black and white Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER forming a graphene layer on the formation substrate, wherein forming the graphene layer comp ri ses: annealing the silicon carbide layer in a gas selected from the group comprising gallium gas, germanium gas, germane, and digermane at temperatures of about 700- 900 °C; treating with a hydrogen gas plasma at temperatures of about 1 00 -400 ° C to selectively remove surface silicon from a silicon carbide layer outer surface and produce a hydrogen terminated carbon rich surface; and annealing at temperatures of about 850 ° C or lower to desorb the hydrogen from the silicon carbide layer outer surface and form the graphene layer remaining carbon; forming a source region abutting the graphene layer; forming a drain region abutting the graphene layer; forming a gate dielectric abutting the graphene layer between the source region and the drain region, wherein the source region and the drain region abut the gate dielectric; and forming a gate abutting the gate dielectric.
The method of claim 37, wherein forming the silicon carbide layer comprises reacting a carbon-containing gas with the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim 37, wherein forming the silicon carbide layer comprises implanting carbon into the silicon substrate to form a silicon carbide buffer layer, and forming a silicon carbide layer on the silicon carbide buffer layer.
The method of claim 37, wherein forming the silicon carbide layer comprises bonding a silicon carbide wafer to the structural substrate.
The method of claim 37, further including doping an impurity into the silicon carbide layer. RESPONSE TO ADVISORY ACTION Page 8 Seri al Number: 12/888,979 Dkt: P₃₅₇₂₇ Fili ng Date: Title: MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL
Layer stacks claimed or described, ordered top of device to substrate.
graphene channel field-effect transistor
Materials described outside the worked examples.
graphene
C
silicon carbide
SiC
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 18, a field effect transistor 300 maybe be formed on the graphene layer, which may be formed by any processes previously discussed. Numerous methods exist …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene on SiC channel mobility (description background) | 5000-10000 cm2/V·s | C |
silicon carrier mobility (description background comparison) | 70 cm2/V·s |
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V
germanium
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GeC
amorphous tin carbide
SnC
hexagonal boron nitride substrate (0001)
h-BN
epitaxial Ge0.95C0.05
Ge0.95C0.05
magnesium carbide
MgC
Temperature | 750–1100 °C | — |
Thickness | 5000–10000 cm | — |
Temperature | 1000–1200 °C | — |
Temperature | 1250–1400 °C | — |
Temperature | 700–900 °C | — |
Temperature | 100–400 °C | — |
Temperature | 200–400 °C | — |
Temperature | 400–600 °C | — |
Temperature | ≥ 1300 °C | — |
Temperature | 0–400 °C | — |
silicon
Si
iron
Fe
vanadium
V
germanium
Ge
amorphous germanium carbide
GeC
amorphous tin carbide
SnC
hexagonal boron nitride substrate (0001)
h-BN
epitaxial Ge0.95C0.05
Ge0.95C0.05
magnesium carbide
MgC
Temperature | 750–1100 °C | — |
Thickness | 5000–10000 cm | — |
Temperature | 1000–1200 °C | — |
Temperature | 1250–1400 °C | — |
Temperature | 700–900 °C | — |
Temperature | 100–400 °C | — |
Temperature | 200–400 °C | — |
Temperature | 400–600 °C | — |
Temperature | ≥ 1300 °C | — |
Temperature | 0–400 °C | — |
silicon
Si
iron
Fe
vanadium
V
germanium
Ge
amorphous germanium carbide
GeC
amorphous tin carbide
SnC
hexagonal boron nitride substrate (0001)
h-BN
epitaxial Ge0.95C0.05
Ge0.95C0.05
magnesium carbide
MgC
Temperature | 750–1100 °C | — |
Thickness | 5000–10000 cm | — |
Temperature | 1000–1200 °C | — |
Temperature | 1250–1400 °C | — |
Temperature | 700–900 °C | — |
Temperature | 100–400 °C | — |
Temperature | 200–400 °C | — |
Temperature | 400–600 °C | — |
Temperature | ≥ 1300 °C | — |
Temperature | 0–400 °C | — |
silicon
Si
iron
Fe
vanadium
V
germanium
Ge
amorphous germanium carbide
GeC
amorphous tin carbide
SnC
hexagonal boron nitride substrate (0001)
h-BN
epitaxial Ge0.95C0.05
Ge0.95C0.05
magnesium carbide
MgC
Temperature | 750–1100 °C | — |
Thickness | 5000–10000 cm | — |
Temperature | 1000–1200 °C | — |
Temperature | 1250–1400 °C | — |
Temperature | 700–900 °C | — |
Temperature | 100–400 °C | — |
Temperature | 200–400 °C | — |
Temperature | 400–600 °C | — |
Temperature | ≥ 1300 °C | — |
Temperature | 0–400 °C | — |