A method of manufacturing a field effect transistor comprising: providing a silicon carbide substrate; forming at least one pair of sidewalls conducive to graphitization on said silicon carbide substrate; performing a solid state graphitization on exposed surfaces of said silicon carbide substrate including said at least one pair of sidewalls, wherein frmihg at least one graphene layer is formed on said silicon carbide substrate, said at least one graphene la y er contiguously extending, in order, t h rough a first horizontal graphene layer, a first vertical graphene layer, a second horizontal graphene la y er, a second vertical graphene layer, and a third horizontal graphene layer that is coplanar with said first horizontal graphene la y er, wherein said second horizontal graphene layer is vertically offset from said first and third graphene layers, and said first and second vertical graphene layers are formed by graphitization of said at least one pair of sidewalls; forming an ion implantation blocking structure over a portion of said at least one graphene layer; forming doped source and drain regions within said silicon carbide substrate; removing said ion implantation blocking structure; 3 1:\ IBM\ 11 26\20799A\AMEND\20799A.am2.doc forming a gate dielectric over said portion of said at least one graphene layer; and forming a gate electrode directly on said gate dielectric layer.

A method of manufacturing a field effect transistor comprising: 5 I:\J BM\ I 126\20799A\AMEND\20799A.a m 2.doc providing a silicon carbide substrate; forming at least one pair of sidewalls not conducive to graphitization on said silicon carbide substrate; performing solid state graphitization on exposed surfaces of said silicon carbide substrate including said at least one pair of sidewalls, wherein a contiguous carbon-containing layer is formed on said silicon carbide substrate, said contiguous carbon-containing layer contiguously extending, in order, through a first horizontal graphene layer, a first vertical carbon layer having a structural arrangement different from a graphene layer, a second horizontal graphene layer, a second vertical carbon layer having a structural arrangement different from a graphene layer, and a third horizontal graphene layer that is coplanar with said first horizontal graphene layer, wherein said second horizontal graphene layer is vertically offset from said first and third graphene layers, and said first and second vertical graphene layer are formed by graphitization of said at least one pair of sidewalls; forming an ion implantation blocking structure over a portion of said at least one graphene layer; forming doped source and drain regions within said silicon carbide substrate; removing said ion implantation blocking structure; forming a gate dielectric over said portion of said at least one graphene layer; and forming a gate electrode directly on said gate dielectric layer.

A method of manufacturing a field effect transistor comprising: providing a silicon carbide substrate; forming at least one pair of sidewalls conducive to graphitization on said silicon carbide substrate; performing a solid state graphitization on exposed surfaces of said silicon carbide substrate including said at least one pair of sidewalls, wherein frmihg at least one graphene layer is formed on said silicon carbide substrate, said at least one graphene la y er contiguously extending, in order, t h rough a first horizontal graphene layer, a first vertical graphene layer, a second horizontal graphene la y er, a second vertical graphene layer, and a third horizontal graphene layer that is coplanar with said first horizontal graphene la y er, wherein said second horizontal graphene layer is vertically offset from said first and third graphene layers, and said first and second vertical graphene layers are formed by graphitization of said at least one pair of sidewalls; forming an ion implantation blocking structure over a portion of said at least one graphene layer; forming doped source and drain regions within said silicon carbide substrate; removing said ion implantation blocking structure; 3 1:\ IBM\ 11 26\20799A\AMEND\20799A.am2.doc forming a gate dielectric over said portion of said at least one graphene layer; and forming a gate electrode directly on said gate dielectric layer.

A method of manufacturing a field effect transistor comprising: 5 I:\J BM\ I 126\20799A\AMEND\20799A.a m 2.doc providing a silicon carbide substrate; forming at least one pair of sidewalls not conducive to graphitization on said silicon carbide substrate; performing solid state graphitization on exposed surfaces of said silicon carbide substrate including said at least one pair of sidewalls, wherein a contiguous carbon-containing layer is formed on said silicon carbide substrate, said contiguous carbon-containing layer contiguously extending, in order, through a first horizontal graphene layer, a first vertical carbon layer having a structural arrangement different from a graphene layer, a second horizontal graphene layer, a second vertical carbon layer having a structural arrangement different from a graphene layer, and a third horizontal graphene layer that is coplanar with said first horizontal graphene layer, wherein said second horizontal graphene layer is vertically offset from said first and third graphene layers, and said first and second vertical graphene layer are formed by graphitization of said at least one pair of sidewalls; forming an ion implantation blocking structure over a portion of said at least one graphene layer; forming doped source and drain regions within said silicon carbide substrate; removing said ion implantation blocking structure; forming a gate dielectric over said portion of said at least one graphene layer; and forming a gate electrode directly on said gate dielectric layer.

A method of manufacturing a field effect transistor comprising: providing a silicon carbide substrate; forming at least one pair of sidewalls conducive to graphitization on said silicon carbide substrate; performing a solid state graphitization on exposed surfaces of said silicon carbide substrate including said at least one pair of sidewalls, wherein frmihg at least one graphene layer is formed on said silicon carbide substrate, said at least one graphene la y er contiguously extending, in order, t h rough a first horizontal graphene layer, a first vertical graphene layer, a second horizontal graphene la y er, a second vertical graphene layer, and a third horizontal graphene layer that is coplanar with said first horizontal graphene la y er, wherein said second horizontal graphene layer is vertically offset from said first and third graphene layers, and said first and second vertical graphene layers are formed by graphitization of said at least one pair of sidewalls; forming an ion implantation blocking structure over a portion of said at least one graphene layer; forming doped source and drain regions within said silicon carbide substrate; removing said ion implantation blocking structure; 3 1:\ IBM\ 11 26\20799A\AMEND\20799A.am2.doc forming a gate dielectric over said portion of said at least one graphene layer; and forming a gate electrode directly on said gate dielectric layer.

A method of manufacturing a field effect transistor comprising: 5 I:\J BM\ I 126\20799A\AMEND\20799A.a m 2.doc providing a silicon carbide substrate; forming at least one pair of sidewalls not conducive to graphitization on said silicon carbide substrate; performing solid state graphitization on exposed surfaces of said silicon carbide substrate including said at least one pair of sidewalls, wherein a contiguous carbon-containing layer is formed on said silicon carbide substrate, said contiguous carbon-containing layer contiguously extending, in order, through a first horizontal graphene layer, a first vertical carbon layer having a structural arrangement different from a graphene layer, a second horizontal graphene layer, a second vertical carbon layer having a structural arrangement different from a graphene layer, and a third horizontal graphene layer that is coplanar with said first horizontal graphene layer, wherein said second horizontal graphene layer is vertically offset from said first and third graphene layers, and said first and second vertical graphene layer are formed by graphitization of said at least one pair of sidewalls; forming an ion implantation blocking structure over a portion of said at least one graphene layer; forming doped source and drain regions within said silicon carbide substrate; removing said ion implantation blocking structure; forming a gate dielectric over said portion of said at least one graphene layer; and forming a gate electrode directly on said gate dielectric layer.

A method of manufacturing a field effect transistor comprising: providing a silicon carbide substrate; forming at least one pair of sidewalls conducive to graphitization on said silicon carbide substrate; performing a solid state graphitization on exposed surfaces of said silicon carbide substrate including said at least one pair of sidewalls, wherein frmihg at least one graphene layer is formed on said silicon carbide substrate, said at least one graphene la y er contiguously extending, in order, t h rough a first horizontal graphene layer, a first vertical graphene layer, a second horizontal graphene la y er, a second vertical graphene layer, and a third horizontal graphene layer that is coplanar with said first horizontal graphene la y er, wherein said second horizontal graphene layer is vertically offset from said first and third graphene layers, and said first and second vertical graphene layers are formed by graphitization of said at least one pair of sidewalls; forming an ion implantation blocking structure over a portion of said at least one graphene layer; forming doped source and drain regions within said silicon carbide substrate; removing said ion implantation blocking structure; 3 1:\ IBM\ 11 26\20799A\AMEND\20799A.am2.doc forming a gate dielectric over said portion of said at least one graphene layer; and forming a gate electrode directly on said gate dielectric layer.

A method of manufacturing a field effect transistor comprising: 5 I:\J BM\ I 126\20799A\AMEND\20799A.a m 2.doc providing a silicon carbide substrate; forming at least one pair of sidewalls not conducive to graphitization on said silicon carbide substrate; performing solid state graphitization on exposed surfaces of said silicon carbide substrate including said at least one pair of sidewalls, wherein a contiguous carbon-containing layer is formed on said silicon carbide substrate, said contiguous carbon-containing layer contiguously extending, in order, through a first horizontal graphene layer, a first vertical carbon layer having a structural arrangement different from a graphene layer, a second horizontal graphene layer, a second vertical carbon layer having a structural arrangement different from a graphene layer, and a third horizontal graphene layer that is coplanar with said first horizontal graphene layer, wherein said second horizontal graphene layer is vertically offset from said first and third graphene layers, and said first and second vertical graphene layer are formed by graphitization of said at least one pair of sidewalls; forming an ion implantation blocking structure over a portion of said at least one graphene layer; forming doped source and drain regions within said silicon carbide substrate; removing said ion implantation blocking structure; forming a gate dielectric over said portion of said at least one graphene layer; and forming a gate electrode directly on said gate dielectric layer.