Patent
US 8,853,749ION IMPLANTED AND SELF ALIGNED GATE STRUCTURE FOR GaN TRANSISTORS
Alexander Lidow, Jianjun Cao, Robert Beach, Robert Strittmatter et al.
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,853,749Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a cross-sectional view of a known enhancement mode GaN transistor device. [0013]
FIG. 2 illustrates a cross-sectional view of a transistor device formed according to a first embodiment of the present invention. [0014]
FIG. 3 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a first juncture of its formation. [0015]
FIG. 4 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a second juncture of its formation. [0016]
FIG. 5 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a third juncture of its formation. [0017]
FIG. 6 illustrates a cross-sectional view of a transistor device according to another embodiment described herein. [0018]
FIG. 7 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a fourth juncture. [0019]
FIG. 8 illustrates a cross-sectional view of a transistor device according to another embodiment described herein.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a substrate; transition material formed over the substrate; a buffer material formed over the transition material; a barrier material formed over the buffer material; a gate layer m ateial formed over the barrier material;, wherein the gate material ei prises a doped p or tion defining a gate region and an un doped p or tion outside of the gate regi o to redu ce curr ent leakage, whe r ein the doped p o rti o n defining the gate regi o n is d o ped wit impl an ed ions f fr m a grou csit ng of Mg, Fe, \T, Cr and C; a dielectric la y er with an opening formed over the gate l a yer; a gate metal formed in the opening of the dielectric layer, the gate metal being e vef-and eenpaeing-and- self-aligned with a _ [[, the]] gate region; and source and drain contacts, wherein the gate layer comprises a doped portion defining the gate region that is disposed under the opening of the dielectric la y er and an undoped portion outside of the gate region adapted to reduce current leakage, and wherein the doped portion defining the gate region is doped with implanted ions from a group consisting of Mg, Fe, V, Cr and C.
The transistor of claim 1, wherein the gate metal comprises one of T iN, Ta, TaN, Pd, W, WSi2, Ni and Au.
The transistor of claim 1, wherein the barrier material comprises AlGaN. original
The transistor of claim 1, wherein sides of the gate have an angle of about 90 degrees with respect to the gate layer- m ate ri al.
The transistor of claim 1, wherein sides of the gate are not perpendicular to the gate la yer-moateial.
The transistor of claim 1, wherein insulating material is formed on sides of the gate metal.
The transistor of claim 1, wherein the gate metal is TiN.
canceled
A method of forming a transistor with a self-aligned gate, the method comprising: forming transition layers on a substrate; forming a GaN buffer layer over the transition layers; forming a barrier layer over the GaN buffer layer; forming a gate layer over the barrier layer, wherein the gate layer is undoped; forming a dielectric layer over the gate layer; forming an opening through the dielectric layer to the gate layer to expose a portion of the gate layer; performing an ion implantation process containing p-type impurities th r ough the opening in the dielectric layer to form an ion implanted region of the gate layer, wherein the ion implanted region defines a gate region and a non-ion implanted region outside the gate region for reducing current leakage; 3 Application No. 13/362,669 Docket No.: E 0101.0018/P018 forming a gate metal material over the gate region using the opening through the dielectric layer to define a gate metal that is self-aligned with the gate region; and forming Ohmic drain and source contact regions.
: The method of claim 9, further comprising an activation process after the ion implantation process.
: The method of claim 9, wherein the ion implantation process implants ions selected from the group consisting of Mg, Fe, V, Cr and C.
: The method of claim 9, wherein the gate metal comprises one of T iN, Ta, TaN, Pd, W, WSi2, Ni and Au.
: The method of claim 9, wherein the barrier
: The method of claim 9, wherein sides of the respect to the gate layer.
: The method of claim 9, wherein sides of the
: The method of claim 9, wherein insulating form spacers to further reduce leakage current.
: The method of claim 9, wherein the gate metal layer comprises AlGaN. gate have an angle of about 90 degrees with gate are not perpendicular to the gate material. material is formed on sides of the gate metal to is TiN. 4
Layer stacks claimed or described, ordered top of device to substrate.
self-aligned gate GaN transistor (HEMT)
Materials described outside the worked examples.
GaN gate layer
GaN
AlGaN barrier layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates a cross-sectional view of a known enhancement mode GaN transistor device. [0013]
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,853,749Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a cross-sectional view of a known enhancement mode GaN transistor device. [0013]
FIG. 2 illustrates a cross-sectional view of a transistor device formed according to a first embodiment of the present invention. [0014]
FIG. 3 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a first juncture of its formation. [0015]
FIG. 4 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a second juncture of its formation. [0016]
FIG. 5 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a third juncture of its formation. [0017]
FIG. 6 illustrates a cross-sectional view of a transistor device according to another embodiment described herein. [0018]
FIG. 7 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a fourth juncture. [0019]
FIG. 8 illustrates a cross-sectional view of a transistor device according to another embodiment described herein.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a substrate; transition material formed over the substrate; a buffer material formed over the transition material; a barrier material formed over the buffer material; a gate layer m ateial formed over the barrier material;, wherein the gate material ei prises a doped p or tion defining a gate region and an un doped p or tion outside of the gate regi o to redu ce curr ent leakage, whe r ein the doped p o rti o n defining the gate regi o n is d o ped wit impl an ed ions f fr m a grou csit ng of Mg, Fe, \T, Cr and C; a dielectric la y er with an opening formed over the gate l a yer; a gate metal formed in the opening of the dielectric layer, the gate metal being e vef-and eenpaeing-and- self-aligned with a _ [[, the]] gate region; and source and drain contacts, wherein the gate layer comprises a doped portion defining the gate region that is disposed under the opening of the dielectric la y er and an undoped portion outside of the gate region adapted to reduce current leakage, and wherein the doped portion defining the gate region is doped with implanted ions from a group consisting of Mg, Fe, V, Cr and C.
The transistor of claim 1, wherein the gate metal comprises one of T iN, Ta, TaN, Pd, W, WSi2, Ni and Au.
The transistor of claim 1, wherein the barrier material comprises AlGaN. original
The transistor of claim 1, wherein sides of the gate have an angle of about 90 degrees with respect to the gate layer- m ate ri al.
The transistor of claim 1, wherein sides of the gate are not perpendicular to the gate la yer-moateial.
The transistor of claim 1, wherein insulating material is formed on sides of the gate metal.
The transistor of claim 1, wherein the gate metal is TiN.
canceled
A method of forming a transistor with a self-aligned gate, the method comprising: forming transition layers on a substrate; forming a GaN buffer layer over the transition layers; forming a barrier layer over the GaN buffer layer; forming a gate layer over the barrier layer, wherein the gate layer is undoped; forming a dielectric layer over the gate layer; forming an opening through the dielectric layer to the gate layer to expose a portion of the gate layer; performing an ion implantation process containing p-type impurities th r ough the opening in the dielectric layer to form an ion implanted region of the gate layer, wherein the ion implanted region defines a gate region and a non-ion implanted region outside the gate region for reducing current leakage; 3 Application No. 13/362,669 Docket No.: E 0101.0018/P018 forming a gate metal material over the gate region using the opening through the dielectric layer to define a gate metal that is self-aligned with the gate region; and forming Ohmic drain and source contact regions.
: The method of claim 9, further comprising an activation process after the ion implantation process.
: The method of claim 9, wherein the ion implantation process implants ions selected from the group consisting of Mg, Fe, V, Cr and C.
: The method of claim 9, wherein the gate metal comprises one of T iN, Ta, TaN, Pd, W, WSi2, Ni and Au.
: The method of claim 9, wherein the barrier
: The method of claim 9, wherein sides of the respect to the gate layer.
: The method of claim 9, wherein sides of the
: The method of claim 9, wherein insulating form spacers to further reduce leakage current.
: The method of claim 9, wherein the gate metal layer comprises AlGaN. gate have an angle of about 90 degrees with gate are not perpendicular to the gate material. material is formed on sides of the gate metal to is TiN. 4
Layer stacks claimed or described, ordered top of device to substrate.
self-aligned gate GaN transistor (HEMT)
Materials described outside the worked examples.
GaN gate layer
GaN
AlGaN barrier layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates a cross-sectional view of a known enhancement mode GaN transistor device. [0013]
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,853,749Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a cross-sectional view of a known enhancement mode GaN transistor device. [0013]
FIG. 2 illustrates a cross-sectional view of a transistor device formed according to a first embodiment of the present invention. [0014]
FIG. 3 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a first juncture of its formation. [0015]
FIG. 4 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a second juncture of its formation. [0016]
FIG. 5 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a third juncture of its formation. [0017]
FIG. 6 illustrates a cross-sectional view of a transistor device according to another embodiment described herein. [0018]
FIG. 7 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a fourth juncture. [0019]
FIG. 8 illustrates a cross-sectional view of a transistor device according to another embodiment described herein.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a substrate; transition material formed over the substrate; a buffer material formed over the transition material; a barrier material formed over the buffer material; a gate layer m ateial formed over the barrier material;, wherein the gate material ei prises a doped p or tion defining a gate region and an un doped p or tion outside of the gate regi o to redu ce curr ent leakage, whe r ein the doped p o rti o n defining the gate regi o n is d o ped wit impl an ed ions f fr m a grou csit ng of Mg, Fe, \T, Cr and C; a dielectric la y er with an opening formed over the gate l a yer; a gate metal formed in the opening of the dielectric layer, the gate metal being e vef-and eenpaeing-and- self-aligned with a _ [[, the]] gate region; and source and drain contacts, wherein the gate layer comprises a doped portion defining the gate region that is disposed under the opening of the dielectric la y er and an undoped portion outside of the gate region adapted to reduce current leakage, and wherein the doped portion defining the gate region is doped with implanted ions from a group consisting of Mg, Fe, V, Cr and C.
The transistor of claim 1, wherein the gate metal comprises one of T iN, Ta, TaN, Pd, W, WSi2, Ni and Au.
The transistor of claim 1, wherein the barrier material comprises AlGaN. original
The transistor of claim 1, wherein sides of the gate have an angle of about 90 degrees with respect to the gate layer- m ate ri al.
The transistor of claim 1, wherein sides of the gate are not perpendicular to the gate la yer-moateial.
The transistor of claim 1, wherein insulating material is formed on sides of the gate metal.
The transistor of claim 1, wherein the gate metal is TiN.
canceled
A method of forming a transistor with a self-aligned gate, the method comprising: forming transition layers on a substrate; forming a GaN buffer layer over the transition layers; forming a barrier layer over the GaN buffer layer; forming a gate layer over the barrier layer, wherein the gate layer is undoped; forming a dielectric layer over the gate layer; forming an opening through the dielectric layer to the gate layer to expose a portion of the gate layer; performing an ion implantation process containing p-type impurities th r ough the opening in the dielectric layer to form an ion implanted region of the gate layer, wherein the ion implanted region defines a gate region and a non-ion implanted region outside the gate region for reducing current leakage; 3 Application No. 13/362,669 Docket No.: E 0101.0018/P018 forming a gate metal material over the gate region using the opening through the dielectric layer to define a gate metal that is self-aligned with the gate region; and forming Ohmic drain and source contact regions.
: The method of claim 9, further comprising an activation process after the ion implantation process.
: The method of claim 9, wherein the ion implantation process implants ions selected from the group consisting of Mg, Fe, V, Cr and C.
: The method of claim 9, wherein the gate metal comprises one of T iN, Ta, TaN, Pd, W, WSi2, Ni and Au.
: The method of claim 9, wherein the barrier
: The method of claim 9, wherein sides of the respect to the gate layer.
: The method of claim 9, wherein sides of the
: The method of claim 9, wherein insulating form spacers to further reduce leakage current.
: The method of claim 9, wherein the gate metal layer comprises AlGaN. gate have an angle of about 90 degrees with gate are not perpendicular to the gate material. material is formed on sides of the gate metal to is TiN. 4
Layer stacks claimed or described, ordered top of device to substrate.
self-aligned gate GaN transistor (HEMT)
Materials described outside the worked examples.
GaN gate layer
GaN
AlGaN barrier layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates a cross-sectional view of a known enhancement mode GaN transistor device. [0013]
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,853,749Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a cross-sectional view of a known enhancement mode GaN transistor device. [0013]
FIG. 2 illustrates a cross-sectional view of a transistor device formed according to a first embodiment of the present invention. [0014]
FIG. 3 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a first juncture of its formation. [0015]
FIG. 4 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a second juncture of its formation. [0016]
FIG. 5 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a third juncture of its formation. [0017]
FIG. 6 illustrates a cross-sectional view of a transistor device according to another embodiment described herein. [0018]
FIG. 7 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a fourth juncture. [0019]
FIG. 8 illustrates a cross-sectional view of a transistor device according to another embodiment described herein.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a substrate; transition material formed over the substrate; a buffer material formed over the transition material; a barrier material formed over the buffer material; a gate layer m ateial formed over the barrier material;, wherein the gate material ei prises a doped p or tion defining a gate region and an un doped p or tion outside of the gate regi o to redu ce curr ent leakage, whe r ein the doped p o rti o n defining the gate regi o n is d o ped wit impl an ed ions f fr m a grou csit ng of Mg, Fe, \T, Cr and C; a dielectric la y er with an opening formed over the gate l a yer; a gate metal formed in the opening of the dielectric layer, the gate metal being e vef-and eenpaeing-and- self-aligned with a _ [[, the]] gate region; and source and drain contacts, wherein the gate layer comprises a doped portion defining the gate region that is disposed under the opening of the dielectric la y er and an undoped portion outside of the gate region adapted to reduce current leakage, and wherein the doped portion defining the gate region is doped with implanted ions from a group consisting of Mg, Fe, V, Cr and C.
The transistor of claim 1, wherein the gate metal comprises one of T iN, Ta, TaN, Pd, W, WSi2, Ni and Au.
The transistor of claim 1, wherein the barrier material comprises AlGaN. original
The transistor of claim 1, wherein sides of the gate have an angle of about 90 degrees with respect to the gate layer- m ate ri al.
The transistor of claim 1, wherein sides of the gate are not perpendicular to the gate la yer-moateial.
The transistor of claim 1, wherein insulating material is formed on sides of the gate metal.
The transistor of claim 1, wherein the gate metal is TiN.
canceled
A method of forming a transistor with a self-aligned gate, the method comprising: forming transition layers on a substrate; forming a GaN buffer layer over the transition layers; forming a barrier layer over the GaN buffer layer; forming a gate layer over the barrier layer, wherein the gate layer is undoped; forming a dielectric layer over the gate layer; forming an opening through the dielectric layer to the gate layer to expose a portion of the gate layer; performing an ion implantation process containing p-type impurities th r ough the opening in the dielectric layer to form an ion implanted region of the gate layer, wherein the ion implanted region defines a gate region and a non-ion implanted region outside the gate region for reducing current leakage; 3 Application No. 13/362,669 Docket No.: E 0101.0018/P018 forming a gate metal material over the gate region using the opening through the dielectric layer to define a gate metal that is self-aligned with the gate region; and forming Ohmic drain and source contact regions.
: The method of claim 9, further comprising an activation process after the ion implantation process.
: The method of claim 9, wherein the ion implantation process implants ions selected from the group consisting of Mg, Fe, V, Cr and C.
: The method of claim 9, wherein the gate metal comprises one of T iN, Ta, TaN, Pd, W, WSi2, Ni and Au.
: The method of claim 9, wherein the barrier
: The method of claim 9, wherein sides of the respect to the gate layer.
: The method of claim 9, wherein sides of the
: The method of claim 9, wherein insulating form spacers to further reduce leakage current.
: The method of claim 9, wherein the gate metal layer comprises AlGaN. gate have an angle of about 90 degrees with gate are not perpendicular to the gate material. material is formed on sides of the gate metal to is TiN. 4
Layer stacks claimed or described, ordered top of device to substrate.
self-aligned gate GaN transistor (HEMT)
Materials described outside the worked examples.
GaN gate layer
GaN
AlGaN barrier layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates a cross-sectional view of a known enhancement mode GaN transistor device. [0013]
Related documents with shared materials, methods, properties, or citations.
transition material
ion implant dopants (Mg, Fe, V, Cr, C)
gate metal (TiN, Ta, TaN, Pd, W, WSi2, Ni, Au)
TiN gate metal
TiN
silicon nitride dielectric
Si₃N₄
AlN/AlGaN transition layers
FIG. 2 illustrates a cross-sectional view of a transistor device formed according to a first embodiment of the present invention. [0014]
FIG. 3 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a first juncture of its formation. [0015]
FIG. 4 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a second juncture of its formation. [0016]
FIG. 5 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a third juncture of its formation. [0017]
FIG. 6 illustrates a cross-sectional view of a transistor device according to another embodiment described herein. [0018]
FIG. 7 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a fourth juncture. [0019]
FIG. 8 illustrates a cross-sectional view of a transistor device according to another embodiment described herein.
transition material
ion implant dopants (Mg, Fe, V, Cr, C)
gate metal (TiN, Ta, TaN, Pd, W, WSi2, Ni, Au)
TiN gate metal
TiN
silicon nitride dielectric
Si₃N₄
AlN/AlGaN transition layers
FIG. 2 illustrates a cross-sectional view of a transistor device formed according to a first embodiment of the present invention. [0014]
FIG. 3 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a first juncture of its formation. [0015]
FIG. 4 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a second juncture of its formation. [0016]
FIG. 5 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a third juncture of its formation. [0017]
FIG. 6 illustrates a cross-sectional view of a transistor device according to another embodiment described herein. [0018]
FIG. 7 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a fourth juncture. [0019]
FIG. 8 illustrates a cross-sectional view of a transistor device according to another embodiment described herein.
transition material
ion implant dopants (Mg, Fe, V, Cr, C)
gate metal (TiN, Ta, TaN, Pd, W, WSi2, Ni, Au)
TiN gate metal
TiN
silicon nitride dielectric
Si₃N₄
AlN/AlGaN transition layers
FIG. 2 illustrates a cross-sectional view of a transistor device formed according to a first embodiment of the present invention. [0014]
FIG. 3 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a first juncture of its formation. [0015]
FIG. 4 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a second juncture of its formation. [0016]
FIG. 5 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a third juncture of its formation. [0017]
FIG. 6 illustrates a cross-sectional view of a transistor device according to another embodiment described herein. [0018]
FIG. 7 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a fourth juncture. [0019]
FIG. 8 illustrates a cross-sectional view of a transistor device according to another embodiment described herein.
transition material
ion implant dopants (Mg, Fe, V, Cr, C)
gate metal (TiN, Ta, TaN, Pd, W, WSi2, Ni, Au)
TiN gate metal
TiN
silicon nitride dielectric
Si₃N₄
AlN/AlGaN transition layers
FIG. 2 illustrates a cross-sectional view of a transistor device formed according to a first embodiment of the present invention. [0014]
FIG. 3 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a first juncture of its formation. [0015]
FIG. 4 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a second juncture of its formation. [0016]
FIG. 5 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a third juncture of its formation. [0017]
FIG. 6 illustrates a cross-sectional view of a transistor device according to another embodiment described herein. [0018]
FIG. 7 illustrates a cross-sectional view of a transistor device according to embodiments described herein at a fourth juncture. [0019]
FIG. 8 illustrates a cross-sectional view of a transistor device according to another embodiment described herein.