Patent
US 9,508,797GALLIUM NITRIDE POWER DEVICES USING ISLAND TOPOGRAPHY
John ROBERTS
US
Copyright © 2026 Matter42. All rights reserved.
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US 9,508,797Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a plan view of a nitride semiconductor transistor having an island 26 topography using square island electrodes. 27 1 0011 1
FIG. 2 is a plan view on an enlarged scale of a portion of the device shown in
FIG. 3 is a cross-section view along the line I II-III of
FIG. 4 is view on an enlarged scale on the line IV-IV of FIG 1 3 [0014]
FIG. 5 is a cross-section view along the line V-V of F I G. 2 4 [0015]
FIG. 6 is a cross-section view along the line VI-VI of
FIGS. 7A to 7C are graphs of gate width versus square island electrode length at a 6 fixed source to drain spacing. 7 [0017]
FIG. 8 is a plan view of a nitride semiconductor transistor having an island 8 topography layout using square island electrodes aligned orthogonally. 9 [0018]
FIG. 9 is a plan view of a nitride semiconductor transistor having an island 10 topography layout using square island electrodes aligned diagonally. 11 [0019]
FIG. 10 is a plan view of a nitride semiconductor transistor having an island 12 topography layout using triangle island electrodes. 13 [0020]
FIG. 11 is a cross-section view of a packaging of the nitride semiconductor transistor 14 using the island topography. 15 [0021]
FIG. 12 is a plan view of a nitride semiconductor transistor having a square island 16 topography with island clusters. 17 [0022]
FIG. 13 is a cross-section view along the line XIII-XIII of
FIG. 14 is a cross-section view along the line XIV-XIV of
FIG. 15 is a plan view showing the source and drain clusters of the nitride 20 semiconductor transistor of
FIG. 16 is a plan view showing the gate clusters of the nitride semiconductor 22 transistor of
FIG. 17 is an expanded plan view of a portion of
FIG. 18 is a plan view of a nitride semiconductor diode having a square island 25 topography with island clusters. 22072614.4 -4- 1 [0028]
FIG. 19 is a cross-section view along the line XIX-XIX of
FIG. 20 is a plan view of a nitride semiconductor diode having a triangle island 3 topography with island clusters. 4 [0030]
FIG. 21 is a plan view of a nitride semiconductor transistor having a castellated island 5 topography. 6 [0031]
FIG. 22 is a plan view of a nitride semiconductor transistor having another 7 embodiment of the castellated island topography. 8 [0032]
FIG. 23 is a plan view of a nitride semiconductor transistor having a concentric island 9 topography. 10 [0033]
FIG. 24 is a plan view of a larger portion of the nitride semiconductor transistor of 11
FIG. 25 is a cross-section view of a nitride semiconductor transistor having a 13 concentric island topography. 14 [0035]
FIG. 26 is a plan view of a nitride semiconductor transistor having a concentric island 15 topography using hexagon electrode tracks and triangle island metal …
FIG. 27 is a plan view of a nitride semiconductor diode having another embodiment 17 of a concentric island topography 18 [0037]
FIG. 28 is a plan view of a nitride semiconductor diode having yet another 19 embodiment of a concentric island topography. 20 [0038]
FIG. 29 is a schematic diagram of a half-bridge circuit. 21 [0039]
FIG. 30 is a plan view of half-islands arranged in rows. 22 [0040]
FIG. 31 is a plan view of half-islands implementing a half-bridge or full-bridge circuit 23 and the corresponding schematic diagram. 24 [0041]
FIG. 32 is another schematic diagram of the full-bridge circuit of
FIG. 33 is a cross-section view of half-islands arranged in a row. 26 [0043]
FIG. 34 is a schematic diagram of a clamped full-bridge rectifier power circuit. 22072614.4 -5- 1 [0044]
FIG. 35 is a plan view of half-islands with interconnections implementing the circuit 2 of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-34. (Previously cancelled) canceled
A nitride semiconductor device comprising: a substrate; a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; a plurality of source island electrodes and a plurality of drain island electrodes of a multi-island transistor formed on the nitride semiconductor layer, the source island electrodes and drain island electrodes being spaced apart from each other and arranged as an array with alternating source island electrodes and drain island electrodes along at least two different axial directions to produce two-dimensional active regions in a device area of the nitride semiconductor layer; a plurality of gate strip electrodes formed on the nitride semiconductor layer in active regions between adjacent source island electrodes and drain island electrodes, an overlying low resistance gate interconnect running between the source island electrodes and drain island electrodes, the plurality of gate electrodes being interconnected to the low resistance gate interconnect by gate interconnections at interstices defined by adjacent vertices of the source island electrodes and the drain island electrodes; each of the plurality of source island electrodes having a respective individual source contact area (pad) comprising a bump, ball or post connection formed thereon; each of the plurality of drain island electrodes having a respective individual drain contact area (pad) comprising a bump, ball or post connection formed thereon; the low resistance gate interconnect being connected to a plurality of gate pads; and wherein, in defective active regions, individual gate strip electrodes are selectively disconnected from the gate interconnect by absence or removal of respective gate interconnections thereto.
The nitride semiconductor device of claim 35, wherein in defective active regions, individual drain island electrodes are isolated by absence or removal of the bump, ball or post connection thereon.
The device according to The nitride semiconductor device of claim 35, wherein each of the plurality of source island electrodes comprises a plurality of castellated peninsulas extending from at least one side, which are interleaved with a plurality of castellated peninsulas extending from a side of an adjacent one of the plurality of drain island electrodes.
The device according to The nitride semiconductor device of claim 35, wherein the first and second island electrodes: a) have a predominantly rectangular shape; or b) have a predominantly triangular shape; and or c) have a polygon shape that can be arranged as said array of alternating source and drain island electrodes to optimize active area usage.
The device of claim 35 The nitride semiconductor device of claim 35, wherein the nitride semiconductor layer comprises hetero-layer of a layer of undoped gallium nitride (GaN) beneath a layer of undoped aluminum gallium nitride (AIGaN).
canceled
The device of claim 41 A nitride semiconductor device comprising: a substrate; a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; a metallization layer formed on the nitride semiconductor layer defining a plurality of first island electrodes and a plurality of second island electrodes spaced apart from each other and arranged as an array with alternating first island electrodes and second island electrodes along at least two orthogonal directions to produce two-dimensional active regions in a device area of the nitride semiconductor layer, with at least one side of each first island electrode opposite a side of an adjacent second island electrode; at least one side of each second island electrode opposite a side of an adjacent first island electrode; an overlying interconnect structure comprising one or more metallization layers and intervening insulating layers; the one or more metallization layers of the overlying interconnect structure defining a plurality of first common electrodes and a plurality of second common electrodes, the first common electrodes and the second common electrodes being arranged as a second array with alternating first common electrodes and second common electrodes, the second array of first and second common electrodes overlying the array of the first and second island electrodes; each first common electrode being interconnected to a set of said first island electrodes by said one or more metallization layers and conductive vias; and each second common electrode being interconnected to a set of said second island electrodes by said one or more metallization layers and conductive vias; each of the first common electrodes providing an external first connection formed thereon comprising a ball, bump or post connection, and each of the second common electrodes comprises an external first connection formed thereon comprising a ball, bump or post connection; the first island electrodes and second island electrodes serving, respectively, as source island electrodes and drain island electrodes of a multi-island transistor; and a plurality of gate strip electrodes of the multi-island transistor formed on the nitride semiconductor layer in active regions between adjacent first island electrodes and second island electrodes; a low resistance gate interconnect running between the source island electrodes and drain island electrodes overlying the gate strip electrodes, the plurality of gate strip electrodes being interconnected to the low resistance gate interconnect by gate interconnections at interstices defined by adjacent vertices of the first island electrodes and second island electrodes; one or more gate common electrodes comprising an external gate connection formed thereon comprising a ball, bump or post connection; and the gate strap connecting the interconnected gate strip electrodes to the one or more gate common electrodes; and wherein, in defective active regions, individual gate electrodes are selectively disconnected from the gate interconnect by absence or removal of respective gate interconnections thereto.
The nitride semiconductor device of claim 41 claim 43, wherein in said defective active regions, individual drain common electrodes are isolated by absence or removal of the bump, ball or post connection thereon.
The nitride semiconductor device according to claim 41 of claim 43, wherein the first and second island electrodes: a) have a predominantly rectangular shape; or b) have a predominantly triangular shape; and or c) have a polygon shape that can be arranged as said array of alternating source and drain island electrodes to optimize active area usage.
The nitride semiconductor device of claim 41 claim 43 wherein the nitride semiconductor layer comprises hetero-layer of a layer of undoped gallium nitride (GaN) beneath a layer of undoped aluminum gallium nitride (AIGaN).
canceled
A nitride semiconductor device comprising: a substrate; a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; a plurality of source, drain and gate electrodes of a multi-island transistor formed on the nitride semiconductor layer, the plurality of source, drain and gate electrodes comprising concentric electrode islands of decreasing size and arranged as repeated square shaped concentric tracks of ohmic and Schottky contacts, every two ohmic contacts having a Schottky contact in between, a plurality of source concentric island electrodes and a plurality of drain concentric island electrodes being formed from said ohmic concentric tracks, the gate electrodes in between the source and drain concentric electrodes being formed from said Schottky concentric tracks, the source and drain concentric electrodes thereby being alternately arranged such that each source island electrode is adjacent to a drain island electrode with a gate electrode in between; an overlying dielectric isolation layer with an array of a plurality of overlying square shaped source metal pads and drain metal pads formed thereon, the source and drain metal pads being arranged alternately with each source metal pad adjacent a drain metal pad, the corners of each adjacent four metal pads being placed over a set of square shaped concentric tracks of source and drain concentric island electrodes; source concentric island electrodes being connected to a respective overlying source metal pad by conductive via s; drain concentric island electrodes being connected to a respective overlying drain metal pad by conductive via s; and a gate connection point located at the center of each set of concentric tracks and in spaces defined between adjacent corners of the source and drain metal pads.
The device of claim 48 wherein the Schottky gate electrodes are connected to an overlying low resistance interconnect metal strap by gate interconnections to said gate connection points.
The device of claim 48 wherein, in defective regions, Schottky gate electrodes are selectively disconnected from the gate strap by absence or removal of said gate interconnections.
Layer stacks claimed or described, ordered top of device to substrate.
nitride semiconductor multi-island transistor (claim 35)
Materials described outside the worked examples.
nitride semiconductor
undoped gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a plan view of a nitride semiconductor transistor having an island 26 topography using square island electrodes. 27 1 0011 1
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 600–1700 V | — |
Thickness | 3–20 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,508,797Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a plan view of a nitride semiconductor transistor having an island 26 topography using square island electrodes. 27 1 0011 1
FIG. 2 is a plan view on an enlarged scale of a portion of the device shown in
FIG. 3 is a cross-section view along the line I II-III of
FIG. 4 is view on an enlarged scale on the line IV-IV of FIG 1 3 [0014]
FIG. 5 is a cross-section view along the line V-V of F I G. 2 4 [0015]
FIG. 6 is a cross-section view along the line VI-VI of
FIGS. 7A to 7C are graphs of gate width versus square island electrode length at a 6 fixed source to drain spacing. 7 [0017]
FIG. 8 is a plan view of a nitride semiconductor transistor having an island 8 topography layout using square island electrodes aligned orthogonally. 9 [0018]
FIG. 9 is a plan view of a nitride semiconductor transistor having an island 10 topography layout using square island electrodes aligned diagonally. 11 [0019]
FIG. 10 is a plan view of a nitride semiconductor transistor having an island 12 topography layout using triangle island electrodes. 13 [0020]
FIG. 11 is a cross-section view of a packaging of the nitride semiconductor transistor 14 using the island topography. 15 [0021]
FIG. 12 is a plan view of a nitride semiconductor transistor having a square island 16 topography with island clusters. 17 [0022]
FIG. 13 is a cross-section view along the line XIII-XIII of
FIG. 14 is a cross-section view along the line XIV-XIV of
FIG. 15 is a plan view showing the source and drain clusters of the nitride 20 semiconductor transistor of
FIG. 16 is a plan view showing the gate clusters of the nitride semiconductor 22 transistor of
FIG. 17 is an expanded plan view of a portion of
FIG. 18 is a plan view of a nitride semiconductor diode having a square island 25 topography with island clusters. 22072614.4 -4- 1 [0028]
FIG. 19 is a cross-section view along the line XIX-XIX of
FIG. 20 is a plan view of a nitride semiconductor diode having a triangle island 3 topography with island clusters. 4 [0030]
FIG. 21 is a plan view of a nitride semiconductor transistor having a castellated island 5 topography. 6 [0031]
FIG. 22 is a plan view of a nitride semiconductor transistor having another 7 embodiment of the castellated island topography. 8 [0032]
FIG. 23 is a plan view of a nitride semiconductor transistor having a concentric island 9 topography. 10 [0033]
FIG. 24 is a plan view of a larger portion of the nitride semiconductor transistor of 11
FIG. 25 is a cross-section view of a nitride semiconductor transistor having a 13 concentric island topography. 14 [0035]
FIG. 26 is a plan view of a nitride semiconductor transistor having a concentric island 15 topography using hexagon electrode tracks and triangle island metal …
FIG. 27 is a plan view of a nitride semiconductor diode having another embodiment 17 of a concentric island topography 18 [0037]
FIG. 28 is a plan view of a nitride semiconductor diode having yet another 19 embodiment of a concentric island topography. 20 [0038]
FIG. 29 is a schematic diagram of a half-bridge circuit. 21 [0039]
FIG. 30 is a plan view of half-islands arranged in rows. 22 [0040]
FIG. 31 is a plan view of half-islands implementing a half-bridge or full-bridge circuit 23 and the corresponding schematic diagram. 24 [0041]
FIG. 32 is another schematic diagram of the full-bridge circuit of
FIG. 33 is a cross-section view of half-islands arranged in a row. 26 [0043]
FIG. 34 is a schematic diagram of a clamped full-bridge rectifier power circuit. 22072614.4 -5- 1 [0044]
FIG. 35 is a plan view of half-islands with interconnections implementing the circuit 2 of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-34. (Previously cancelled) canceled
A nitride semiconductor device comprising: a substrate; a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; a plurality of source island electrodes and a plurality of drain island electrodes of a multi-island transistor formed on the nitride semiconductor layer, the source island electrodes and drain island electrodes being spaced apart from each other and arranged as an array with alternating source island electrodes and drain island electrodes along at least two different axial directions to produce two-dimensional active regions in a device area of the nitride semiconductor layer; a plurality of gate strip electrodes formed on the nitride semiconductor layer in active regions between adjacent source island electrodes and drain island electrodes, an overlying low resistance gate interconnect running between the source island electrodes and drain island electrodes, the plurality of gate electrodes being interconnected to the low resistance gate interconnect by gate interconnections at interstices defined by adjacent vertices of the source island electrodes and the drain island electrodes; each of the plurality of source island electrodes having a respective individual source contact area (pad) comprising a bump, ball or post connection formed thereon; each of the plurality of drain island electrodes having a respective individual drain contact area (pad) comprising a bump, ball or post connection formed thereon; the low resistance gate interconnect being connected to a plurality of gate pads; and wherein, in defective active regions, individual gate strip electrodes are selectively disconnected from the gate interconnect by absence or removal of respective gate interconnections thereto.
The nitride semiconductor device of claim 35, wherein in defective active regions, individual drain island electrodes are isolated by absence or removal of the bump, ball or post connection thereon.
The device according to The nitride semiconductor device of claim 35, wherein each of the plurality of source island electrodes comprises a plurality of castellated peninsulas extending from at least one side, which are interleaved with a plurality of castellated peninsulas extending from a side of an adjacent one of the plurality of drain island electrodes.
The device according to The nitride semiconductor device of claim 35, wherein the first and second island electrodes: a) have a predominantly rectangular shape; or b) have a predominantly triangular shape; and or c) have a polygon shape that can be arranged as said array of alternating source and drain island electrodes to optimize active area usage.
The device of claim 35 The nitride semiconductor device of claim 35, wherein the nitride semiconductor layer comprises hetero-layer of a layer of undoped gallium nitride (GaN) beneath a layer of undoped aluminum gallium nitride (AIGaN).
canceled
The device of claim 41 A nitride semiconductor device comprising: a substrate; a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; a metallization layer formed on the nitride semiconductor layer defining a plurality of first island electrodes and a plurality of second island electrodes spaced apart from each other and arranged as an array with alternating first island electrodes and second island electrodes along at least two orthogonal directions to produce two-dimensional active regions in a device area of the nitride semiconductor layer, with at least one side of each first island electrode opposite a side of an adjacent second island electrode; at least one side of each second island electrode opposite a side of an adjacent first island electrode; an overlying interconnect structure comprising one or more metallization layers and intervening insulating layers; the one or more metallization layers of the overlying interconnect structure defining a plurality of first common electrodes and a plurality of second common electrodes, the first common electrodes and the second common electrodes being arranged as a second array with alternating first common electrodes and second common electrodes, the second array of first and second common electrodes overlying the array of the first and second island electrodes; each first common electrode being interconnected to a set of said first island electrodes by said one or more metallization layers and conductive vias; and each second common electrode being interconnected to a set of said second island electrodes by said one or more metallization layers and conductive vias; each of the first common electrodes providing an external first connection formed thereon comprising a ball, bump or post connection, and each of the second common electrodes comprises an external first connection formed thereon comprising a ball, bump or post connection; the first island electrodes and second island electrodes serving, respectively, as source island electrodes and drain island electrodes of a multi-island transistor; and a plurality of gate strip electrodes of the multi-island transistor formed on the nitride semiconductor layer in active regions between adjacent first island electrodes and second island electrodes; a low resistance gate interconnect running between the source island electrodes and drain island electrodes overlying the gate strip electrodes, the plurality of gate strip electrodes being interconnected to the low resistance gate interconnect by gate interconnections at interstices defined by adjacent vertices of the first island electrodes and second island electrodes; one or more gate common electrodes comprising an external gate connection formed thereon comprising a ball, bump or post connection; and the gate strap connecting the interconnected gate strip electrodes to the one or more gate common electrodes; and wherein, in defective active regions, individual gate electrodes are selectively disconnected from the gate interconnect by absence or removal of respective gate interconnections thereto.
The nitride semiconductor device of claim 41 claim 43, wherein in said defective active regions, individual drain common electrodes are isolated by absence or removal of the bump, ball or post connection thereon.
The nitride semiconductor device according to claim 41 of claim 43, wherein the first and second island electrodes: a) have a predominantly rectangular shape; or b) have a predominantly triangular shape; and or c) have a polygon shape that can be arranged as said array of alternating source and drain island electrodes to optimize active area usage.
The nitride semiconductor device of claim 41 claim 43 wherein the nitride semiconductor layer comprises hetero-layer of a layer of undoped gallium nitride (GaN) beneath a layer of undoped aluminum gallium nitride (AIGaN).
canceled
A nitride semiconductor device comprising: a substrate; a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; a plurality of source, drain and gate electrodes of a multi-island transistor formed on the nitride semiconductor layer, the plurality of source, drain and gate electrodes comprising concentric electrode islands of decreasing size and arranged as repeated square shaped concentric tracks of ohmic and Schottky contacts, every two ohmic contacts having a Schottky contact in between, a plurality of source concentric island electrodes and a plurality of drain concentric island electrodes being formed from said ohmic concentric tracks, the gate electrodes in between the source and drain concentric electrodes being formed from said Schottky concentric tracks, the source and drain concentric electrodes thereby being alternately arranged such that each source island electrode is adjacent to a drain island electrode with a gate electrode in between; an overlying dielectric isolation layer with an array of a plurality of overlying square shaped source metal pads and drain metal pads formed thereon, the source and drain metal pads being arranged alternately with each source metal pad adjacent a drain metal pad, the corners of each adjacent four metal pads being placed over a set of square shaped concentric tracks of source and drain concentric island electrodes; source concentric island electrodes being connected to a respective overlying source metal pad by conductive via s; drain concentric island electrodes being connected to a respective overlying drain metal pad by conductive via s; and a gate connection point located at the center of each set of concentric tracks and in spaces defined between adjacent corners of the source and drain metal pads.
The device of claim 48 wherein the Schottky gate electrodes are connected to an overlying low resistance interconnect metal strap by gate interconnections to said gate connection points.
The device of claim 48 wherein, in defective regions, Schottky gate electrodes are selectively disconnected from the gate strap by absence or removal of said gate interconnections.
Layer stacks claimed or described, ordered top of device to substrate.
nitride semiconductor multi-island transistor (claim 35)
Materials described outside the worked examples.
nitride semiconductor
undoped gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a plan view of a nitride semiconductor transistor having an island 26 topography using square island electrodes. 27 1 0011 1
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 600–1700 V | — |
Thickness | 3–20 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,508,797Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a plan view of a nitride semiconductor transistor having an island 26 topography using square island electrodes. 27 1 0011 1
FIG. 2 is a plan view on an enlarged scale of a portion of the device shown in
FIG. 3 is a cross-section view along the line I II-III of
FIG. 4 is view on an enlarged scale on the line IV-IV of FIG 1 3 [0014]
FIG. 5 is a cross-section view along the line V-V of F I G. 2 4 [0015]
FIG. 6 is a cross-section view along the line VI-VI of
FIGS. 7A to 7C are graphs of gate width versus square island electrode length at a 6 fixed source to drain spacing. 7 [0017]
FIG. 8 is a plan view of a nitride semiconductor transistor having an island 8 topography layout using square island electrodes aligned orthogonally. 9 [0018]
FIG. 9 is a plan view of a nitride semiconductor transistor having an island 10 topography layout using square island electrodes aligned diagonally. 11 [0019]
FIG. 10 is a plan view of a nitride semiconductor transistor having an island 12 topography layout using triangle island electrodes. 13 [0020]
FIG. 11 is a cross-section view of a packaging of the nitride semiconductor transistor 14 using the island topography. 15 [0021]
FIG. 12 is a plan view of a nitride semiconductor transistor having a square island 16 topography with island clusters. 17 [0022]
FIG. 13 is a cross-section view along the line XIII-XIII of
FIG. 14 is a cross-section view along the line XIV-XIV of
FIG. 15 is a plan view showing the source and drain clusters of the nitride 20 semiconductor transistor of
FIG. 16 is a plan view showing the gate clusters of the nitride semiconductor 22 transistor of
FIG. 17 is an expanded plan view of a portion of
FIG. 18 is a plan view of a nitride semiconductor diode having a square island 25 topography with island clusters. 22072614.4 -4- 1 [0028]
FIG. 19 is a cross-section view along the line XIX-XIX of
FIG. 20 is a plan view of a nitride semiconductor diode having a triangle island 3 topography with island clusters. 4 [0030]
FIG. 21 is a plan view of a nitride semiconductor transistor having a castellated island 5 topography. 6 [0031]
FIG. 22 is a plan view of a nitride semiconductor transistor having another 7 embodiment of the castellated island topography. 8 [0032]
FIG. 23 is a plan view of a nitride semiconductor transistor having a concentric island 9 topography. 10 [0033]
FIG. 24 is a plan view of a larger portion of the nitride semiconductor transistor of 11
FIG. 25 is a cross-section view of a nitride semiconductor transistor having a 13 concentric island topography. 14 [0035]
FIG. 26 is a plan view of a nitride semiconductor transistor having a concentric island 15 topography using hexagon electrode tracks and triangle island metal …
FIG. 27 is a plan view of a nitride semiconductor diode having another embodiment 17 of a concentric island topography 18 [0037]
FIG. 28 is a plan view of a nitride semiconductor diode having yet another 19 embodiment of a concentric island topography. 20 [0038]
FIG. 29 is a schematic diagram of a half-bridge circuit. 21 [0039]
FIG. 30 is a plan view of half-islands arranged in rows. 22 [0040]
FIG. 31 is a plan view of half-islands implementing a half-bridge or full-bridge circuit 23 and the corresponding schematic diagram. 24 [0041]
FIG. 32 is another schematic diagram of the full-bridge circuit of
FIG. 33 is a cross-section view of half-islands arranged in a row. 26 [0043]
FIG. 34 is a schematic diagram of a clamped full-bridge rectifier power circuit. 22072614.4 -5- 1 [0044]
FIG. 35 is a plan view of half-islands with interconnections implementing the circuit 2 of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-34. (Previously cancelled) canceled
A nitride semiconductor device comprising: a substrate; a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; a plurality of source island electrodes and a plurality of drain island electrodes of a multi-island transistor formed on the nitride semiconductor layer, the source island electrodes and drain island electrodes being spaced apart from each other and arranged as an array with alternating source island electrodes and drain island electrodes along at least two different axial directions to produce two-dimensional active regions in a device area of the nitride semiconductor layer; a plurality of gate strip electrodes formed on the nitride semiconductor layer in active regions between adjacent source island electrodes and drain island electrodes, an overlying low resistance gate interconnect running between the source island electrodes and drain island electrodes, the plurality of gate electrodes being interconnected to the low resistance gate interconnect by gate interconnections at interstices defined by adjacent vertices of the source island electrodes and the drain island electrodes; each of the plurality of source island electrodes having a respective individual source contact area (pad) comprising a bump, ball or post connection formed thereon; each of the plurality of drain island electrodes having a respective individual drain contact area (pad) comprising a bump, ball or post connection formed thereon; the low resistance gate interconnect being connected to a plurality of gate pads; and wherein, in defective active regions, individual gate strip electrodes are selectively disconnected from the gate interconnect by absence or removal of respective gate interconnections thereto.
The nitride semiconductor device of claim 35, wherein in defective active regions, individual drain island electrodes are isolated by absence or removal of the bump, ball or post connection thereon.
The device according to The nitride semiconductor device of claim 35, wherein each of the plurality of source island electrodes comprises a plurality of castellated peninsulas extending from at least one side, which are interleaved with a plurality of castellated peninsulas extending from a side of an adjacent one of the plurality of drain island electrodes.
The device according to The nitride semiconductor device of claim 35, wherein the first and second island electrodes: a) have a predominantly rectangular shape; or b) have a predominantly triangular shape; and or c) have a polygon shape that can be arranged as said array of alternating source and drain island electrodes to optimize active area usage.
The device of claim 35 The nitride semiconductor device of claim 35, wherein the nitride semiconductor layer comprises hetero-layer of a layer of undoped gallium nitride (GaN) beneath a layer of undoped aluminum gallium nitride (AIGaN).
canceled
The device of claim 41 A nitride semiconductor device comprising: a substrate; a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; a metallization layer formed on the nitride semiconductor layer defining a plurality of first island electrodes and a plurality of second island electrodes spaced apart from each other and arranged as an array with alternating first island electrodes and second island electrodes along at least two orthogonal directions to produce two-dimensional active regions in a device area of the nitride semiconductor layer, with at least one side of each first island electrode opposite a side of an adjacent second island electrode; at least one side of each second island electrode opposite a side of an adjacent first island electrode; an overlying interconnect structure comprising one or more metallization layers and intervening insulating layers; the one or more metallization layers of the overlying interconnect structure defining a plurality of first common electrodes and a plurality of second common electrodes, the first common electrodes and the second common electrodes being arranged as a second array with alternating first common electrodes and second common electrodes, the second array of first and second common electrodes overlying the array of the first and second island electrodes; each first common electrode being interconnected to a set of said first island electrodes by said one or more metallization layers and conductive vias; and each second common electrode being interconnected to a set of said second island electrodes by said one or more metallization layers and conductive vias; each of the first common electrodes providing an external first connection formed thereon comprising a ball, bump or post connection, and each of the second common electrodes comprises an external first connection formed thereon comprising a ball, bump or post connection; the first island electrodes and second island electrodes serving, respectively, as source island electrodes and drain island electrodes of a multi-island transistor; and a plurality of gate strip electrodes of the multi-island transistor formed on the nitride semiconductor layer in active regions between adjacent first island electrodes and second island electrodes; a low resistance gate interconnect running between the source island electrodes and drain island electrodes overlying the gate strip electrodes, the plurality of gate strip electrodes being interconnected to the low resistance gate interconnect by gate interconnections at interstices defined by adjacent vertices of the first island electrodes and second island electrodes; one or more gate common electrodes comprising an external gate connection formed thereon comprising a ball, bump or post connection; and the gate strap connecting the interconnected gate strip electrodes to the one or more gate common electrodes; and wherein, in defective active regions, individual gate electrodes are selectively disconnected from the gate interconnect by absence or removal of respective gate interconnections thereto.
The nitride semiconductor device of claim 41 claim 43, wherein in said defective active regions, individual drain common electrodes are isolated by absence or removal of the bump, ball or post connection thereon.
The nitride semiconductor device according to claim 41 of claim 43, wherein the first and second island electrodes: a) have a predominantly rectangular shape; or b) have a predominantly triangular shape; and or c) have a polygon shape that can be arranged as said array of alternating source and drain island electrodes to optimize active area usage.
The nitride semiconductor device of claim 41 claim 43 wherein the nitride semiconductor layer comprises hetero-layer of a layer of undoped gallium nitride (GaN) beneath a layer of undoped aluminum gallium nitride (AIGaN).
canceled
A nitride semiconductor device comprising: a substrate; a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; a plurality of source, drain and gate electrodes of a multi-island transistor formed on the nitride semiconductor layer, the plurality of source, drain and gate electrodes comprising concentric electrode islands of decreasing size and arranged as repeated square shaped concentric tracks of ohmic and Schottky contacts, every two ohmic contacts having a Schottky contact in between, a plurality of source concentric island electrodes and a plurality of drain concentric island electrodes being formed from said ohmic concentric tracks, the gate electrodes in between the source and drain concentric electrodes being formed from said Schottky concentric tracks, the source and drain concentric electrodes thereby being alternately arranged such that each source island electrode is adjacent to a drain island electrode with a gate electrode in between; an overlying dielectric isolation layer with an array of a plurality of overlying square shaped source metal pads and drain metal pads formed thereon, the source and drain metal pads being arranged alternately with each source metal pad adjacent a drain metal pad, the corners of each adjacent four metal pads being placed over a set of square shaped concentric tracks of source and drain concentric island electrodes; source concentric island electrodes being connected to a respective overlying source metal pad by conductive via s; drain concentric island electrodes being connected to a respective overlying drain metal pad by conductive via s; and a gate connection point located at the center of each set of concentric tracks and in spaces defined between adjacent corners of the source and drain metal pads.
The device of claim 48 wherein the Schottky gate electrodes are connected to an overlying low resistance interconnect metal strap by gate interconnections to said gate connection points.
The device of claim 48 wherein, in defective regions, Schottky gate electrodes are selectively disconnected from the gate strap by absence or removal of said gate interconnections.
Layer stacks claimed or described, ordered top of device to substrate.
nitride semiconductor multi-island transistor (claim 35)
Materials described outside the worked examples.
nitride semiconductor
undoped gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a plan view of a nitride semiconductor transistor having an island 26 topography using square island electrodes. 27 1 0011 1
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 600–1700 V | — |
Thickness | 3–20 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
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US 9,508,797Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a plan view of a nitride semiconductor transistor having an island 26 topography using square island electrodes. 27 1 0011 1
FIG. 2 is a plan view on an enlarged scale of a portion of the device shown in
FIG. 3 is a cross-section view along the line I II-III of
FIG. 4 is view on an enlarged scale on the line IV-IV of FIG 1 3 [0014]
FIG. 5 is a cross-section view along the line V-V of F I G. 2 4 [0015]
FIG. 6 is a cross-section view along the line VI-VI of
FIGS. 7A to 7C are graphs of gate width versus square island electrode length at a 6 fixed source to drain spacing. 7 [0017]
FIG. 8 is a plan view of a nitride semiconductor transistor having an island 8 topography layout using square island electrodes aligned orthogonally. 9 [0018]
FIG. 9 is a plan view of a nitride semiconductor transistor having an island 10 topography layout using square island electrodes aligned diagonally. 11 [0019]
FIG. 10 is a plan view of a nitride semiconductor transistor having an island 12 topography layout using triangle island electrodes. 13 [0020]
FIG. 11 is a cross-section view of a packaging of the nitride semiconductor transistor 14 using the island topography. 15 [0021]
FIG. 12 is a plan view of a nitride semiconductor transistor having a square island 16 topography with island clusters. 17 [0022]
FIG. 13 is a cross-section view along the line XIII-XIII of
FIG. 14 is a cross-section view along the line XIV-XIV of
FIG. 15 is a plan view showing the source and drain clusters of the nitride 20 semiconductor transistor of
FIG. 16 is a plan view showing the gate clusters of the nitride semiconductor 22 transistor of
FIG. 17 is an expanded plan view of a portion of
FIG. 18 is a plan view of a nitride semiconductor diode having a square island 25 topography with island clusters. 22072614.4 -4- 1 [0028]
FIG. 19 is a cross-section view along the line XIX-XIX of
FIG. 20 is a plan view of a nitride semiconductor diode having a triangle island 3 topography with island clusters. 4 [0030]
FIG. 21 is a plan view of a nitride semiconductor transistor having a castellated island 5 topography. 6 [0031]
FIG. 22 is a plan view of a nitride semiconductor transistor having another 7 embodiment of the castellated island topography. 8 [0032]
FIG. 23 is a plan view of a nitride semiconductor transistor having a concentric island 9 topography. 10 [0033]
FIG. 24 is a plan view of a larger portion of the nitride semiconductor transistor of 11
FIG. 25 is a cross-section view of a nitride semiconductor transistor having a 13 concentric island topography. 14 [0035]
FIG. 26 is a plan view of a nitride semiconductor transistor having a concentric island 15 topography using hexagon electrode tracks and triangle island metal …
FIG. 27 is a plan view of a nitride semiconductor diode having another embodiment 17 of a concentric island topography 18 [0037]
FIG. 28 is a plan view of a nitride semiconductor diode having yet another 19 embodiment of a concentric island topography. 20 [0038]
FIG. 29 is a schematic diagram of a half-bridge circuit. 21 [0039]
FIG. 30 is a plan view of half-islands arranged in rows. 22 [0040]
FIG. 31 is a plan view of half-islands implementing a half-bridge or full-bridge circuit 23 and the corresponding schematic diagram. 24 [0041]
FIG. 32 is another schematic diagram of the full-bridge circuit of
FIG. 33 is a cross-section view of half-islands arranged in a row. 26 [0043]
FIG. 34 is a schematic diagram of a clamped full-bridge rectifier power circuit. 22072614.4 -5- 1 [0044]
FIG. 35 is a plan view of half-islands with interconnections implementing the circuit 2 of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-34. (Previously cancelled) canceled
A nitride semiconductor device comprising: a substrate; a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; a plurality of source island electrodes and a plurality of drain island electrodes of a multi-island transistor formed on the nitride semiconductor layer, the source island electrodes and drain island electrodes being spaced apart from each other and arranged as an array with alternating source island electrodes and drain island electrodes along at least two different axial directions to produce two-dimensional active regions in a device area of the nitride semiconductor layer; a plurality of gate strip electrodes formed on the nitride semiconductor layer in active regions between adjacent source island electrodes and drain island electrodes, an overlying low resistance gate interconnect running between the source island electrodes and drain island electrodes, the plurality of gate electrodes being interconnected to the low resistance gate interconnect by gate interconnections at interstices defined by adjacent vertices of the source island electrodes and the drain island electrodes; each of the plurality of source island electrodes having a respective individual source contact area (pad) comprising a bump, ball or post connection formed thereon; each of the plurality of drain island electrodes having a respective individual drain contact area (pad) comprising a bump, ball or post connection formed thereon; the low resistance gate interconnect being connected to a plurality of gate pads; and wherein, in defective active regions, individual gate strip electrodes are selectively disconnected from the gate interconnect by absence or removal of respective gate interconnections thereto.
The nitride semiconductor device of claim 35, wherein in defective active regions, individual drain island electrodes are isolated by absence or removal of the bump, ball or post connection thereon.
The device according to The nitride semiconductor device of claim 35, wherein each of the plurality of source island electrodes comprises a plurality of castellated peninsulas extending from at least one side, which are interleaved with a plurality of castellated peninsulas extending from a side of an adjacent one of the plurality of drain island electrodes.
The device according to The nitride semiconductor device of claim 35, wherein the first and second island electrodes: a) have a predominantly rectangular shape; or b) have a predominantly triangular shape; and or c) have a polygon shape that can be arranged as said array of alternating source and drain island electrodes to optimize active area usage.
The device of claim 35 The nitride semiconductor device of claim 35, wherein the nitride semiconductor layer comprises hetero-layer of a layer of undoped gallium nitride (GaN) beneath a layer of undoped aluminum gallium nitride (AIGaN).
canceled
The device of claim 41 A nitride semiconductor device comprising: a substrate; a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; a metallization layer formed on the nitride semiconductor layer defining a plurality of first island electrodes and a plurality of second island electrodes spaced apart from each other and arranged as an array with alternating first island electrodes and second island electrodes along at least two orthogonal directions to produce two-dimensional active regions in a device area of the nitride semiconductor layer, with at least one side of each first island electrode opposite a side of an adjacent second island electrode; at least one side of each second island electrode opposite a side of an adjacent first island electrode; an overlying interconnect structure comprising one or more metallization layers and intervening insulating layers; the one or more metallization layers of the overlying interconnect structure defining a plurality of first common electrodes and a plurality of second common electrodes, the first common electrodes and the second common electrodes being arranged as a second array with alternating first common electrodes and second common electrodes, the second array of first and second common electrodes overlying the array of the first and second island electrodes; each first common electrode being interconnected to a set of said first island electrodes by said one or more metallization layers and conductive vias; and each second common electrode being interconnected to a set of said second island electrodes by said one or more metallization layers and conductive vias; each of the first common electrodes providing an external first connection formed thereon comprising a ball, bump or post connection, and each of the second common electrodes comprises an external first connection formed thereon comprising a ball, bump or post connection; the first island electrodes and second island electrodes serving, respectively, as source island electrodes and drain island electrodes of a multi-island transistor; and a plurality of gate strip electrodes of the multi-island transistor formed on the nitride semiconductor layer in active regions between adjacent first island electrodes and second island electrodes; a low resistance gate interconnect running between the source island electrodes and drain island electrodes overlying the gate strip electrodes, the plurality of gate strip electrodes being interconnected to the low resistance gate interconnect by gate interconnections at interstices defined by adjacent vertices of the first island electrodes and second island electrodes; one or more gate common electrodes comprising an external gate connection formed thereon comprising a ball, bump or post connection; and the gate strap connecting the interconnected gate strip electrodes to the one or more gate common electrodes; and wherein, in defective active regions, individual gate electrodes are selectively disconnected from the gate interconnect by absence or removal of respective gate interconnections thereto.
The nitride semiconductor device of claim 41 claim 43, wherein in said defective active regions, individual drain common electrodes are isolated by absence or removal of the bump, ball or post connection thereon.
The nitride semiconductor device according to claim 41 of claim 43, wherein the first and second island electrodes: a) have a predominantly rectangular shape; or b) have a predominantly triangular shape; and or c) have a polygon shape that can be arranged as said array of alternating source and drain island electrodes to optimize active area usage.
The nitride semiconductor device of claim 41 claim 43 wherein the nitride semiconductor layer comprises hetero-layer of a layer of undoped gallium nitride (GaN) beneath a layer of undoped aluminum gallium nitride (AIGaN).
canceled
A nitride semiconductor device comprising: a substrate; a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; a plurality of source, drain and gate electrodes of a multi-island transistor formed on the nitride semiconductor layer, the plurality of source, drain and gate electrodes comprising concentric electrode islands of decreasing size and arranged as repeated square shaped concentric tracks of ohmic and Schottky contacts, every two ohmic contacts having a Schottky contact in between, a plurality of source concentric island electrodes and a plurality of drain concentric island electrodes being formed from said ohmic concentric tracks, the gate electrodes in between the source and drain concentric electrodes being formed from said Schottky concentric tracks, the source and drain concentric electrodes thereby being alternately arranged such that each source island electrode is adjacent to a drain island electrode with a gate electrode in between; an overlying dielectric isolation layer with an array of a plurality of overlying square shaped source metal pads and drain metal pads formed thereon, the source and drain metal pads being arranged alternately with each source metal pad adjacent a drain metal pad, the corners of each adjacent four metal pads being placed over a set of square shaped concentric tracks of source and drain concentric island electrodes; source concentric island electrodes being connected to a respective overlying source metal pad by conductive via s; drain concentric island electrodes being connected to a respective overlying drain metal pad by conductive via s; and a gate connection point located at the center of each set of concentric tracks and in spaces defined between adjacent corners of the source and drain metal pads.
The device of claim 48 wherein the Schottky gate electrodes are connected to an overlying low resistance interconnect metal strap by gate interconnections to said gate connection points.
The device of claim 48 wherein, in defective regions, Schottky gate electrodes are selectively disconnected from the gate strap by absence or removal of said gate interconnections.
Layer stacks claimed or described, ordered top of device to substrate.
nitride semiconductor multi-island transistor (claim 35)
Materials described outside the worked examples.
nitride semiconductor
undoped gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a plan view of a nitride semiconductor transistor having an island 26 topography using square island electrodes. 27 1 0011 1
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 600–1700 V | — |
Thickness | 3–20 µm |
Related documents with shared materials, methods, properties, or citations.
nitride semiconductor multi-island transistor with overlying interconnect structure (claim 43)
nitride semiconductor multi-island transistor with concentric square electrode topology (claim 48)
nitride semiconductor transistor (description embodiment)
undoped aluminum gallium nitride
AlGaN
titanium/aluminum (source/drain electrode)
palladium (gate electrode)
Pd
gold (via/bump)
Au
FIG. 4 is view on an enlarged scale on the line IV-IV of FIG 1 3 [0014]
FIG. 8 is a plan view of a nitride semiconductor transistor having an island 8 topography layout using square island electrodes aligned orthogonally. 9 [0018]
FIG. 9 is a plan view of a nitride semiconductor transistor having an island 10 topography layout using square island electrodes aligned diagonally. 11 [0019]
FIG. 10 is a plan view of a nitride semiconductor transistor having an island 12 topography layout using triangle island electrodes. 13 [0020]
FIG. 11 is a cross-section view of a packaging of the nitride semiconductor transistor 14 using the island topography. 15 [0021]
FIG. 12 is a plan view of a nitride semiconductor transistor having a square island 16 topography with island clusters. 17 [0022]
FIG. 15 is a plan view showing the source and drain clusters of the nitride 20 semiconductor transistor of
FIG. 16 is a plan view showing the gate clusters of the nitride semiconductor 22 transistor of
FIG. 21 is a plan view of a nitride semiconductor transistor having a castellated island 5 topography. 6 [0031]
FIG. 22 is a plan view of a nitride semiconductor transistor having another 7 embodiment of the castellated island topography. 8 [0032]
FIG. 23 is a plan view of a nitride semiconductor transistor having a concentric island 9 topography. 10 [0033]
FIG. 24 is a plan view of a larger portion of the nitride semiconductor transistor of 11
FIG. 25 is a cross-section view of a nitride semiconductor transistor having a 13 concentric island topography. 14 [0035]
FIG. 26 is a plan view of a nitride semiconductor transistor having a concentric island 15 topography using hexagon electrode tracks and triangle island metal …
| — |
nitride semiconductor multi-island transistor with overlying interconnect structure (claim 43)
nitride semiconductor multi-island transistor with concentric square electrode topology (claim 48)
nitride semiconductor transistor (description embodiment)
undoped aluminum gallium nitride
AlGaN
titanium/aluminum (source/drain electrode)
palladium (gate electrode)
Pd
gold (via/bump)
Au
FIG. 4 is view on an enlarged scale on the line IV-IV of FIG 1 3 [0014]
FIG. 8 is a plan view of a nitride semiconductor transistor having an island 8 topography layout using square island electrodes aligned orthogonally. 9 [0018]
FIG. 9 is a plan view of a nitride semiconductor transistor having an island 10 topography layout using square island electrodes aligned diagonally. 11 [0019]
FIG. 10 is a plan view of a nitride semiconductor transistor having an island 12 topography layout using triangle island electrodes. 13 [0020]
FIG. 11 is a cross-section view of a packaging of the nitride semiconductor transistor 14 using the island topography. 15 [0021]
FIG. 12 is a plan view of a nitride semiconductor transistor having a square island 16 topography with island clusters. 17 [0022]
FIG. 15 is a plan view showing the source and drain clusters of the nitride 20 semiconductor transistor of
FIG. 16 is a plan view showing the gate clusters of the nitride semiconductor 22 transistor of
FIG. 21 is a plan view of a nitride semiconductor transistor having a castellated island 5 topography. 6 [0031]
FIG. 22 is a plan view of a nitride semiconductor transistor having another 7 embodiment of the castellated island topography. 8 [0032]
FIG. 23 is a plan view of a nitride semiconductor transistor having a concentric island 9 topography. 10 [0033]
FIG. 24 is a plan view of a larger portion of the nitride semiconductor transistor of 11
FIG. 25 is a cross-section view of a nitride semiconductor transistor having a 13 concentric island topography. 14 [0035]
FIG. 26 is a plan view of a nitride semiconductor transistor having a concentric island 15 topography using hexagon electrode tracks and triangle island metal …
| — |
nitride semiconductor multi-island transistor with overlying interconnect structure (claim 43)
nitride semiconductor multi-island transistor with concentric square electrode topology (claim 48)
nitride semiconductor transistor (description embodiment)
undoped aluminum gallium nitride
AlGaN
titanium/aluminum (source/drain electrode)
palladium (gate electrode)
Pd
gold (via/bump)
Au
FIG. 4 is view on an enlarged scale on the line IV-IV of FIG 1 3 [0014]
FIG. 8 is a plan view of a nitride semiconductor transistor having an island 8 topography layout using square island electrodes aligned orthogonally. 9 [0018]
FIG. 9 is a plan view of a nitride semiconductor transistor having an island 10 topography layout using square island electrodes aligned diagonally. 11 [0019]
FIG. 10 is a plan view of a nitride semiconductor transistor having an island 12 topography layout using triangle island electrodes. 13 [0020]
FIG. 11 is a cross-section view of a packaging of the nitride semiconductor transistor 14 using the island topography. 15 [0021]
FIG. 12 is a plan view of a nitride semiconductor transistor having a square island 16 topography with island clusters. 17 [0022]
FIG. 15 is a plan view showing the source and drain clusters of the nitride 20 semiconductor transistor of
FIG. 16 is a plan view showing the gate clusters of the nitride semiconductor 22 transistor of
FIG. 21 is a plan view of a nitride semiconductor transistor having a castellated island 5 topography. 6 [0031]
FIG. 22 is a plan view of a nitride semiconductor transistor having another 7 embodiment of the castellated island topography. 8 [0032]
FIG. 23 is a plan view of a nitride semiconductor transistor having a concentric island 9 topography. 10 [0033]
FIG. 24 is a plan view of a larger portion of the nitride semiconductor transistor of 11
FIG. 25 is a cross-section view of a nitride semiconductor transistor having a 13 concentric island topography. 14 [0035]
FIG. 26 is a plan view of a nitride semiconductor transistor having a concentric island 15 topography using hexagon electrode tracks and triangle island metal …
| — |
nitride semiconductor multi-island transistor with overlying interconnect structure (claim 43)
nitride semiconductor multi-island transistor with concentric square electrode topology (claim 48)
nitride semiconductor transistor (description embodiment)
undoped aluminum gallium nitride
AlGaN
titanium/aluminum (source/drain electrode)
palladium (gate electrode)
Pd
gold (via/bump)
Au
FIG. 4 is view on an enlarged scale on the line IV-IV of FIG 1 3 [0014]
FIG. 8 is a plan view of a nitride semiconductor transistor having an island 8 topography layout using square island electrodes aligned orthogonally. 9 [0018]
FIG. 9 is a plan view of a nitride semiconductor transistor having an island 10 topography layout using square island electrodes aligned diagonally. 11 [0019]
FIG. 10 is a plan view of a nitride semiconductor transistor having an island 12 topography layout using triangle island electrodes. 13 [0020]
FIG. 11 is a cross-section view of a packaging of the nitride semiconductor transistor 14 using the island topography. 15 [0021]
FIG. 12 is a plan view of a nitride semiconductor transistor having a square island 16 topography with island clusters. 17 [0022]
FIG. 15 is a plan view showing the source and drain clusters of the nitride 20 semiconductor transistor of
FIG. 16 is a plan view showing the gate clusters of the nitride semiconductor 22 transistor of
FIG. 21 is a plan view of a nitride semiconductor transistor having a castellated island 5 topography. 6 [0031]
FIG. 22 is a plan view of a nitride semiconductor transistor having another 7 embodiment of the castellated island topography. 8 [0032]
FIG. 23 is a plan view of a nitride semiconductor transistor having a concentric island 9 topography. 10 [0033]
FIG. 24 is a plan view of a larger portion of the nitride semiconductor transistor of 11
FIG. 25 is a cross-section view of a nitride semiconductor transistor having a 13 concentric island topography. 14 [0035]
FIG. 26 is a plan view of a nitride semiconductor transistor having a concentric island 15 topography using hexagon electrode tracks and triangle island metal …
| — |