Patent
US 10,756,183N-CHANNEL GALLIUM NITRIDE TRANSISTORS
Han Wui Then
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,756,183Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an n-channel gallium nitride transistor 100 according to embodiments of the present description. The n-channel gallium nitride transistor …
FIG. 2, a stacked substrate 130 may be formed comprising the charge inducing layer 108 formed on the gallium nitride layer 102. As discussed with regard to
FIG. 3, a hardmask 132, such as silicon nitride, silicon oxide, and the like, may be patterned by any known technique, such as photolithography, on the …
FIG. 4) may be etched to expose a top surface 134 of the hardmask 132 and expose portions of the polarization layer 114, whereby first spacers 144 are formed on …
FIG. 5, the first spacer material 142 (see
FIG. 6) may be etched to expose the hardmask top surface 134, a top surface 146 of the first spacers 144, and expose portions of the polarization layer 114, …
FIG. 7, the second spacer material 152 (see
FIG. 8) may be etched to expose the hardmask top surface 134, the first spacer top surfaces 146, a top surface 156 of the second spacers 154, and portions of …
FIG. 9) may be removed and, using the first spacers 144, the second spacers 154, and the third spacers 164 as etch masks, recesses 172 may be formed to extend …
FIG. 10, the hardmask 132 (see
FIG. 11, the source structures 104 and the shared drain structure 106, such as N + indium gallium nitride, N + gallium nitride, N + indium nitride, and any …
FIG. 12) and the gate electrodes 122 may be formed on the gate dielectric layer 118 such that the gate dielectric layer 118 electrically isolates the gate …
FIG. 13, the gate dielectric layer 118 may be formed on the polarization layer 114 within the recesses 174 (see
FIG. 14 is a flow chart of a process of fabricating an asymmetrical n-channel gallium nitride transistor, according to an embodiment of the present description. …
FIG. 15 illustrates a wireless power/charging device 300, according to an embodiment of the present description. The wireless power/charging device 300 may …
FIG. 16, the transmitter 314 (i.e. full-bridge inverter) may have four n-channel gallium nitride transistors T 1, T 2, T 3, and T 4. Such a configuration, the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
An n-channel gallium nitride transistor, comprising: a gallium nitride layer; a source structure and a drain structure formed in the gallium nitride layer; a charge inducing layer comprising a polarization layer extending between the source structure and the drain structure; and a gate electrode extending at least partially into the polarization layer, wherein a thickness of a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is less than about lnm. Previously presented
The n-channel gallium nitride transistor of claim 2, further comprising a gate dielectric disposed between the gate electrode and the polarization layer. Previously presented
The n-channel gallium nitride transistor of claim 2, further comprising a portion of the polarization layer which is not between the gate electrode and the gallium nitride layer is between about 5nm and 10 nm. Previously presented
The n-channel gallium nitride transistor of claim 2, wherein the polarization layer is selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, and indium gallium nitride. Previously presented
The n-channel gallium nitride transistor of claim 2, further including a crystal transition layer disposed between the gallium nitride layer and the polarization layer. Previously presented
The n-channel gallium nitride transistor of claim 2, further including a gate-to-drain length between about 120 nm to about 400nm and a gate-to-source length between about 5nm to about 400nm. Previously presented
A method of forming an n-channel gallium nitride transistor, comprising: forming a gallium nitride layer; forming a charge inducing layer comprising a polarization layer on the gallium nitride layer; forming a source structure and a drain structure formed in the gallium nitride layer; forming a recess within the polarization layer between the source structure and the drain structure, wherein a thickness of a portion of the polarization layer which is between the recess and the gallium nitride layer is less than about lnm; forming asymmetrical dielectric spacers of different widths; forming a gate dielectric within the recess; and forming a gate electrode adjacent the gate dielectric. Previously presented
The method of claim 10, wherein forming the charge inducing layer comprising the polarization layer on the gallium nitride layer comprises forming the charge inducing layer comprising the polarization layer having a thickness of between about 5nm and 10 nm. Previously presented
The method of claim 10, wherein forming the charge inducing layer comprises forming the polarization layer selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, and indium gallium nitride. Previously presented
The method of claim 10, further including forming a crystal transition layer between the gallium nitride layer and the polarization layer. Previously presented
The method of claim 10, further including forming a gate-to-drain length between about 120 nm to about 400nm and forming a gate-to-source length between about 5nm to about 400nm. Previously presented
A wireless power/charging device transmission module, comprising: a coil assembly; and a transmitter, wherein the transmitter includes at least one n-channel gallium nitride transistor, comprising: a gallium nitride layer; a source structure and a drain structure formed in the gallium nitride layer; a charge inducing layer comprising a polarization layer extending between the source structure and the drain structure; and a gate electrode extending at least partially into the polarization layer. Previously presented
The wireless power/charging device transmission module of claim 17, wherein a thickness of a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is less than about lnm. Previously presented
The wireless power/charging device transmission module of claim 17, further comprising a gate dielectric disposed between the gate electrode and the polarization layer. Previously presented
The wireless power/char ging device transmission module of claim 17, further comprising a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is between about 5nm and 10 nm. Previously presented
The wireless power/charging device transmission module of claim 17, further including a crystal transition layer disposed between the gallium nitride layer and the polarization layer. Previously presented
A wireless power/charging device receiving module, comprising: a coil assembly; a rectifier; and a load unit including a voltage regulator and a battery, wherein the voltage regulator includes at least one n-channel gallium nitride transistor. comprising: a gallium nitride layer; a source structure and a drain structure formed in the gallium nitride layer; a charge inducing layer comprising a polarization layer extending between the source structure and the drain structure; and a gate electrode extending at least partially into the polarization layer. Previously presented
The wireless power/charging device receiving module of claim 22, wherein a thickness of a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is less than about I nm. Previously presented
The wireless power/charging device receiving module of claim 22. further comprising a gate dielectric disposed between the gate electrode and the polarization layer. Previously presented
The wireless power/charging device receiving module of claim 22, further comprising a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is between about 5 nm and 10 nm. Previously presented
The wireless power/charging device receiving module of claim 22, further including a crystal transition layer disposed between the gallium nitride layer and the polarization layer. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
n-channel gallium nitride transistor (enhancement mode, recessed gate)
wireless power/charging device transmission module
No layer stack recorded.
wireless power/charging device receiving module
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride
GaN
polarization layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an n-channel gallium nitride transistor 100 according to embodiments of the present description. The n-channel gallium nitride transistor …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
polarization layer thickness between gate electrode and GaN layer (enhancement mode region) | ≤ 1 nm | polarization layer |
polarization layer thickness in access region (gate-to-drain and gate-to-source areas) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,756,183Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an n-channel gallium nitride transistor 100 according to embodiments of the present description. The n-channel gallium nitride transistor …
FIG. 2, a stacked substrate 130 may be formed comprising the charge inducing layer 108 formed on the gallium nitride layer 102. As discussed with regard to
FIG. 3, a hardmask 132, such as silicon nitride, silicon oxide, and the like, may be patterned by any known technique, such as photolithography, on the …
FIG. 4) may be etched to expose a top surface 134 of the hardmask 132 and expose portions of the polarization layer 114, whereby first spacers 144 are formed on …
FIG. 5, the first spacer material 142 (see
FIG. 6) may be etched to expose the hardmask top surface 134, a top surface 146 of the first spacers 144, and expose portions of the polarization layer 114, …
FIG. 7, the second spacer material 152 (see
FIG. 8) may be etched to expose the hardmask top surface 134, the first spacer top surfaces 146, a top surface 156 of the second spacers 154, and portions of …
FIG. 9) may be removed and, using the first spacers 144, the second spacers 154, and the third spacers 164 as etch masks, recesses 172 may be formed to extend …
FIG. 10, the hardmask 132 (see
FIG. 11, the source structures 104 and the shared drain structure 106, such as N + indium gallium nitride, N + gallium nitride, N + indium nitride, and any …
FIG. 12) and the gate electrodes 122 may be formed on the gate dielectric layer 118 such that the gate dielectric layer 118 electrically isolates the gate …
FIG. 13, the gate dielectric layer 118 may be formed on the polarization layer 114 within the recesses 174 (see
FIG. 14 is a flow chart of a process of fabricating an asymmetrical n-channel gallium nitride transistor, according to an embodiment of the present description. …
FIG. 15 illustrates a wireless power/charging device 300, according to an embodiment of the present description. The wireless power/charging device 300 may …
FIG. 16, the transmitter 314 (i.e. full-bridge inverter) may have four n-channel gallium nitride transistors T 1, T 2, T 3, and T 4. Such a configuration, the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
An n-channel gallium nitride transistor, comprising: a gallium nitride layer; a source structure and a drain structure formed in the gallium nitride layer; a charge inducing layer comprising a polarization layer extending between the source structure and the drain structure; and a gate electrode extending at least partially into the polarization layer, wherein a thickness of a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is less than about lnm. Previously presented
The n-channel gallium nitride transistor of claim 2, further comprising a gate dielectric disposed between the gate electrode and the polarization layer. Previously presented
The n-channel gallium nitride transistor of claim 2, further comprising a portion of the polarization layer which is not between the gate electrode and the gallium nitride layer is between about 5nm and 10 nm. Previously presented
The n-channel gallium nitride transistor of claim 2, wherein the polarization layer is selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, and indium gallium nitride. Previously presented
The n-channel gallium nitride transistor of claim 2, further including a crystal transition layer disposed between the gallium nitride layer and the polarization layer. Previously presented
The n-channel gallium nitride transistor of claim 2, further including a gate-to-drain length between about 120 nm to about 400nm and a gate-to-source length between about 5nm to about 400nm. Previously presented
A method of forming an n-channel gallium nitride transistor, comprising: forming a gallium nitride layer; forming a charge inducing layer comprising a polarization layer on the gallium nitride layer; forming a source structure and a drain structure formed in the gallium nitride layer; forming a recess within the polarization layer between the source structure and the drain structure, wherein a thickness of a portion of the polarization layer which is between the recess and the gallium nitride layer is less than about lnm; forming asymmetrical dielectric spacers of different widths; forming a gate dielectric within the recess; and forming a gate electrode adjacent the gate dielectric. Previously presented
The method of claim 10, wherein forming the charge inducing layer comprising the polarization layer on the gallium nitride layer comprises forming the charge inducing layer comprising the polarization layer having a thickness of between about 5nm and 10 nm. Previously presented
The method of claim 10, wherein forming the charge inducing layer comprises forming the polarization layer selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, and indium gallium nitride. Previously presented
The method of claim 10, further including forming a crystal transition layer between the gallium nitride layer and the polarization layer. Previously presented
The method of claim 10, further including forming a gate-to-drain length between about 120 nm to about 400nm and forming a gate-to-source length between about 5nm to about 400nm. Previously presented
A wireless power/charging device transmission module, comprising: a coil assembly; and a transmitter, wherein the transmitter includes at least one n-channel gallium nitride transistor, comprising: a gallium nitride layer; a source structure and a drain structure formed in the gallium nitride layer; a charge inducing layer comprising a polarization layer extending between the source structure and the drain structure; and a gate electrode extending at least partially into the polarization layer. Previously presented
The wireless power/charging device transmission module of claim 17, wherein a thickness of a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is less than about lnm. Previously presented
The wireless power/charging device transmission module of claim 17, further comprising a gate dielectric disposed between the gate electrode and the polarization layer. Previously presented
The wireless power/char ging device transmission module of claim 17, further comprising a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is between about 5nm and 10 nm. Previously presented
The wireless power/charging device transmission module of claim 17, further including a crystal transition layer disposed between the gallium nitride layer and the polarization layer. Previously presented
A wireless power/charging device receiving module, comprising: a coil assembly; a rectifier; and a load unit including a voltage regulator and a battery, wherein the voltage regulator includes at least one n-channel gallium nitride transistor. comprising: a gallium nitride layer; a source structure and a drain structure formed in the gallium nitride layer; a charge inducing layer comprising a polarization layer extending between the source structure and the drain structure; and a gate electrode extending at least partially into the polarization layer. Previously presented
The wireless power/charging device receiving module of claim 22, wherein a thickness of a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is less than about I nm. Previously presented
The wireless power/charging device receiving module of claim 22. further comprising a gate dielectric disposed between the gate electrode and the polarization layer. Previously presented
The wireless power/charging device receiving module of claim 22, further comprising a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is between about 5 nm and 10 nm. Previously presented
The wireless power/charging device receiving module of claim 22, further including a crystal transition layer disposed between the gallium nitride layer and the polarization layer. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
n-channel gallium nitride transistor (enhancement mode, recessed gate)
wireless power/charging device transmission module
No layer stack recorded.
wireless power/charging device receiving module
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride
GaN
polarization layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an n-channel gallium nitride transistor 100 according to embodiments of the present description. The n-channel gallium nitride transistor …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
polarization layer thickness between gate electrode and GaN layer (enhancement mode region) | ≤ 1 nm | polarization layer |
polarization layer thickness in access region (gate-to-drain and gate-to-source areas) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,756,183Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an n-channel gallium nitride transistor 100 according to embodiments of the present description. The n-channel gallium nitride transistor …
FIG. 2, a stacked substrate 130 may be formed comprising the charge inducing layer 108 formed on the gallium nitride layer 102. As discussed with regard to
FIG. 3, a hardmask 132, such as silicon nitride, silicon oxide, and the like, may be patterned by any known technique, such as photolithography, on the …
FIG. 4) may be etched to expose a top surface 134 of the hardmask 132 and expose portions of the polarization layer 114, whereby first spacers 144 are formed on …
FIG. 5, the first spacer material 142 (see
FIG. 6) may be etched to expose the hardmask top surface 134, a top surface 146 of the first spacers 144, and expose portions of the polarization layer 114, …
FIG. 7, the second spacer material 152 (see
FIG. 8) may be etched to expose the hardmask top surface 134, the first spacer top surfaces 146, a top surface 156 of the second spacers 154, and portions of …
FIG. 9) may be removed and, using the first spacers 144, the second spacers 154, and the third spacers 164 as etch masks, recesses 172 may be formed to extend …
FIG. 10, the hardmask 132 (see
FIG. 11, the source structures 104 and the shared drain structure 106, such as N + indium gallium nitride, N + gallium nitride, N + indium nitride, and any …
FIG. 12) and the gate electrodes 122 may be formed on the gate dielectric layer 118 such that the gate dielectric layer 118 electrically isolates the gate …
FIG. 13, the gate dielectric layer 118 may be formed on the polarization layer 114 within the recesses 174 (see
FIG. 14 is a flow chart of a process of fabricating an asymmetrical n-channel gallium nitride transistor, according to an embodiment of the present description. …
FIG. 15 illustrates a wireless power/charging device 300, according to an embodiment of the present description. The wireless power/charging device 300 may …
FIG. 16, the transmitter 314 (i.e. full-bridge inverter) may have four n-channel gallium nitride transistors T 1, T 2, T 3, and T 4. Such a configuration, the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
An n-channel gallium nitride transistor, comprising: a gallium nitride layer; a source structure and a drain structure formed in the gallium nitride layer; a charge inducing layer comprising a polarization layer extending between the source structure and the drain structure; and a gate electrode extending at least partially into the polarization layer, wherein a thickness of a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is less than about lnm. Previously presented
The n-channel gallium nitride transistor of claim 2, further comprising a gate dielectric disposed between the gate electrode and the polarization layer. Previously presented
The n-channel gallium nitride transistor of claim 2, further comprising a portion of the polarization layer which is not between the gate electrode and the gallium nitride layer is between about 5nm and 10 nm. Previously presented
The n-channel gallium nitride transistor of claim 2, wherein the polarization layer is selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, and indium gallium nitride. Previously presented
The n-channel gallium nitride transistor of claim 2, further including a crystal transition layer disposed between the gallium nitride layer and the polarization layer. Previously presented
The n-channel gallium nitride transistor of claim 2, further including a gate-to-drain length between about 120 nm to about 400nm and a gate-to-source length between about 5nm to about 400nm. Previously presented
A method of forming an n-channel gallium nitride transistor, comprising: forming a gallium nitride layer; forming a charge inducing layer comprising a polarization layer on the gallium nitride layer; forming a source structure and a drain structure formed in the gallium nitride layer; forming a recess within the polarization layer between the source structure and the drain structure, wherein a thickness of a portion of the polarization layer which is between the recess and the gallium nitride layer is less than about lnm; forming asymmetrical dielectric spacers of different widths; forming a gate dielectric within the recess; and forming a gate electrode adjacent the gate dielectric. Previously presented
The method of claim 10, wherein forming the charge inducing layer comprising the polarization layer on the gallium nitride layer comprises forming the charge inducing layer comprising the polarization layer having a thickness of between about 5nm and 10 nm. Previously presented
The method of claim 10, wherein forming the charge inducing layer comprises forming the polarization layer selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, and indium gallium nitride. Previously presented
The method of claim 10, further including forming a crystal transition layer between the gallium nitride layer and the polarization layer. Previously presented
The method of claim 10, further including forming a gate-to-drain length between about 120 nm to about 400nm and forming a gate-to-source length between about 5nm to about 400nm. Previously presented
A wireless power/charging device transmission module, comprising: a coil assembly; and a transmitter, wherein the transmitter includes at least one n-channel gallium nitride transistor, comprising: a gallium nitride layer; a source structure and a drain structure formed in the gallium nitride layer; a charge inducing layer comprising a polarization layer extending between the source structure and the drain structure; and a gate electrode extending at least partially into the polarization layer. Previously presented
The wireless power/charging device transmission module of claim 17, wherein a thickness of a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is less than about lnm. Previously presented
The wireless power/charging device transmission module of claim 17, further comprising a gate dielectric disposed between the gate electrode and the polarization layer. Previously presented
The wireless power/char ging device transmission module of claim 17, further comprising a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is between about 5nm and 10 nm. Previously presented
The wireless power/charging device transmission module of claim 17, further including a crystal transition layer disposed between the gallium nitride layer and the polarization layer. Previously presented
A wireless power/charging device receiving module, comprising: a coil assembly; a rectifier; and a load unit including a voltage regulator and a battery, wherein the voltage regulator includes at least one n-channel gallium nitride transistor. comprising: a gallium nitride layer; a source structure and a drain structure formed in the gallium nitride layer; a charge inducing layer comprising a polarization layer extending between the source structure and the drain structure; and a gate electrode extending at least partially into the polarization layer. Previously presented
The wireless power/charging device receiving module of claim 22, wherein a thickness of a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is less than about I nm. Previously presented
The wireless power/charging device receiving module of claim 22. further comprising a gate dielectric disposed between the gate electrode and the polarization layer. Previously presented
The wireless power/charging device receiving module of claim 22, further comprising a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is between about 5 nm and 10 nm. Previously presented
The wireless power/charging device receiving module of claim 22, further including a crystal transition layer disposed between the gallium nitride layer and the polarization layer. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
n-channel gallium nitride transistor (enhancement mode, recessed gate)
wireless power/charging device transmission module
No layer stack recorded.
wireless power/charging device receiving module
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride
GaN
polarization layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an n-channel gallium nitride transistor 100 according to embodiments of the present description. The n-channel gallium nitride transistor …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
polarization layer thickness between gate electrode and GaN layer (enhancement mode region) | ≤ 1 nm | polarization layer |
polarization layer thickness in access region (gate-to-drain and gate-to-source areas) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,756,183Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an n-channel gallium nitride transistor 100 according to embodiments of the present description. The n-channel gallium nitride transistor …
FIG. 2, a stacked substrate 130 may be formed comprising the charge inducing layer 108 formed on the gallium nitride layer 102. As discussed with regard to
FIG. 3, a hardmask 132, such as silicon nitride, silicon oxide, and the like, may be patterned by any known technique, such as photolithography, on the …
FIG. 4) may be etched to expose a top surface 134 of the hardmask 132 and expose portions of the polarization layer 114, whereby first spacers 144 are formed on …
FIG. 5, the first spacer material 142 (see
FIG. 6) may be etched to expose the hardmask top surface 134, a top surface 146 of the first spacers 144, and expose portions of the polarization layer 114, …
FIG. 7, the second spacer material 152 (see
FIG. 8) may be etched to expose the hardmask top surface 134, the first spacer top surfaces 146, a top surface 156 of the second spacers 154, and portions of …
FIG. 9) may be removed and, using the first spacers 144, the second spacers 154, and the third spacers 164 as etch masks, recesses 172 may be formed to extend …
FIG. 10, the hardmask 132 (see
FIG. 11, the source structures 104 and the shared drain structure 106, such as N + indium gallium nitride, N + gallium nitride, N + indium nitride, and any …
FIG. 12) and the gate electrodes 122 may be formed on the gate dielectric layer 118 such that the gate dielectric layer 118 electrically isolates the gate …
FIG. 13, the gate dielectric layer 118 may be formed on the polarization layer 114 within the recesses 174 (see
FIG. 14 is a flow chart of a process of fabricating an asymmetrical n-channel gallium nitride transistor, according to an embodiment of the present description. …
FIG. 15 illustrates a wireless power/charging device 300, according to an embodiment of the present description. The wireless power/charging device 300 may …
FIG. 16, the transmitter 314 (i.e. full-bridge inverter) may have four n-channel gallium nitride transistors T 1, T 2, T 3, and T 4. Such a configuration, the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
An n-channel gallium nitride transistor, comprising: a gallium nitride layer; a source structure and a drain structure formed in the gallium nitride layer; a charge inducing layer comprising a polarization layer extending between the source structure and the drain structure; and a gate electrode extending at least partially into the polarization layer, wherein a thickness of a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is less than about lnm. Previously presented
The n-channel gallium nitride transistor of claim 2, further comprising a gate dielectric disposed between the gate electrode and the polarization layer. Previously presented
The n-channel gallium nitride transistor of claim 2, further comprising a portion of the polarization layer which is not between the gate electrode and the gallium nitride layer is between about 5nm and 10 nm. Previously presented
The n-channel gallium nitride transistor of claim 2, wherein the polarization layer is selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, and indium gallium nitride. Previously presented
The n-channel gallium nitride transistor of claim 2, further including a crystal transition layer disposed between the gallium nitride layer and the polarization layer. Previously presented
The n-channel gallium nitride transistor of claim 2, further including a gate-to-drain length between about 120 nm to about 400nm and a gate-to-source length between about 5nm to about 400nm. Previously presented
A method of forming an n-channel gallium nitride transistor, comprising: forming a gallium nitride layer; forming a charge inducing layer comprising a polarization layer on the gallium nitride layer; forming a source structure and a drain structure formed in the gallium nitride layer; forming a recess within the polarization layer between the source structure and the drain structure, wherein a thickness of a portion of the polarization layer which is between the recess and the gallium nitride layer is less than about lnm; forming asymmetrical dielectric spacers of different widths; forming a gate dielectric within the recess; and forming a gate electrode adjacent the gate dielectric. Previously presented
The method of claim 10, wherein forming the charge inducing layer comprising the polarization layer on the gallium nitride layer comprises forming the charge inducing layer comprising the polarization layer having a thickness of between about 5nm and 10 nm. Previously presented
The method of claim 10, wherein forming the charge inducing layer comprises forming the polarization layer selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, and indium gallium nitride. Previously presented
The method of claim 10, further including forming a crystal transition layer between the gallium nitride layer and the polarization layer. Previously presented
The method of claim 10, further including forming a gate-to-drain length between about 120 nm to about 400nm and forming a gate-to-source length between about 5nm to about 400nm. Previously presented
A wireless power/charging device transmission module, comprising: a coil assembly; and a transmitter, wherein the transmitter includes at least one n-channel gallium nitride transistor, comprising: a gallium nitride layer; a source structure and a drain structure formed in the gallium nitride layer; a charge inducing layer comprising a polarization layer extending between the source structure and the drain structure; and a gate electrode extending at least partially into the polarization layer. Previously presented
The wireless power/charging device transmission module of claim 17, wherein a thickness of a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is less than about lnm. Previously presented
The wireless power/charging device transmission module of claim 17, further comprising a gate dielectric disposed between the gate electrode and the polarization layer. Previously presented
The wireless power/char ging device transmission module of claim 17, further comprising a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is between about 5nm and 10 nm. Previously presented
The wireless power/charging device transmission module of claim 17, further including a crystal transition layer disposed between the gallium nitride layer and the polarization layer. Previously presented
A wireless power/charging device receiving module, comprising: a coil assembly; a rectifier; and a load unit including a voltage regulator and a battery, wherein the voltage regulator includes at least one n-channel gallium nitride transistor. comprising: a gallium nitride layer; a source structure and a drain structure formed in the gallium nitride layer; a charge inducing layer comprising a polarization layer extending between the source structure and the drain structure; and a gate electrode extending at least partially into the polarization layer. Previously presented
The wireless power/charging device receiving module of claim 22, wherein a thickness of a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is less than about I nm. Previously presented
The wireless power/charging device receiving module of claim 22. further comprising a gate dielectric disposed between the gate electrode and the polarization layer. Previously presented
The wireless power/charging device receiving module of claim 22, further comprising a portion of the polarization layer which is between the gate electrode and the gallium nitride layer is between about 5 nm and 10 nm. Previously presented
The wireless power/charging device receiving module of claim 22, further including a crystal transition layer disposed between the gallium nitride layer and the polarization layer. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
n-channel gallium nitride transistor (enhancement mode, recessed gate)
wireless power/charging device transmission module
No layer stack recorded.
wireless power/charging device receiving module
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride
GaN
polarization layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an n-channel gallium nitride transistor 100 according to embodiments of the present description. The n-channel gallium nitride transistor …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
polarization layer thickness between gate electrode and GaN layer (enhancement mode region) | ≤ 1 nm | polarization layer |
polarization layer thickness in access region (gate-to-drain and gate-to-source areas) |
Related documents with shared materials, methods, properties, or citations.
aluminum gallium nitride
AlGaN
aluminum indium nitride
AlInN
indium gallium nitride
InGaN
crystal transition layer
indium nitride/aluminum nitride
gate dielectric
Al0.83In0.17N
silicon dioxide
SiO₂
silicon oxynitride
SiOxNy
silicon nitride
Si₃N₄
hafnium oxide
HfO₂
indium nitride
InN
aluminum nitride
AlN
FIG. 12) and the gate electrodes 122 may be formed on the gate dielectric layer 118 such that the gate dielectric layer 118 electrically isolates the gate …
FIG. 14 is a flow chart of a process of fabricating an asymmetrical n-channel gallium nitride transistor, according to an embodiment of the present description. …
FIG. 16, the transmitter 314 (i.e. full-bridge inverter) may have four n-channel gallium nitride transistors T 1, T 2, T 3, and T 4. Such a configuration, the …
polarization layer |
crystal transition layer thickness | ≤ 1 nm | crystal transition layer |
gate-to-drain length LGD | 120–400 nm | — |
gate-to-source length LGS | 5–400 nm | — |
gate length LG | 20–500 nm | — |
Thickness | 0–500 nm | — |
Thickness | ≥ 1 cm | — |
aluminum gallium nitride
AlGaN
aluminum indium nitride
AlInN
indium gallium nitride
InGaN
crystal transition layer
indium nitride/aluminum nitride
gate dielectric
Al0.83In0.17N
silicon dioxide
SiO₂
silicon oxynitride
SiOxNy
silicon nitride
Si₃N₄
hafnium oxide
HfO₂
indium nitride
InN
aluminum nitride
AlN
FIG. 12) and the gate electrodes 122 may be formed on the gate dielectric layer 118 such that the gate dielectric layer 118 electrically isolates the gate …
FIG. 14 is a flow chart of a process of fabricating an asymmetrical n-channel gallium nitride transistor, according to an embodiment of the present description. …
FIG. 16, the transmitter 314 (i.e. full-bridge inverter) may have four n-channel gallium nitride transistors T 1, T 2, T 3, and T 4. Such a configuration, the …
polarization layer |
crystal transition layer thickness | ≤ 1 nm | crystal transition layer |
gate-to-drain length LGD | 120–400 nm | — |
gate-to-source length LGS | 5–400 nm | — |
gate length LG | 20–500 nm | — |
Thickness | 0–500 nm | — |
Thickness | ≥ 1 cm | — |
aluminum gallium nitride
AlGaN
aluminum indium nitride
AlInN
indium gallium nitride
InGaN
crystal transition layer
indium nitride/aluminum nitride
gate dielectric
Al0.83In0.17N
silicon dioxide
SiO₂
silicon oxynitride
SiOxNy
silicon nitride
Si₃N₄
hafnium oxide
HfO₂
indium nitride
InN
aluminum nitride
AlN
FIG. 12) and the gate electrodes 122 may be formed on the gate dielectric layer 118 such that the gate dielectric layer 118 electrically isolates the gate …
FIG. 14 is a flow chart of a process of fabricating an asymmetrical n-channel gallium nitride transistor, according to an embodiment of the present description. …
FIG. 16, the transmitter 314 (i.e. full-bridge inverter) may have four n-channel gallium nitride transistors T 1, T 2, T 3, and T 4. Such a configuration, the …
polarization layer |
crystal transition layer thickness | ≤ 1 nm | crystal transition layer |
gate-to-drain length LGD | 120–400 nm | — |
gate-to-source length LGS | 5–400 nm | — |
gate length LG | 20–500 nm | — |
Thickness | 0–500 nm | — |
Thickness | ≥ 1 cm | — |
aluminum gallium nitride
AlGaN
aluminum indium nitride
AlInN
indium gallium nitride
InGaN
crystal transition layer
indium nitride/aluminum nitride
gate dielectric
Al0.83In0.17N
silicon dioxide
SiO₂
silicon oxynitride
SiOxNy
silicon nitride
Si₃N₄
hafnium oxide
HfO₂
indium nitride
InN
aluminum nitride
AlN
FIG. 12) and the gate electrodes 122 may be formed on the gate dielectric layer 118 such that the gate dielectric layer 118 electrically isolates the gate …
FIG. 14 is a flow chart of a process of fabricating an asymmetrical n-channel gallium nitride transistor, according to an embodiment of the present description. …
FIG. 16, the transmitter 314 (i.e. full-bridge inverter) may have four n-channel gallium nitride transistors T 1, T 2, T 3, and T 4. Such a configuration, the …
polarization layer |
crystal transition layer thickness | ≤ 1 nm | crystal transition layer |
gate-to-drain length LGD | 120–400 nm | — |
gate-to-source length LGS | 5–400 nm | — |
gate length LG | 20–500 nm | — |
Thickness | 0–500 nm | — |
Thickness | ≥ 1 cm | — |