Patent
US 9,385,001SELF-ALIGNED ITO GATE ELECTRODE FOR GAN HEMT DEVICE
Yongxiang He
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 9,385,001Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. In
FIG. 2D, a lift-off process is used to remove the second mask layer 211, taking along portions of the first metal layer 213 deposited on the second mask layer …
FIG. 3, a P-N junction gate HEMT device 300 begins with a substrate 302. Substrate 302 can be silicon (Si), silicon carbide (SiC), sapphire (A 120 3), bulk …
FIG. 4G. Accordingly, the gate electrode 410 and the gate layer 408 are substantially the same length. The length of the gate electrode 410 and the gate layer …
FIGS. 5 and 6 have the same channel layer thickness, barrier layer thickness, and gate electrode thickness. The only difference is the length of the gate layer …
FIG. 6. As previously explained, the offset in the gate electrode and gate layer of the prior art P-N junction gate HEMT devices along with the degraded -16- …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high electron mobility transistor (HEMT) comprising: a heterojunction comprising a ba rr ier layer formed on a channel layer, the barrier layer and the channel layer comprising group I II -V semiconductor materials; a gate layer comprising a P-type group I II -V semiconductor material formed on the barr ier layer; and a gate electrode comprising indium tin oxide (I TO) formed on the gate layer and electrically coupled to the gate layer, wherein the gate electrode and the gate layer have substantially the same length.
The HEMT device of claim 1, further comprising: a source electrode and a drain electrode formed on the ba rr ier layer and electrically coupled to the barrier layer.
The HEMT device of claim 1, wherein the channel layer comprises gallium nitride (GaN).
The HEMT device of claim 1, wherein the ba rr ier layer comprises aluminum gallium nitride (A l GaN).
The HEMT device of claim 1, wherein the gate layer comprises gallium nitride (GaN).
The HEMT device of claim 1, wherein the length of the gate electrode and gate layer is between 1 m to 4 m. -18- 1283810-0029US
The HEMT device of claim 1, wherein the length of the gate electrode and gate layer is 1 m or less.
The HEMT device of claim 1, wherein the gate electrode has a thickness between 0.04 m and 0.3 m.
The HEMT device of claim 1, wherein the gate layer has a thickness between 0.04 m and 0.3 m.
A method of forming a high electron mobility transistor (HEMT) comprising: providing a substrate; forming a channel layer comprising a group I II -V semiconductor material on the substrate; forming a barrier layer comprising a group I II -V semiconductor material on the channel layer to create a heterojunction; forming a gate layer comprising a P-type group I II -V semiconductor material on the barr ier layer; depositing a gate electrode layer comprising indium tin oxide (I TO) on the gate layer; patterning the gate electrode layer; etching the gate electrode layer to form a gate electrode using a wet-etch process; and etching the gate layer using a dry-etch process, wherein the gate electrode and the gate layer have substantially the same length.
The method of claim 10, further comprising: forming a source electrode and a drain electrode on the ba rr ier layer after etching the gate layer; and -19- 1283810-0029US annealing the source electrode, the drain electrode, and the gate electrode in a nitrogen (N 2) rich environment, with substantially no oxygen (02).
The method of claim 10, wherein the gate electrode layer is deposited using an electron beam evaporation process.
The method of claim 10, wherein the gate electrode layer is deposited using a sputtering process.
The method of claim 10, wherein the channel layer comprises gallium nitride (GaN).
The method of claim 10, wherein the barrier GaN).
The method of claim 10, wherein the gate layer
The method of claim 10, wherein the length m to 4 m.
The method of claim 10, wherein the length
The method of claim 10, wherein the gate m.
The method of claim 10, wherein the gate layer -20-layer comprises aluminum gallium nitride (A l comprises gallium nitride (GaN). of the gate electrode and gate layer is between 1 of the gate electrode and gate layer is 1 m or less. electrode has a thickness between 0.04 m and 0.3 has a thickness between 0.04 m and 0.3 m.
Layer stacks claimed or described, ordered top of device to substrate.
P-N junction gate HEMT with self-aligned ITO gate electrode
Materials described outside the worked examples.
indium tin oxide
ITO
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4G. Accordingly, the gate electrode 410 and the gate layer 408 are substantially the same length. The length of the gate electrode 410 and the gate layer …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,385,001Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. In
FIG. 2D, a lift-off process is used to remove the second mask layer 211, taking along portions of the first metal layer 213 deposited on the second mask layer …
FIG. 3, a P-N junction gate HEMT device 300 begins with a substrate 302. Substrate 302 can be silicon (Si), silicon carbide (SiC), sapphire (A 120 3), bulk …
FIG. 4G. Accordingly, the gate electrode 410 and the gate layer 408 are substantially the same length. The length of the gate electrode 410 and the gate layer …
FIGS. 5 and 6 have the same channel layer thickness, barrier layer thickness, and gate electrode thickness. The only difference is the length of the gate layer …
FIG. 6. As previously explained, the offset in the gate electrode and gate layer of the prior art P-N junction gate HEMT devices along with the degraded -16- …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high electron mobility transistor (HEMT) comprising: a heterojunction comprising a ba rr ier layer formed on a channel layer, the barrier layer and the channel layer comprising group I II -V semiconductor materials; a gate layer comprising a P-type group I II -V semiconductor material formed on the barr ier layer; and a gate electrode comprising indium tin oxide (I TO) formed on the gate layer and electrically coupled to the gate layer, wherein the gate electrode and the gate layer have substantially the same length.
The HEMT device of claim 1, further comprising: a source electrode and a drain electrode formed on the ba rr ier layer and electrically coupled to the barrier layer.
The HEMT device of claim 1, wherein the channel layer comprises gallium nitride (GaN).
The HEMT device of claim 1, wherein the ba rr ier layer comprises aluminum gallium nitride (A l GaN).
The HEMT device of claim 1, wherein the gate layer comprises gallium nitride (GaN).
The HEMT device of claim 1, wherein the length of the gate electrode and gate layer is between 1 m to 4 m. -18- 1283810-0029US
The HEMT device of claim 1, wherein the length of the gate electrode and gate layer is 1 m or less.
The HEMT device of claim 1, wherein the gate electrode has a thickness between 0.04 m and 0.3 m.
The HEMT device of claim 1, wherein the gate layer has a thickness between 0.04 m and 0.3 m.
A method of forming a high electron mobility transistor (HEMT) comprising: providing a substrate; forming a channel layer comprising a group I II -V semiconductor material on the substrate; forming a barrier layer comprising a group I II -V semiconductor material on the channel layer to create a heterojunction; forming a gate layer comprising a P-type group I II -V semiconductor material on the barr ier layer; depositing a gate electrode layer comprising indium tin oxide (I TO) on the gate layer; patterning the gate electrode layer; etching the gate electrode layer to form a gate electrode using a wet-etch process; and etching the gate layer using a dry-etch process, wherein the gate electrode and the gate layer have substantially the same length.
The method of claim 10, further comprising: forming a source electrode and a drain electrode on the ba rr ier layer after etching the gate layer; and -19- 1283810-0029US annealing the source electrode, the drain electrode, and the gate electrode in a nitrogen (N 2) rich environment, with substantially no oxygen (02).
The method of claim 10, wherein the gate electrode layer is deposited using an electron beam evaporation process.
The method of claim 10, wherein the gate electrode layer is deposited using a sputtering process.
The method of claim 10, wherein the channel layer comprises gallium nitride (GaN).
The method of claim 10, wherein the barrier GaN).
The method of claim 10, wherein the gate layer
The method of claim 10, wherein the length m to 4 m.
The method of claim 10, wherein the length
The method of claim 10, wherein the gate m.
The method of claim 10, wherein the gate layer -20-layer comprises aluminum gallium nitride (A l comprises gallium nitride (GaN). of the gate electrode and gate layer is between 1 of the gate electrode and gate layer is 1 m or less. electrode has a thickness between 0.04 m and 0.3 has a thickness between 0.04 m and 0.3 m.
Layer stacks claimed or described, ordered top of device to substrate.
P-N junction gate HEMT with self-aligned ITO gate electrode
Materials described outside the worked examples.
indium tin oxide
ITO
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4G. Accordingly, the gate electrode 410 and the gate layer 408 are substantially the same length. The length of the gate electrode 410 and the gate layer …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,385,001Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. In
FIG. 2D, a lift-off process is used to remove the second mask layer 211, taking along portions of the first metal layer 213 deposited on the second mask layer …
FIG. 3, a P-N junction gate HEMT device 300 begins with a substrate 302. Substrate 302 can be silicon (Si), silicon carbide (SiC), sapphire (A 120 3), bulk …
FIG. 4G. Accordingly, the gate electrode 410 and the gate layer 408 are substantially the same length. The length of the gate electrode 410 and the gate layer …
FIGS. 5 and 6 have the same channel layer thickness, barrier layer thickness, and gate electrode thickness. The only difference is the length of the gate layer …
FIG. 6. As previously explained, the offset in the gate electrode and gate layer of the prior art P-N junction gate HEMT devices along with the degraded -16- …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high electron mobility transistor (HEMT) comprising: a heterojunction comprising a ba rr ier layer formed on a channel layer, the barrier layer and the channel layer comprising group I II -V semiconductor materials; a gate layer comprising a P-type group I II -V semiconductor material formed on the barr ier layer; and a gate electrode comprising indium tin oxide (I TO) formed on the gate layer and electrically coupled to the gate layer, wherein the gate electrode and the gate layer have substantially the same length.
The HEMT device of claim 1, further comprising: a source electrode and a drain electrode formed on the ba rr ier layer and electrically coupled to the barrier layer.
The HEMT device of claim 1, wherein the channel layer comprises gallium nitride (GaN).
The HEMT device of claim 1, wherein the ba rr ier layer comprises aluminum gallium nitride (A l GaN).
The HEMT device of claim 1, wherein the gate layer comprises gallium nitride (GaN).
The HEMT device of claim 1, wherein the length of the gate electrode and gate layer is between 1 m to 4 m. -18- 1283810-0029US
The HEMT device of claim 1, wherein the length of the gate electrode and gate layer is 1 m or less.
The HEMT device of claim 1, wherein the gate electrode has a thickness between 0.04 m and 0.3 m.
The HEMT device of claim 1, wherein the gate layer has a thickness between 0.04 m and 0.3 m.
A method of forming a high electron mobility transistor (HEMT) comprising: providing a substrate; forming a channel layer comprising a group I II -V semiconductor material on the substrate; forming a barrier layer comprising a group I II -V semiconductor material on the channel layer to create a heterojunction; forming a gate layer comprising a P-type group I II -V semiconductor material on the barr ier layer; depositing a gate electrode layer comprising indium tin oxide (I TO) on the gate layer; patterning the gate electrode layer; etching the gate electrode layer to form a gate electrode using a wet-etch process; and etching the gate layer using a dry-etch process, wherein the gate electrode and the gate layer have substantially the same length.
The method of claim 10, further comprising: forming a source electrode and a drain electrode on the ba rr ier layer after etching the gate layer; and -19- 1283810-0029US annealing the source electrode, the drain electrode, and the gate electrode in a nitrogen (N 2) rich environment, with substantially no oxygen (02).
The method of claim 10, wherein the gate electrode layer is deposited using an electron beam evaporation process.
The method of claim 10, wherein the gate electrode layer is deposited using a sputtering process.
The method of claim 10, wherein the channel layer comprises gallium nitride (GaN).
The method of claim 10, wherein the barrier GaN).
The method of claim 10, wherein the gate layer
The method of claim 10, wherein the length m to 4 m.
The method of claim 10, wherein the length
The method of claim 10, wherein the gate m.
The method of claim 10, wherein the gate layer -20-layer comprises aluminum gallium nitride (A l comprises gallium nitride (GaN). of the gate electrode and gate layer is between 1 of the gate electrode and gate layer is 1 m or less. electrode has a thickness between 0.04 m and 0.3 has a thickness between 0.04 m and 0.3 m.
Layer stacks claimed or described, ordered top of device to substrate.
P-N junction gate HEMT with self-aligned ITO gate electrode
Materials described outside the worked examples.
indium tin oxide
ITO
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4G. Accordingly, the gate electrode 410 and the gate layer 408 are substantially the same length. The length of the gate electrode 410 and the gate layer …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,385,001Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. In
FIG. 2D, a lift-off process is used to remove the second mask layer 211, taking along portions of the first metal layer 213 deposited on the second mask layer …
FIG. 3, a P-N junction gate HEMT device 300 begins with a substrate 302. Substrate 302 can be silicon (Si), silicon carbide (SiC), sapphire (A 120 3), bulk …
FIG. 4G. Accordingly, the gate electrode 410 and the gate layer 408 are substantially the same length. The length of the gate electrode 410 and the gate layer …
FIGS. 5 and 6 have the same channel layer thickness, barrier layer thickness, and gate electrode thickness. The only difference is the length of the gate layer …
FIG. 6. As previously explained, the offset in the gate electrode and gate layer of the prior art P-N junction gate HEMT devices along with the degraded -16- …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high electron mobility transistor (HEMT) comprising: a heterojunction comprising a ba rr ier layer formed on a channel layer, the barrier layer and the channel layer comprising group I II -V semiconductor materials; a gate layer comprising a P-type group I II -V semiconductor material formed on the barr ier layer; and a gate electrode comprising indium tin oxide (I TO) formed on the gate layer and electrically coupled to the gate layer, wherein the gate electrode and the gate layer have substantially the same length.
The HEMT device of claim 1, further comprising: a source electrode and a drain electrode formed on the ba rr ier layer and electrically coupled to the barrier layer.
The HEMT device of claim 1, wherein the channel layer comprises gallium nitride (GaN).
The HEMT device of claim 1, wherein the ba rr ier layer comprises aluminum gallium nitride (A l GaN).
The HEMT device of claim 1, wherein the gate layer comprises gallium nitride (GaN).
The HEMT device of claim 1, wherein the length of the gate electrode and gate layer is between 1 m to 4 m. -18- 1283810-0029US
The HEMT device of claim 1, wherein the length of the gate electrode and gate layer is 1 m or less.
The HEMT device of claim 1, wherein the gate electrode has a thickness between 0.04 m and 0.3 m.
The HEMT device of claim 1, wherein the gate layer has a thickness between 0.04 m and 0.3 m.
A method of forming a high electron mobility transistor (HEMT) comprising: providing a substrate; forming a channel layer comprising a group I II -V semiconductor material on the substrate; forming a barrier layer comprising a group I II -V semiconductor material on the channel layer to create a heterojunction; forming a gate layer comprising a P-type group I II -V semiconductor material on the barr ier layer; depositing a gate electrode layer comprising indium tin oxide (I TO) on the gate layer; patterning the gate electrode layer; etching the gate electrode layer to form a gate electrode using a wet-etch process; and etching the gate layer using a dry-etch process, wherein the gate electrode and the gate layer have substantially the same length.
The method of claim 10, further comprising: forming a source electrode and a drain electrode on the ba rr ier layer after etching the gate layer; and -19- 1283810-0029US annealing the source electrode, the drain electrode, and the gate electrode in a nitrogen (N 2) rich environment, with substantially no oxygen (02).
The method of claim 10, wherein the gate electrode layer is deposited using an electron beam evaporation process.
The method of claim 10, wherein the gate electrode layer is deposited using a sputtering process.
The method of claim 10, wherein the channel layer comprises gallium nitride (GaN).
The method of claim 10, wherein the barrier GaN).
The method of claim 10, wherein the gate layer
The method of claim 10, wherein the length m to 4 m.
The method of claim 10, wherein the length
The method of claim 10, wherein the gate m.
The method of claim 10, wherein the gate layer -20-layer comprises aluminum gallium nitride (A l comprises gallium nitride (GaN). of the gate electrode and gate layer is between 1 of the gate electrode and gate layer is 1 m or less. electrode has a thickness between 0.04 m and 0.3 has a thickness between 0.04 m and 0.3 m.
Layer stacks claimed or described, ordered top of device to substrate.
P-N junction gate HEMT with self-aligned ITO gate electrode
Materials described outside the worked examples.
indium tin oxide
ITO
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4G. Accordingly, the gate electrode 410 and the gate layer 408 are substantially the same length. The length of the gate electrode 410 and the gate layer …
Related documents with shared materials, methods, properties, or citations.
aluminum gallium nitride
AlGaN
P-type gallium nitride
p-GaN
FIGS. 5 and 6 have the same channel layer thickness, barrier layer thickness, and gate electrode thickness. The only difference is the length of the gate layer …
FIGS. 5 and 6 have the same channel layer thickness, barrier layer thickness, and gate electrode thickness. The only difference is the length of the gate layer …
FIG. 6. As previously explained, the offset in the gate electrode and gate layer of the prior art P-N junction gate HEMT devices along with the degraded -16- …
aluminum gallium nitride
AlGaN
P-type gallium nitride
p-GaN
FIGS. 5 and 6 have the same channel layer thickness, barrier layer thickness, and gate electrode thickness. The only difference is the length of the gate layer …
FIGS. 5 and 6 have the same channel layer thickness, barrier layer thickness, and gate electrode thickness. The only difference is the length of the gate layer …
FIG. 6. As previously explained, the offset in the gate electrode and gate layer of the prior art P-N junction gate HEMT devices along with the degraded -16- …
aluminum gallium nitride
AlGaN
P-type gallium nitride
p-GaN
FIGS. 5 and 6 have the same channel layer thickness, barrier layer thickness, and gate electrode thickness. The only difference is the length of the gate layer …
FIGS. 5 and 6 have the same channel layer thickness, barrier layer thickness, and gate electrode thickness. The only difference is the length of the gate layer …
FIG. 6. As previously explained, the offset in the gate electrode and gate layer of the prior art P-N junction gate HEMT devices along with the degraded -16- …
aluminum gallium nitride
AlGaN
P-type gallium nitride
p-GaN
FIGS. 5 and 6 have the same channel layer thickness, barrier layer thickness, and gate electrode thickness. The only difference is the length of the gate layer …
FIGS. 5 and 6 have the same channel layer thickness, barrier layer thickness, and gate electrode thickness. The only difference is the length of the gate layer …
FIG. 6. As previously explained, the offset in the gate electrode and gate layer of the prior art P-N junction gate HEMT devices along with the degraded -16- …