Patent
US 9,793,389Apparatus And Method Of Fabrication For GaN/Si Transistors Isolation
Chan-Hong Chern
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,793,389Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a block diagram of an example semiconductor device that is fabricated on a silicon on insulator (SOI) wafer and that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figure 2 is a process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figure 3 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. 1 TSMC No. 2016-0105/Attorney Docket No. 181877-625231
Figure 4 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figures 5A, 5B, 5C, 5D, and 5E provide cross-sectional views of an example semiconductor device during various stages of fabrication according to operations specified in
Figure 6 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figures 7A, 7B, 7C, and 7D provide cross-sectional views of an example semiconductor device during various stages of fabrication according to operations specified in
Figure 8 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figure 9 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figures 10 A, 10 B, 10 C, and 10 D provide cross-sectional views of an example semiconductor device during various stages of fabrication according to operations specified in
Figure 11 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. 2 TSMC No. 2016-0105/Attorney Docket No. 181877-625231 [0
Figures 12A, 12B, 12C, 12D, 12E, 12F, and 12G provide cross-sectional views of an example semiconductor device during various stages of fabrication according to operations specified in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device having an isolated first transistor circuit and an isolated second transistor circuit, the method comprising: providing a silicon on insulator (SO I) wafer comprising an insulator layer and a silicon layer disposed over the insulator layer; applying a first mask to the silicon layer; etching the first mask and the silicon layer to an etch stop at the insulator to form fabricating an isolated first silicon region and an isolated second silicon region each disposed over the insulator layer, the isolated first and second silicon regions being separated from one another by a trench; on the SOI wafer, filling the trench with insulator material so as to bound each of the first silicon region and the second silicon region bounded on its respective sides by the a trench filled with insulator material; after filling the trench, removing the first mask to define a first cavity over the isolated first silicon region and a second cavity over the isolated second silicon region; after removing the first mask, fabricating [[an]] a first active area comprising gallium nitride (GaN) on each of within the first cavity over the isolated first silicon region and a second active area comprising GaN within the second cavity over the isolated second silicon region to respectively form the first transistor circuit and the second transistor circuit; and fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit.
-2- NAI-1502598161v1 3. The method of claim 1 wherein fabricating [[an]] the first active area comprising GaN on each of the first silicon region and the second silicon region comprises fabricating through epitaxial growth a f i rst GaN layer on each of the isolated first silicon region and the second silicon region; fabricating through epitaxial growth [[an]] a first aluminum gallium nitride (AlGaN) layer on each of the first GaN layers laeyr; and wherein fabricating the second active area comprises fabricating through epitaxial growth a second GaN layer on the isolated second silicon region and fabricating through epitaxial growth a second AlGaN layer on the second GaN layer fabricating through epitaxial growth a polarization modulation layer above each of the AlGaN layers; patterning the polarization modulation layers; and fabricating through deposition and polishing a passivation layer above each of the first silicon region and the second silicon region. currently amended
The method of claim 1 wherein the fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit comprises: fabricating the body connection for each of the first transistor circuit and the second transistor circuit; and fabricating the source, drain, and gate connection for each of the first transistor circuit and the second transistor circuit after fabricating the body connection.
The method of claim 1 wherein fabricating the body connection for each of the first transistor circuit and the second transistor circuit comprises: applying a second mask above the wafer; etching a first via hole through the second mask and the first active area of each of the first transistor circuit and the second transistor circuit to the isolated first silicon region, the first via hole having a first sidewall layer above the insulator; etching a second via hole through the second mask and the second active area of the second transistor circuit to the isolated second silicon region, the second via hole having a second sidewall: -3- NAI-1502598161v1 respectively coating the via hole sidewall first and second sidewalls with insulator material; and after the coating, implanting metal material into each of the first and second via holes hole in each of the first transistor circuit and the second transistor circuit to form a respective contact to the isolated first and second silicon regions in each of the first transistor circuit and the second transistor circuit.
The method of claim 1 wherein fabricating the source, drain, and gate connections for each of the first transistor circuit and the second transistor circuit comprises: applying a second mask above the wafer; patterning the second mask for contact holes; depositing metal material into the contact holes to form contacts for the source, drain, and gate connections for each of the first transistor circuit and the second transistor circuit; and removing the second mask.
The method of claim [[2]] 1, further comprising wherein fabricating an active area comprising GaN on each of the first silicon region and the second silicon region comprises fabricating through epitaxial growth a GaN layer on each of the first silicon region and the second silicon region; fabricating through epitaxial growth an aluminum gallium nitride (AlGaN) layer on each of the GaN layers; fabricating through epitaxial growth a polarization modulation layer above each of the AlGaN layers; patterning the polarization modulation layers; and -4- NAI-1502598161v1 fabricating through deposition and polishing a passivation layer above each of the isolated first silicon region and the isolated second silicon region.
The method of claim 8 wherein fabricating the body connection for each of the first transistor circuit and the second transistor circuit comprises: applying a second mask above the wafer; etching a first via hole through the second mask and the first active area of each of the first transistor circuit and the second transistor circuit to the isolated first silicon region, the first via hole having a first sidewall layer above the insulator; etching a second via hole through the second mask and the second active area of the second transistor circuit to the isolated second silicon region, the second via hole having a second sidewall; respectively coating the via hole sidewall first and second sidewalls with insulator material; and after the coating, implanting metal material into each of the first and second via holes hole in each of the first transistor circuit and the second transistor circuit to form a respective contact to the isolated first and second silicon regions in each of the first transistor circuit and the second transistor circuit.
Claims 11 -16. canceled
canceled
canceled
canceled
canceled
-5- NAI-1502598161v1 canceled
A method of fabricating gallium nitride (GaN) transistors on a silicon on insulator (SO I) wafer with a GaN transistor in a first transistor circuit having its substrate isolated from the substrate of a transistor in a second transistor circuit, the method comprising: fabricating an isolated first silicon region and an isolated second silicon region on a SO I wafer comprising an insulator layer and a silicon layer disposed over the insulator layer, each of the first silicon region and the second silicon region bounded on its sides by a trench filled with insulator material so as to define a first cavity over the isolated first silicon region and a second cavity over the isolated second silicon region; fabricating [[an]] a first active area within the first cavity over the isolated on each of the first silicon region and fabricating a second active area within the second cavity over the isolated [[the]] second silicon region through epitaxial growth operations to respectively form the first transistor circuit and the second transistor circuit, the first active area of the first silicon region comprising a first GaN layer; and fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit.
The method of claim 17 wherein fabricating [[an]] the isolated first silicon region and an isolated second silicon region on the SO I wafer comprises: applying a mask to the silicon layer above the insulator on the SOI wafer; etching the mask and the silicon layer to an etch stop at the insulator layer to form a silicon trench in the silicon layer separating the isolated first and second silicon regions from one another; filling the trench with insulator material; and removing the mask to define the first cavity and the second cavity.
The method of claim 17 wherein fabricating [[an]] the first active area comprising GaN comprises [[:]] fabricating through epitaxial growth a first GaN layer on each of the isolated first silicon region and the second silicon region; fabricating through epitaxial growth [[an]] a first aluminum gallium nitride (AlGaN) layer on each of the first GaN layer layers; and -6-NAI-1502598161v1 wherein fabricating the second active area comprises fabricating through epitaxial growth a second GaN layer on the isolated second silicon region and fabricating through epitaxial growth a second AlGaN layer on the second GaN layer fabricating through epitaxial growth a polarization modulation layer above each of the AlGaN layers; patterning the polarization modulation layers; and fabricating through deposition and polishing a passivation layer above each of the first silicon region and the second silicon region.
The method of claim 17 wherein fabricating the body connection for each of the first transistor circuit and the second transistor circuit comprises: applying a mask above the wafer; etching a first via hole through the mask and the first active area of each of the each of the first transistor circuit and the second transistor circuit to the isolated first silicon region, the first via hole having a first sidewall layer above the insulator; etching a second via hole through the mask and the second active area of the second transistor circuit to the isolated second silicon region, the second via hole having a second sidewall; respectively coating the via hole sidewall first and second sidewalls with insulator material; and after the coating, implanting metal material into the each of the first and second via holes hole in each of the first transistor circuit and the second transistor circuit to form a respective contact to the isolated first and second silicon regions in each of the first transistor circuit and the second transistor circuit.
A method of fabricating a semiconductor device on a silicon on insulator (SO I) wafer comprising a silicon layer and an insulator layer, the method comprising: fabricating a first transistor circuit on an isolated first silicon region and a second transistor circuit on an isolated second silicon region, each of the first transistor circuit and the second transistor circuit having an active region comprising gallium nitride (GaN) material -7- NAI-1502598161v1 above its respective isolated silicon region, each of the first and second isolated silicon regions each formed from the silicon layer and separated from one another by a trench above the insulator layer on the SOI wafer; filling [[a]] t he trench with an insulator that bounds [[the]] respective sides of the isolated first and second silicon regions, the sides of the active region of the first transistor circuit, and the sides of the active region of the second transistor circuit wherein such that the first silicon region and the first transistor circuit are is isolated from the second silicon region and the second transistor circuit by the insulator material and a cavity respectively is disposed over each of the first and second silicon regions; after filling the trench, respectively fabricating first and second active regions comprising first and second GaN layers within the cavities to form the first transistor circuit and the second transistor circuit to form the first transistor circuit and the second transistor circuit; and providing a respective body contact connection point for each of the first transistor circuit and the second transistor circuit.
The method of claim 21 wherein respectively fabricating the active regions of each of the first transistor circuit and the second transistor circuit comprises a silicon layer, comprises respectively fabricating, within the cavities, a transition layer above the silicon layer, a GaN layer above the transition layer, and an aluminum gallium nitride (AlGaN) layer above the GaN layer.
The method of claim 21 wherein further comprising forming the isolated first silicon region and the isolated second silicon region [[by]] are fabricated using steps comprising: applying a mask above the silicon layer on the SOI wafer; etching the mask and a portion of the silicon layer to an etch stop at the insulator layer of the SOI wafer to form a silicon the trench; filling the trench with insulator material; and removing the mask to form the cavities being.
The method of claim 21 wherein providing [[a]] the respective body contact connection point for each of the first transistor circuit and the second transistor circuit comprises: providing a through-GaN-via (TGV) hole in the active region of the respective transistor circuit to the respective isolated silicon region that is filled with metal material forming a contact to the respective isolated silicon region.
Layer stacks claimed or described, ordered top of device to substrate.
GaN/Si HEMT on SOI wafer with substrate isolation
Materials described outside the worked examples.
gallium nitride
GaN
insulator material (trench fill)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a block diagram of an example semiconductor device that is fabricated on a silicon on insulator (SOI) wafer and that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,793,389Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a block diagram of an example semiconductor device that is fabricated on a silicon on insulator (SOI) wafer and that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figure 2 is a process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figure 3 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. 1 TSMC No. 2016-0105/Attorney Docket No. 181877-625231
Figure 4 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figures 5A, 5B, 5C, 5D, and 5E provide cross-sectional views of an example semiconductor device during various stages of fabrication according to operations specified in
Figure 6 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figures 7A, 7B, 7C, and 7D provide cross-sectional views of an example semiconductor device during various stages of fabrication according to operations specified in
Figure 8 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figure 9 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figures 10 A, 10 B, 10 C, and 10 D provide cross-sectional views of an example semiconductor device during various stages of fabrication according to operations specified in
Figure 11 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. 2 TSMC No. 2016-0105/Attorney Docket No. 181877-625231 [0
Figures 12A, 12B, 12C, 12D, 12E, 12F, and 12G provide cross-sectional views of an example semiconductor device during various stages of fabrication according to operations specified in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device having an isolated first transistor circuit and an isolated second transistor circuit, the method comprising: providing a silicon on insulator (SO I) wafer comprising an insulator layer and a silicon layer disposed over the insulator layer; applying a first mask to the silicon layer; etching the first mask and the silicon layer to an etch stop at the insulator to form fabricating an isolated first silicon region and an isolated second silicon region each disposed over the insulator layer, the isolated first and second silicon regions being separated from one another by a trench; on the SOI wafer, filling the trench with insulator material so as to bound each of the first silicon region and the second silicon region bounded on its respective sides by the a trench filled with insulator material; after filling the trench, removing the first mask to define a first cavity over the isolated first silicon region and a second cavity over the isolated second silicon region; after removing the first mask, fabricating [[an]] a first active area comprising gallium nitride (GaN) on each of within the first cavity over the isolated first silicon region and a second active area comprising GaN within the second cavity over the isolated second silicon region to respectively form the first transistor circuit and the second transistor circuit; and fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit.
-2- NAI-1502598161v1 3. The method of claim 1 wherein fabricating [[an]] the first active area comprising GaN on each of the first silicon region and the second silicon region comprises fabricating through epitaxial growth a f i rst GaN layer on each of the isolated first silicon region and the second silicon region; fabricating through epitaxial growth [[an]] a first aluminum gallium nitride (AlGaN) layer on each of the first GaN layers laeyr; and wherein fabricating the second active area comprises fabricating through epitaxial growth a second GaN layer on the isolated second silicon region and fabricating through epitaxial growth a second AlGaN layer on the second GaN layer fabricating through epitaxial growth a polarization modulation layer above each of the AlGaN layers; patterning the polarization modulation layers; and fabricating through deposition and polishing a passivation layer above each of the first silicon region and the second silicon region. currently amended
The method of claim 1 wherein the fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit comprises: fabricating the body connection for each of the first transistor circuit and the second transistor circuit; and fabricating the source, drain, and gate connection for each of the first transistor circuit and the second transistor circuit after fabricating the body connection.
The method of claim 1 wherein fabricating the body connection for each of the first transistor circuit and the second transistor circuit comprises: applying a second mask above the wafer; etching a first via hole through the second mask and the first active area of each of the first transistor circuit and the second transistor circuit to the isolated first silicon region, the first via hole having a first sidewall layer above the insulator; etching a second via hole through the second mask and the second active area of the second transistor circuit to the isolated second silicon region, the second via hole having a second sidewall: -3- NAI-1502598161v1 respectively coating the via hole sidewall first and second sidewalls with insulator material; and after the coating, implanting metal material into each of the first and second via holes hole in each of the first transistor circuit and the second transistor circuit to form a respective contact to the isolated first and second silicon regions in each of the first transistor circuit and the second transistor circuit.
The method of claim 1 wherein fabricating the source, drain, and gate connections for each of the first transistor circuit and the second transistor circuit comprises: applying a second mask above the wafer; patterning the second mask for contact holes; depositing metal material into the contact holes to form contacts for the source, drain, and gate connections for each of the first transistor circuit and the second transistor circuit; and removing the second mask.
The method of claim [[2]] 1, further comprising wherein fabricating an active area comprising GaN on each of the first silicon region and the second silicon region comprises fabricating through epitaxial growth a GaN layer on each of the first silicon region and the second silicon region; fabricating through epitaxial growth an aluminum gallium nitride (AlGaN) layer on each of the GaN layers; fabricating through epitaxial growth a polarization modulation layer above each of the AlGaN layers; patterning the polarization modulation layers; and -4- NAI-1502598161v1 fabricating through deposition and polishing a passivation layer above each of the isolated first silicon region and the isolated second silicon region.
The method of claim 8 wherein fabricating the body connection for each of the first transistor circuit and the second transistor circuit comprises: applying a second mask above the wafer; etching a first via hole through the second mask and the first active area of each of the first transistor circuit and the second transistor circuit to the isolated first silicon region, the first via hole having a first sidewall layer above the insulator; etching a second via hole through the second mask and the second active area of the second transistor circuit to the isolated second silicon region, the second via hole having a second sidewall; respectively coating the via hole sidewall first and second sidewalls with insulator material; and after the coating, implanting metal material into each of the first and second via holes hole in each of the first transistor circuit and the second transistor circuit to form a respective contact to the isolated first and second silicon regions in each of the first transistor circuit and the second transistor circuit.
Claims 11 -16. canceled
canceled
canceled
canceled
canceled
-5- NAI-1502598161v1 canceled
A method of fabricating gallium nitride (GaN) transistors on a silicon on insulator (SO I) wafer with a GaN transistor in a first transistor circuit having its substrate isolated from the substrate of a transistor in a second transistor circuit, the method comprising: fabricating an isolated first silicon region and an isolated second silicon region on a SO I wafer comprising an insulator layer and a silicon layer disposed over the insulator layer, each of the first silicon region and the second silicon region bounded on its sides by a trench filled with insulator material so as to define a first cavity over the isolated first silicon region and a second cavity over the isolated second silicon region; fabricating [[an]] a first active area within the first cavity over the isolated on each of the first silicon region and fabricating a second active area within the second cavity over the isolated [[the]] second silicon region through epitaxial growth operations to respectively form the first transistor circuit and the second transistor circuit, the first active area of the first silicon region comprising a first GaN layer; and fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit.
The method of claim 17 wherein fabricating [[an]] the isolated first silicon region and an isolated second silicon region on the SO I wafer comprises: applying a mask to the silicon layer above the insulator on the SOI wafer; etching the mask and the silicon layer to an etch stop at the insulator layer to form a silicon trench in the silicon layer separating the isolated first and second silicon regions from one another; filling the trench with insulator material; and removing the mask to define the first cavity and the second cavity.
The method of claim 17 wherein fabricating [[an]] the first active area comprising GaN comprises [[:]] fabricating through epitaxial growth a first GaN layer on each of the isolated first silicon region and the second silicon region; fabricating through epitaxial growth [[an]] a first aluminum gallium nitride (AlGaN) layer on each of the first GaN layer layers; and -6-NAI-1502598161v1 wherein fabricating the second active area comprises fabricating through epitaxial growth a second GaN layer on the isolated second silicon region and fabricating through epitaxial growth a second AlGaN layer on the second GaN layer fabricating through epitaxial growth a polarization modulation layer above each of the AlGaN layers; patterning the polarization modulation layers; and fabricating through deposition and polishing a passivation layer above each of the first silicon region and the second silicon region.
The method of claim 17 wherein fabricating the body connection for each of the first transistor circuit and the second transistor circuit comprises: applying a mask above the wafer; etching a first via hole through the mask and the first active area of each of the each of the first transistor circuit and the second transistor circuit to the isolated first silicon region, the first via hole having a first sidewall layer above the insulator; etching a second via hole through the mask and the second active area of the second transistor circuit to the isolated second silicon region, the second via hole having a second sidewall; respectively coating the via hole sidewall first and second sidewalls with insulator material; and after the coating, implanting metal material into the each of the first and second via holes hole in each of the first transistor circuit and the second transistor circuit to form a respective contact to the isolated first and second silicon regions in each of the first transistor circuit and the second transistor circuit.
A method of fabricating a semiconductor device on a silicon on insulator (SO I) wafer comprising a silicon layer and an insulator layer, the method comprising: fabricating a first transistor circuit on an isolated first silicon region and a second transistor circuit on an isolated second silicon region, each of the first transistor circuit and the second transistor circuit having an active region comprising gallium nitride (GaN) material -7- NAI-1502598161v1 above its respective isolated silicon region, each of the first and second isolated silicon regions each formed from the silicon layer and separated from one another by a trench above the insulator layer on the SOI wafer; filling [[a]] t he trench with an insulator that bounds [[the]] respective sides of the isolated first and second silicon regions, the sides of the active region of the first transistor circuit, and the sides of the active region of the second transistor circuit wherein such that the first silicon region and the first transistor circuit are is isolated from the second silicon region and the second transistor circuit by the insulator material and a cavity respectively is disposed over each of the first and second silicon regions; after filling the trench, respectively fabricating first and second active regions comprising first and second GaN layers within the cavities to form the first transistor circuit and the second transistor circuit to form the first transistor circuit and the second transistor circuit; and providing a respective body contact connection point for each of the first transistor circuit and the second transistor circuit.
The method of claim 21 wherein respectively fabricating the active regions of each of the first transistor circuit and the second transistor circuit comprises a silicon layer, comprises respectively fabricating, within the cavities, a transition layer above the silicon layer, a GaN layer above the transition layer, and an aluminum gallium nitride (AlGaN) layer above the GaN layer.
The method of claim 21 wherein further comprising forming the isolated first silicon region and the isolated second silicon region [[by]] are fabricated using steps comprising: applying a mask above the silicon layer on the SOI wafer; etching the mask and a portion of the silicon layer to an etch stop at the insulator layer of the SOI wafer to form a silicon the trench; filling the trench with insulator material; and removing the mask to form the cavities being.
The method of claim 21 wherein providing [[a]] the respective body contact connection point for each of the first transistor circuit and the second transistor circuit comprises: providing a through-GaN-via (TGV) hole in the active region of the respective transistor circuit to the respective isolated silicon region that is filled with metal material forming a contact to the respective isolated silicon region.
Layer stacks claimed or described, ordered top of device to substrate.
GaN/Si HEMT on SOI wafer with substrate isolation
Materials described outside the worked examples.
gallium nitride
GaN
insulator material (trench fill)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a block diagram of an example semiconductor device that is fabricated on a silicon on insulator (SOI) wafer and that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,793,389Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a block diagram of an example semiconductor device that is fabricated on a silicon on insulator (SOI) wafer and that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figure 2 is a process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figure 3 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. 1 TSMC No. 2016-0105/Attorney Docket No. 181877-625231
Figure 4 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figures 5A, 5B, 5C, 5D, and 5E provide cross-sectional views of an example semiconductor device during various stages of fabrication according to operations specified in
Figure 6 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figures 7A, 7B, 7C, and 7D provide cross-sectional views of an example semiconductor device during various stages of fabrication according to operations specified in
Figure 8 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figure 9 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figures 10 A, 10 B, 10 C, and 10 D provide cross-sectional views of an example semiconductor device during various stages of fabrication according to operations specified in
Figure 11 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. 2 TSMC No. 2016-0105/Attorney Docket No. 181877-625231 [0
Figures 12A, 12B, 12C, 12D, 12E, 12F, and 12G provide cross-sectional views of an example semiconductor device during various stages of fabrication according to operations specified in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device having an isolated first transistor circuit and an isolated second transistor circuit, the method comprising: providing a silicon on insulator (SO I) wafer comprising an insulator layer and a silicon layer disposed over the insulator layer; applying a first mask to the silicon layer; etching the first mask and the silicon layer to an etch stop at the insulator to form fabricating an isolated first silicon region and an isolated second silicon region each disposed over the insulator layer, the isolated first and second silicon regions being separated from one another by a trench; on the SOI wafer, filling the trench with insulator material so as to bound each of the first silicon region and the second silicon region bounded on its respective sides by the a trench filled with insulator material; after filling the trench, removing the first mask to define a first cavity over the isolated first silicon region and a second cavity over the isolated second silicon region; after removing the first mask, fabricating [[an]] a first active area comprising gallium nitride (GaN) on each of within the first cavity over the isolated first silicon region and a second active area comprising GaN within the second cavity over the isolated second silicon region to respectively form the first transistor circuit and the second transistor circuit; and fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit.
-2- NAI-1502598161v1 3. The method of claim 1 wherein fabricating [[an]] the first active area comprising GaN on each of the first silicon region and the second silicon region comprises fabricating through epitaxial growth a f i rst GaN layer on each of the isolated first silicon region and the second silicon region; fabricating through epitaxial growth [[an]] a first aluminum gallium nitride (AlGaN) layer on each of the first GaN layers laeyr; and wherein fabricating the second active area comprises fabricating through epitaxial growth a second GaN layer on the isolated second silicon region and fabricating through epitaxial growth a second AlGaN layer on the second GaN layer fabricating through epitaxial growth a polarization modulation layer above each of the AlGaN layers; patterning the polarization modulation layers; and fabricating through deposition and polishing a passivation layer above each of the first silicon region and the second silicon region. currently amended
The method of claim 1 wherein the fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit comprises: fabricating the body connection for each of the first transistor circuit and the second transistor circuit; and fabricating the source, drain, and gate connection for each of the first transistor circuit and the second transistor circuit after fabricating the body connection.
The method of claim 1 wherein fabricating the body connection for each of the first transistor circuit and the second transistor circuit comprises: applying a second mask above the wafer; etching a first via hole through the second mask and the first active area of each of the first transistor circuit and the second transistor circuit to the isolated first silicon region, the first via hole having a first sidewall layer above the insulator; etching a second via hole through the second mask and the second active area of the second transistor circuit to the isolated second silicon region, the second via hole having a second sidewall: -3- NAI-1502598161v1 respectively coating the via hole sidewall first and second sidewalls with insulator material; and after the coating, implanting metal material into each of the first and second via holes hole in each of the first transistor circuit and the second transistor circuit to form a respective contact to the isolated first and second silicon regions in each of the first transistor circuit and the second transistor circuit.
The method of claim 1 wherein fabricating the source, drain, and gate connections for each of the first transistor circuit and the second transistor circuit comprises: applying a second mask above the wafer; patterning the second mask for contact holes; depositing metal material into the contact holes to form contacts for the source, drain, and gate connections for each of the first transistor circuit and the second transistor circuit; and removing the second mask.
The method of claim [[2]] 1, further comprising wherein fabricating an active area comprising GaN on each of the first silicon region and the second silicon region comprises fabricating through epitaxial growth a GaN layer on each of the first silicon region and the second silicon region; fabricating through epitaxial growth an aluminum gallium nitride (AlGaN) layer on each of the GaN layers; fabricating through epitaxial growth a polarization modulation layer above each of the AlGaN layers; patterning the polarization modulation layers; and -4- NAI-1502598161v1 fabricating through deposition and polishing a passivation layer above each of the isolated first silicon region and the isolated second silicon region.
The method of claim 8 wherein fabricating the body connection for each of the first transistor circuit and the second transistor circuit comprises: applying a second mask above the wafer; etching a first via hole through the second mask and the first active area of each of the first transistor circuit and the second transistor circuit to the isolated first silicon region, the first via hole having a first sidewall layer above the insulator; etching a second via hole through the second mask and the second active area of the second transistor circuit to the isolated second silicon region, the second via hole having a second sidewall; respectively coating the via hole sidewall first and second sidewalls with insulator material; and after the coating, implanting metal material into each of the first and second via holes hole in each of the first transistor circuit and the second transistor circuit to form a respective contact to the isolated first and second silicon regions in each of the first transistor circuit and the second transistor circuit.
Claims 11 -16. canceled
canceled
canceled
canceled
canceled
-5- NAI-1502598161v1 canceled
A method of fabricating gallium nitride (GaN) transistors on a silicon on insulator (SO I) wafer with a GaN transistor in a first transistor circuit having its substrate isolated from the substrate of a transistor in a second transistor circuit, the method comprising: fabricating an isolated first silicon region and an isolated second silicon region on a SO I wafer comprising an insulator layer and a silicon layer disposed over the insulator layer, each of the first silicon region and the second silicon region bounded on its sides by a trench filled with insulator material so as to define a first cavity over the isolated first silicon region and a second cavity over the isolated second silicon region; fabricating [[an]] a first active area within the first cavity over the isolated on each of the first silicon region and fabricating a second active area within the second cavity over the isolated [[the]] second silicon region through epitaxial growth operations to respectively form the first transistor circuit and the second transistor circuit, the first active area of the first silicon region comprising a first GaN layer; and fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit.
The method of claim 17 wherein fabricating [[an]] the isolated first silicon region and an isolated second silicon region on the SO I wafer comprises: applying a mask to the silicon layer above the insulator on the SOI wafer; etching the mask and the silicon layer to an etch stop at the insulator layer to form a silicon trench in the silicon layer separating the isolated first and second silicon regions from one another; filling the trench with insulator material; and removing the mask to define the first cavity and the second cavity.
The method of claim 17 wherein fabricating [[an]] the first active area comprising GaN comprises [[:]] fabricating through epitaxial growth a first GaN layer on each of the isolated first silicon region and the second silicon region; fabricating through epitaxial growth [[an]] a first aluminum gallium nitride (AlGaN) layer on each of the first GaN layer layers; and -6-NAI-1502598161v1 wherein fabricating the second active area comprises fabricating through epitaxial growth a second GaN layer on the isolated second silicon region and fabricating through epitaxial growth a second AlGaN layer on the second GaN layer fabricating through epitaxial growth a polarization modulation layer above each of the AlGaN layers; patterning the polarization modulation layers; and fabricating through deposition and polishing a passivation layer above each of the first silicon region and the second silicon region.
The method of claim 17 wherein fabricating the body connection for each of the first transistor circuit and the second transistor circuit comprises: applying a mask above the wafer; etching a first via hole through the mask and the first active area of each of the each of the first transistor circuit and the second transistor circuit to the isolated first silicon region, the first via hole having a first sidewall layer above the insulator; etching a second via hole through the mask and the second active area of the second transistor circuit to the isolated second silicon region, the second via hole having a second sidewall; respectively coating the via hole sidewall first and second sidewalls with insulator material; and after the coating, implanting metal material into the each of the first and second via holes hole in each of the first transistor circuit and the second transistor circuit to form a respective contact to the isolated first and second silicon regions in each of the first transistor circuit and the second transistor circuit.
A method of fabricating a semiconductor device on a silicon on insulator (SO I) wafer comprising a silicon layer and an insulator layer, the method comprising: fabricating a first transistor circuit on an isolated first silicon region and a second transistor circuit on an isolated second silicon region, each of the first transistor circuit and the second transistor circuit having an active region comprising gallium nitride (GaN) material -7- NAI-1502598161v1 above its respective isolated silicon region, each of the first and second isolated silicon regions each formed from the silicon layer and separated from one another by a trench above the insulator layer on the SOI wafer; filling [[a]] t he trench with an insulator that bounds [[the]] respective sides of the isolated first and second silicon regions, the sides of the active region of the first transistor circuit, and the sides of the active region of the second transistor circuit wherein such that the first silicon region and the first transistor circuit are is isolated from the second silicon region and the second transistor circuit by the insulator material and a cavity respectively is disposed over each of the first and second silicon regions; after filling the trench, respectively fabricating first and second active regions comprising first and second GaN layers within the cavities to form the first transistor circuit and the second transistor circuit to form the first transistor circuit and the second transistor circuit; and providing a respective body contact connection point for each of the first transistor circuit and the second transistor circuit.
The method of claim 21 wherein respectively fabricating the active regions of each of the first transistor circuit and the second transistor circuit comprises a silicon layer, comprises respectively fabricating, within the cavities, a transition layer above the silicon layer, a GaN layer above the transition layer, and an aluminum gallium nitride (AlGaN) layer above the GaN layer.
The method of claim 21 wherein further comprising forming the isolated first silicon region and the isolated second silicon region [[by]] are fabricated using steps comprising: applying a mask above the silicon layer on the SOI wafer; etching the mask and a portion of the silicon layer to an etch stop at the insulator layer of the SOI wafer to form a silicon the trench; filling the trench with insulator material; and removing the mask to form the cavities being.
The method of claim 21 wherein providing [[a]] the respective body contact connection point for each of the first transistor circuit and the second transistor circuit comprises: providing a through-GaN-via (TGV) hole in the active region of the respective transistor circuit to the respective isolated silicon region that is filled with metal material forming a contact to the respective isolated silicon region.
Layer stacks claimed or described, ordered top of device to substrate.
GaN/Si HEMT on SOI wafer with substrate isolation
Materials described outside the worked examples.
gallium nitride
GaN
insulator material (trench fill)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a block diagram of an example semiconductor device that is fabricated on a silicon on insulator (SOI) wafer and that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,793,389Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a block diagram of an example semiconductor device that is fabricated on a silicon on insulator (SOI) wafer and that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figure 2 is a process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figure 3 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. 1 TSMC No. 2016-0105/Attorney Docket No. 181877-625231
Figure 4 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figures 5A, 5B, 5C, 5D, and 5E provide cross-sectional views of an example semiconductor device during various stages of fabrication according to operations specified in
Figure 6 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figures 7A, 7B, 7C, and 7D provide cross-sectional views of an example semiconductor device during various stages of fabrication according to operations specified in
Figure 8 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figure 9 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figures 10 A, 10 B, 10 C, and 10 D provide cross-sectional views of an example semiconductor device during various stages of fabrication according to operations specified in
Figure 11 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. 2 TSMC No. 2016-0105/Attorney Docket No. 181877-625231 [0
Figures 12A, 12B, 12C, 12D, 12E, 12F, and 12G provide cross-sectional views of an example semiconductor device during various stages of fabrication according to operations specified in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device having an isolated first transistor circuit and an isolated second transistor circuit, the method comprising: providing a silicon on insulator (SO I) wafer comprising an insulator layer and a silicon layer disposed over the insulator layer; applying a first mask to the silicon layer; etching the first mask and the silicon layer to an etch stop at the insulator to form fabricating an isolated first silicon region and an isolated second silicon region each disposed over the insulator layer, the isolated first and second silicon regions being separated from one another by a trench; on the SOI wafer, filling the trench with insulator material so as to bound each of the first silicon region and the second silicon region bounded on its respective sides by the a trench filled with insulator material; after filling the trench, removing the first mask to define a first cavity over the isolated first silicon region and a second cavity over the isolated second silicon region; after removing the first mask, fabricating [[an]] a first active area comprising gallium nitride (GaN) on each of within the first cavity over the isolated first silicon region and a second active area comprising GaN within the second cavity over the isolated second silicon region to respectively form the first transistor circuit and the second transistor circuit; and fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit.
-2- NAI-1502598161v1 3. The method of claim 1 wherein fabricating [[an]] the first active area comprising GaN on each of the first silicon region and the second silicon region comprises fabricating through epitaxial growth a f i rst GaN layer on each of the isolated first silicon region and the second silicon region; fabricating through epitaxial growth [[an]] a first aluminum gallium nitride (AlGaN) layer on each of the first GaN layers laeyr; and wherein fabricating the second active area comprises fabricating through epitaxial growth a second GaN layer on the isolated second silicon region and fabricating through epitaxial growth a second AlGaN layer on the second GaN layer fabricating through epitaxial growth a polarization modulation layer above each of the AlGaN layers; patterning the polarization modulation layers; and fabricating through deposition and polishing a passivation layer above each of the first silicon region and the second silicon region. currently amended
The method of claim 1 wherein the fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit comprises: fabricating the body connection for each of the first transistor circuit and the second transistor circuit; and fabricating the source, drain, and gate connection for each of the first transistor circuit and the second transistor circuit after fabricating the body connection.
The method of claim 1 wherein fabricating the body connection for each of the first transistor circuit and the second transistor circuit comprises: applying a second mask above the wafer; etching a first via hole through the second mask and the first active area of each of the first transistor circuit and the second transistor circuit to the isolated first silicon region, the first via hole having a first sidewall layer above the insulator; etching a second via hole through the second mask and the second active area of the second transistor circuit to the isolated second silicon region, the second via hole having a second sidewall: -3- NAI-1502598161v1 respectively coating the via hole sidewall first and second sidewalls with insulator material; and after the coating, implanting metal material into each of the first and second via holes hole in each of the first transistor circuit and the second transistor circuit to form a respective contact to the isolated first and second silicon regions in each of the first transistor circuit and the second transistor circuit.
The method of claim 1 wherein fabricating the source, drain, and gate connections for each of the first transistor circuit and the second transistor circuit comprises: applying a second mask above the wafer; patterning the second mask for contact holes; depositing metal material into the contact holes to form contacts for the source, drain, and gate connections for each of the first transistor circuit and the second transistor circuit; and removing the second mask.
The method of claim [[2]] 1, further comprising wherein fabricating an active area comprising GaN on each of the first silicon region and the second silicon region comprises fabricating through epitaxial growth a GaN layer on each of the first silicon region and the second silicon region; fabricating through epitaxial growth an aluminum gallium nitride (AlGaN) layer on each of the GaN layers; fabricating through epitaxial growth a polarization modulation layer above each of the AlGaN layers; patterning the polarization modulation layers; and -4- NAI-1502598161v1 fabricating through deposition and polishing a passivation layer above each of the isolated first silicon region and the isolated second silicon region.
The method of claim 8 wherein fabricating the body connection for each of the first transistor circuit and the second transistor circuit comprises: applying a second mask above the wafer; etching a first via hole through the second mask and the first active area of each of the first transistor circuit and the second transistor circuit to the isolated first silicon region, the first via hole having a first sidewall layer above the insulator; etching a second via hole through the second mask and the second active area of the second transistor circuit to the isolated second silicon region, the second via hole having a second sidewall; respectively coating the via hole sidewall first and second sidewalls with insulator material; and after the coating, implanting metal material into each of the first and second via holes hole in each of the first transistor circuit and the second transistor circuit to form a respective contact to the isolated first and second silicon regions in each of the first transistor circuit and the second transistor circuit.
Claims 11 -16. canceled
canceled
canceled
canceled
canceled
-5- NAI-1502598161v1 canceled
A method of fabricating gallium nitride (GaN) transistors on a silicon on insulator (SO I) wafer with a GaN transistor in a first transistor circuit having its substrate isolated from the substrate of a transistor in a second transistor circuit, the method comprising: fabricating an isolated first silicon region and an isolated second silicon region on a SO I wafer comprising an insulator layer and a silicon layer disposed over the insulator layer, each of the first silicon region and the second silicon region bounded on its sides by a trench filled with insulator material so as to define a first cavity over the isolated first silicon region and a second cavity over the isolated second silicon region; fabricating [[an]] a first active area within the first cavity over the isolated on each of the first silicon region and fabricating a second active area within the second cavity over the isolated [[the]] second silicon region through epitaxial growth operations to respectively form the first transistor circuit and the second transistor circuit, the first active area of the first silicon region comprising a first GaN layer; and fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit.
The method of claim 17 wherein fabricating [[an]] the isolated first silicon region and an isolated second silicon region on the SO I wafer comprises: applying a mask to the silicon layer above the insulator on the SOI wafer; etching the mask and the silicon layer to an etch stop at the insulator layer to form a silicon trench in the silicon layer separating the isolated first and second silicon regions from one another; filling the trench with insulator material; and removing the mask to define the first cavity and the second cavity.
The method of claim 17 wherein fabricating [[an]] the first active area comprising GaN comprises [[:]] fabricating through epitaxial growth a first GaN layer on each of the isolated first silicon region and the second silicon region; fabricating through epitaxial growth [[an]] a first aluminum gallium nitride (AlGaN) layer on each of the first GaN layer layers; and -6-NAI-1502598161v1 wherein fabricating the second active area comprises fabricating through epitaxial growth a second GaN layer on the isolated second silicon region and fabricating through epitaxial growth a second AlGaN layer on the second GaN layer fabricating through epitaxial growth a polarization modulation layer above each of the AlGaN layers; patterning the polarization modulation layers; and fabricating through deposition and polishing a passivation layer above each of the first silicon region and the second silicon region.
The method of claim 17 wherein fabricating the body connection for each of the first transistor circuit and the second transistor circuit comprises: applying a mask above the wafer; etching a first via hole through the mask and the first active area of each of the each of the first transistor circuit and the second transistor circuit to the isolated first silicon region, the first via hole having a first sidewall layer above the insulator; etching a second via hole through the mask and the second active area of the second transistor circuit to the isolated second silicon region, the second via hole having a second sidewall; respectively coating the via hole sidewall first and second sidewalls with insulator material; and after the coating, implanting metal material into the each of the first and second via holes hole in each of the first transistor circuit and the second transistor circuit to form a respective contact to the isolated first and second silicon regions in each of the first transistor circuit and the second transistor circuit.
A method of fabricating a semiconductor device on a silicon on insulator (SO I) wafer comprising a silicon layer and an insulator layer, the method comprising: fabricating a first transistor circuit on an isolated first silicon region and a second transistor circuit on an isolated second silicon region, each of the first transistor circuit and the second transistor circuit having an active region comprising gallium nitride (GaN) material -7- NAI-1502598161v1 above its respective isolated silicon region, each of the first and second isolated silicon regions each formed from the silicon layer and separated from one another by a trench above the insulator layer on the SOI wafer; filling [[a]] t he trench with an insulator that bounds [[the]] respective sides of the isolated first and second silicon regions, the sides of the active region of the first transistor circuit, and the sides of the active region of the second transistor circuit wherein such that the first silicon region and the first transistor circuit are is isolated from the second silicon region and the second transistor circuit by the insulator material and a cavity respectively is disposed over each of the first and second silicon regions; after filling the trench, respectively fabricating first and second active regions comprising first and second GaN layers within the cavities to form the first transistor circuit and the second transistor circuit to form the first transistor circuit and the second transistor circuit; and providing a respective body contact connection point for each of the first transistor circuit and the second transistor circuit.
The method of claim 21 wherein respectively fabricating the active regions of each of the first transistor circuit and the second transistor circuit comprises a silicon layer, comprises respectively fabricating, within the cavities, a transition layer above the silicon layer, a GaN layer above the transition layer, and an aluminum gallium nitride (AlGaN) layer above the GaN layer.
The method of claim 21 wherein further comprising forming the isolated first silicon region and the isolated second silicon region [[by]] are fabricated using steps comprising: applying a mask above the silicon layer on the SOI wafer; etching the mask and a portion of the silicon layer to an etch stop at the insulator layer of the SOI wafer to form a silicon the trench; filling the trench with insulator material; and removing the mask to form the cavities being.
The method of claim 21 wherein providing [[a]] the respective body contact connection point for each of the first transistor circuit and the second transistor circuit comprises: providing a through-GaN-via (TGV) hole in the active region of the respective transistor circuit to the respective isolated silicon region that is filled with metal material forming a contact to the respective isolated silicon region.
Layer stacks claimed or described, ordered top of device to substrate.
GaN/Si HEMT on SOI wafer with substrate isolation
Materials described outside the worked examples.
gallium nitride
GaN
insulator material (trench fill)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a block diagram of an example semiconductor device that is fabricated on a silicon on insulator (SOI) wafer and that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Related documents with shared materials, methods, properties, or citations.
aluminum gallium nitride
AlGaN
metal material
inter-layer-dielectric material
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
aluminum nitride
AlN
magnesium oxide
MgO
Figure 2 is a process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figure 3 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. 1 TSMC No. 2016-0105/Attorney Docket No. 181877-625231
Figure 4 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figure 6 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figure 8 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figure 9 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figure 11 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. 2 TSMC No. 2016-0105/Attorney Docket No. 181877-625231 [0
N-CHANNEL GALLIUM NITRIDE TRANSISTORS
GALLIUM NITRIDE VOLTAGE REGULATOR
aluminum gallium nitride
AlGaN
metal material
inter-layer-dielectric material
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
aluminum nitride
AlN
magnesium oxide
MgO
Figure 2 is a process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figure 3 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. 1 TSMC No. 2016-0105/Attorney Docket No. 181877-625231
Figure 4 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figure 6 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figure 8 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figure 9 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figure 11 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. 2 TSMC No. 2016-0105/Attorney Docket No. 181877-625231 [0
N-CHANNEL GALLIUM NITRIDE TRANSISTORS
GALLIUM NITRIDE VOLTAGE REGULATOR
aluminum gallium nitride
AlGaN
metal material
inter-layer-dielectric material
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
aluminum nitride
AlN
magnesium oxide
MgO
Figure 2 is a process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figure 3 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. 1 TSMC No. 2016-0105/Attorney Docket No. 181877-625231
Figure 4 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figure 6 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figure 8 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figure 9 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figure 11 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. 2 TSMC No. 2016-0105/Attorney Docket No. 181877-625231 [0
N-CHANNEL GALLIUM NITRIDE TRANSISTORS
GALLIUM NITRIDE VOLTAGE REGULATOR
aluminum gallium nitride
AlGaN
metal material
inter-layer-dielectric material
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
aluminum nitride
AlN
magnesium oxide
MgO
Figure 2 is a process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figure 3 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. 1 TSMC No. 2016-0105/Attorney Docket No. 181877-625231
Figure 4 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments.
Figure 6 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figure 8 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figure 9 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. [0
Figure 11 is another process flow chart illustrating an example method of fabricating a semiconductor device that achieves isolation of GaN/Si transistors, in accordance with some embodiments. 2 TSMC No. 2016-0105/Attorney Docket No. 181877-625231 [0
N-CHANNEL GALLIUM NITRIDE TRANSISTORS