Patent
US 8,729,565LAYOUT DESIGN FOR A HIGH POWER, GaN-BASED FET
LinLin Liu
US
Copyright © 2026 Matter42. All rights reserved.
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US 8,729,565Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-section through two GaN-based FET cells constructed in accordance with the present invention. As shown, a heterojunction structure is formed …
FIG. 2. In some embodiments of the invention the source and drain electrodes 50 and 70 extend about 2 -3 microns beyond the edge of the mesa. The gate …
FIG. 3, which is a cross-sectional view taken along line A- A in
FIG. 4. A source pad via 158 is formed in the dielectric layer 155. The source pad 150 is formed in and above the source pad via 158 and electrically contacts …
FIG. 5 is an even more greatly expanded plan view of the GaN-based FET showing two gate pads 120, source pad 150 and drain pad 162.
FIG. 6 is cross-sectional view of the FET taken along line C- C in
FIG. 7 is cross-sectional view of the FET taken along line D-D in
FIG. 8.
FIG. 9. One advantage of the embodiments of the invention shown in FIG s. 8-11 is that a relatively low spreading resistance can be achieved between the …
FIG. 10 is cross-section view of a FET through line E-E in
FIG. 11 is cross-sectional view of a FET through line F-F in
FIG. 12(b) shows the dependence of the breakdown voltage on the gate-to-drain spacing Lgd. These results, based on simulations, show that a low on-resistance …
FIG. 13 shows the dependence of the cut-off frequency of the device on the gate- to-drain spacing Lgd f o r two different gate lengths Lg. These simulated …
FIG. 14 is a plan view of an alternative embodiment of a FET layout in which there are two sets of fingers 145 instead of the single set of fingers shown in …
FIG. 15 shows yet another embodiment similar to
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comp nsing a heterostructure that in cludes a channel layer extend ing m a longitud in al direction, a first portion of the channel layer be in g located on a mesa and a second portion of the channel layer bein g located off the mesa, a se n es of m terdigitated gate, source and dra in electrodes extend ing m the longitud inal direction and be in g disposed over the first portion of the channel layer located on the mesa, the source and dra in electrodes extend ing m the longitud in al direction beyond an edge of the mesa and extend in g over the second portion of the channel layer, the gate electrodes extend in g along a sidewall of the mesa, a source pad located off the mesa, a conductive source in terconnect hav in g a first portion elect ri cally connected to one of the source electrodes and a second portion elect n cally connected to the source pad, a gate pad located off the mesa and overlapp in g the source pad at least m part, and a conductive gate in terconnect hav in g a first portion elect n cally connected to a portion of the gate electrode extend in g along the mesa sidewall, the conductive gate in terconnect hav in g a second portion elect ri cally commu ni cat in g with the gate pad
The semiconductor device of claim 1 further comp nsing a first dielect ric layer disposed under the conductive source in terconnect, and a source pad via formed m the first dielect nc layer, the source pad be in g located formed m the source pad via
The semiconductor device of claim 1 where in the conductive gate connect st ri p at least partially overlaps the conductive source in terconnect
The semiconductor device of claim 1 where in the channel layer comp ri ses a group III nitn de semiconductor mate nal
The semiconductor device of claim 1 where in the channel layer comp n ses GaN
The semiconductor device of claim 1 where in one of the gate electrodes has a length of about 3 microns
The semiconductor device of claim 1 where in the source electrodes extend beyond the edge of the mesa by about 2-3 microns
The semiconductor device of claim 1 where in the source, gate and dra m electrodes extend m the longitud in al direction between about 250 microns and 1mm 4 Sen al No 13/965,87 1
The semiconductor device of claim 1 where in a distance between one of the gate electrodes and one of the dra m electrodes is less than about 15 microns
The FET of claim 1 where in at least one of the conductive gate connect strip at least partially overlaps at least one of the conductive source in terconnects 6
A FET, comp rising a substrate, a channel layer disposed on the substrate and a ba rn er layer disposed over the channel layer, a plura li ty of source, gate and dra m electrodes located over the bar ri er layer and extend ing m a longitud in al direction thereon, where in a portion of the channel and bar ri er layers define a mesa extend ing m the longitud in al direction and the source and dra m electrodes extend beyond an edge of the mesa and where in the gate electrodes extends along an edge sidewall of the mesa, a plura li ty of conductive source in terconnects each hav in g a first end elect ri cally connected to one of the source electrodes, a first dielect ric layer disposed over the conductive source in terconnect, a plura li ty of conductive gate nodes, each of the conductive gate nodes elect n cally connect in g the portions of a pair of adjacent gate electrodes extend in g along the sidewall of the mesa, a plura li ty of gate pads disposed on the first dielect nc layer adjacent the mesa, a plura li ty of conductive gate connect st ri ps m contact with the conductive gate nodes, said conductive gate connect st ri ps each be ing m elect n cal contact with one of the gate pads, a source via formed m the first dielect nc layer, and a source pad formed m the source via, the conductive source in terconnects each hav in g a second end m elect ri cal contact with the source pad
The FET of claim 13 further comp nsin g at least one set of finger arrays which in cludes one of the source, gate and dra m electrodes 5 Seri al No 13/965,87 1
The FET of claim 13 fu rt her comp risin g a gate via formed m the first dielectric layer, one of the conductive gate connect strips be in g connected to one of the gate nodes through the gate via
The FET of claim 13 where in the gate pads and the source pad do not overlap one another
The FET of claim 13 where in one of the gate pads and the source pad overlap at least m part
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based semiconductor device (heterostructure FET with mesa, interdigitated electrodes)
GaN-based FET with finger arrays, mesa, source/gate/drain interconnects
Materials described outside the worked examples.
heterostructure channel layer
group III nitride semiconductor
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-section through two GaN-based FET cells constructed in accordance with the present invention. As shown, a heterojunction structure is formed …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 250000–1000000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,729,565Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-section through two GaN-based FET cells constructed in accordance with the present invention. As shown, a heterojunction structure is formed …
FIG. 2. In some embodiments of the invention the source and drain electrodes 50 and 70 extend about 2 -3 microns beyond the edge of the mesa. The gate …
FIG. 3, which is a cross-sectional view taken along line A- A in
FIG. 4. A source pad via 158 is formed in the dielectric layer 155. The source pad 150 is formed in and above the source pad via 158 and electrically contacts …
FIG. 5 is an even more greatly expanded plan view of the GaN-based FET showing two gate pads 120, source pad 150 and drain pad 162.
FIG. 6 is cross-sectional view of the FET taken along line C- C in
FIG. 7 is cross-sectional view of the FET taken along line D-D in
FIG. 8.
FIG. 9. One advantage of the embodiments of the invention shown in FIG s. 8-11 is that a relatively low spreading resistance can be achieved between the …
FIG. 10 is cross-section view of a FET through line E-E in
FIG. 11 is cross-sectional view of a FET through line F-F in
FIG. 12(b) shows the dependence of the breakdown voltage on the gate-to-drain spacing Lgd. These results, based on simulations, show that a low on-resistance …
FIG. 13 shows the dependence of the cut-off frequency of the device on the gate- to-drain spacing Lgd f o r two different gate lengths Lg. These simulated …
FIG. 14 is a plan view of an alternative embodiment of a FET layout in which there are two sets of fingers 145 instead of the single set of fingers shown in …
FIG. 15 shows yet another embodiment similar to
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comp nsing a heterostructure that in cludes a channel layer extend ing m a longitud in al direction, a first portion of the channel layer be in g located on a mesa and a second portion of the channel layer bein g located off the mesa, a se n es of m terdigitated gate, source and dra in electrodes extend ing m the longitud inal direction and be in g disposed over the first portion of the channel layer located on the mesa, the source and dra in electrodes extend ing m the longitud in al direction beyond an edge of the mesa and extend in g over the second portion of the channel layer, the gate electrodes extend in g along a sidewall of the mesa, a source pad located off the mesa, a conductive source in terconnect hav in g a first portion elect ri cally connected to one of the source electrodes and a second portion elect n cally connected to the source pad, a gate pad located off the mesa and overlapp in g the source pad at least m part, and a conductive gate in terconnect hav in g a first portion elect n cally connected to a portion of the gate electrode extend in g along the mesa sidewall, the conductive gate in terconnect hav in g a second portion elect ri cally commu ni cat in g with the gate pad
The semiconductor device of claim 1 further comp nsing a first dielect ric layer disposed under the conductive source in terconnect, and a source pad via formed m the first dielect nc layer, the source pad be in g located formed m the source pad via
The semiconductor device of claim 1 where in the conductive gate connect st ri p at least partially overlaps the conductive source in terconnect
The semiconductor device of claim 1 where in the channel layer comp ri ses a group III nitn de semiconductor mate nal
The semiconductor device of claim 1 where in the channel layer comp n ses GaN
The semiconductor device of claim 1 where in one of the gate electrodes has a length of about 3 microns
The semiconductor device of claim 1 where in the source electrodes extend beyond the edge of the mesa by about 2-3 microns
The semiconductor device of claim 1 where in the source, gate and dra m electrodes extend m the longitud in al direction between about 250 microns and 1mm 4 Sen al No 13/965,87 1
The semiconductor device of claim 1 where in a distance between one of the gate electrodes and one of the dra m electrodes is less than about 15 microns
The FET of claim 1 where in at least one of the conductive gate connect strip at least partially overlaps at least one of the conductive source in terconnects 6
A FET, comp rising a substrate, a channel layer disposed on the substrate and a ba rn er layer disposed over the channel layer, a plura li ty of source, gate and dra m electrodes located over the bar ri er layer and extend ing m a longitud in al direction thereon, where in a portion of the channel and bar ri er layers define a mesa extend ing m the longitud in al direction and the source and dra m electrodes extend beyond an edge of the mesa and where in the gate electrodes extends along an edge sidewall of the mesa, a plura li ty of conductive source in terconnects each hav in g a first end elect ri cally connected to one of the source electrodes, a first dielect ric layer disposed over the conductive source in terconnect, a plura li ty of conductive gate nodes, each of the conductive gate nodes elect n cally connect in g the portions of a pair of adjacent gate electrodes extend in g along the sidewall of the mesa, a plura li ty of gate pads disposed on the first dielect nc layer adjacent the mesa, a plura li ty of conductive gate connect st ri ps m contact with the conductive gate nodes, said conductive gate connect st ri ps each be ing m elect n cal contact with one of the gate pads, a source via formed m the first dielect nc layer, and a source pad formed m the source via, the conductive source in terconnects each hav in g a second end m elect ri cal contact with the source pad
The FET of claim 13 further comp nsin g at least one set of finger arrays which in cludes one of the source, gate and dra m electrodes 5 Seri al No 13/965,87 1
The FET of claim 13 fu rt her comp risin g a gate via formed m the first dielectric layer, one of the conductive gate connect strips be in g connected to one of the gate nodes through the gate via
The FET of claim 13 where in the gate pads and the source pad do not overlap one another
The FET of claim 13 where in one of the gate pads and the source pad overlap at least m part
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based semiconductor device (heterostructure FET with mesa, interdigitated electrodes)
GaN-based FET with finger arrays, mesa, source/gate/drain interconnects
Materials described outside the worked examples.
heterostructure channel layer
group III nitride semiconductor
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-section through two GaN-based FET cells constructed in accordance with the present invention. As shown, a heterojunction structure is formed …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 250000–1000000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,729,565Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-section through two GaN-based FET cells constructed in accordance with the present invention. As shown, a heterojunction structure is formed …
FIG. 2. In some embodiments of the invention the source and drain electrodes 50 and 70 extend about 2 -3 microns beyond the edge of the mesa. The gate …
FIG. 3, which is a cross-sectional view taken along line A- A in
FIG. 4. A source pad via 158 is formed in the dielectric layer 155. The source pad 150 is formed in and above the source pad via 158 and electrically contacts …
FIG. 5 is an even more greatly expanded plan view of the GaN-based FET showing two gate pads 120, source pad 150 and drain pad 162.
FIG. 6 is cross-sectional view of the FET taken along line C- C in
FIG. 7 is cross-sectional view of the FET taken along line D-D in
FIG. 8.
FIG. 9. One advantage of the embodiments of the invention shown in FIG s. 8-11 is that a relatively low spreading resistance can be achieved between the …
FIG. 10 is cross-section view of a FET through line E-E in
FIG. 11 is cross-sectional view of a FET through line F-F in
FIG. 12(b) shows the dependence of the breakdown voltage on the gate-to-drain spacing Lgd. These results, based on simulations, show that a low on-resistance …
FIG. 13 shows the dependence of the cut-off frequency of the device on the gate- to-drain spacing Lgd f o r two different gate lengths Lg. These simulated …
FIG. 14 is a plan view of an alternative embodiment of a FET layout in which there are two sets of fingers 145 instead of the single set of fingers shown in …
FIG. 15 shows yet another embodiment similar to
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comp nsing a heterostructure that in cludes a channel layer extend ing m a longitud in al direction, a first portion of the channel layer be in g located on a mesa and a second portion of the channel layer bein g located off the mesa, a se n es of m terdigitated gate, source and dra in electrodes extend ing m the longitud inal direction and be in g disposed over the first portion of the channel layer located on the mesa, the source and dra in electrodes extend ing m the longitud in al direction beyond an edge of the mesa and extend in g over the second portion of the channel layer, the gate electrodes extend in g along a sidewall of the mesa, a source pad located off the mesa, a conductive source in terconnect hav in g a first portion elect ri cally connected to one of the source electrodes and a second portion elect n cally connected to the source pad, a gate pad located off the mesa and overlapp in g the source pad at least m part, and a conductive gate in terconnect hav in g a first portion elect n cally connected to a portion of the gate electrode extend in g along the mesa sidewall, the conductive gate in terconnect hav in g a second portion elect ri cally commu ni cat in g with the gate pad
The semiconductor device of claim 1 further comp nsing a first dielect ric layer disposed under the conductive source in terconnect, and a source pad via formed m the first dielect nc layer, the source pad be in g located formed m the source pad via
The semiconductor device of claim 1 where in the conductive gate connect st ri p at least partially overlaps the conductive source in terconnect
The semiconductor device of claim 1 where in the channel layer comp ri ses a group III nitn de semiconductor mate nal
The semiconductor device of claim 1 where in the channel layer comp n ses GaN
The semiconductor device of claim 1 where in one of the gate electrodes has a length of about 3 microns
The semiconductor device of claim 1 where in the source electrodes extend beyond the edge of the mesa by about 2-3 microns
The semiconductor device of claim 1 where in the source, gate and dra m electrodes extend m the longitud in al direction between about 250 microns and 1mm 4 Sen al No 13/965,87 1
The semiconductor device of claim 1 where in a distance between one of the gate electrodes and one of the dra m electrodes is less than about 15 microns
The FET of claim 1 where in at least one of the conductive gate connect strip at least partially overlaps at least one of the conductive source in terconnects 6
A FET, comp rising a substrate, a channel layer disposed on the substrate and a ba rn er layer disposed over the channel layer, a plura li ty of source, gate and dra m electrodes located over the bar ri er layer and extend ing m a longitud in al direction thereon, where in a portion of the channel and bar ri er layers define a mesa extend ing m the longitud in al direction and the source and dra m electrodes extend beyond an edge of the mesa and where in the gate electrodes extends along an edge sidewall of the mesa, a plura li ty of conductive source in terconnects each hav in g a first end elect ri cally connected to one of the source electrodes, a first dielect ric layer disposed over the conductive source in terconnect, a plura li ty of conductive gate nodes, each of the conductive gate nodes elect n cally connect in g the portions of a pair of adjacent gate electrodes extend in g along the sidewall of the mesa, a plura li ty of gate pads disposed on the first dielect nc layer adjacent the mesa, a plura li ty of conductive gate connect st ri ps m contact with the conductive gate nodes, said conductive gate connect st ri ps each be ing m elect n cal contact with one of the gate pads, a source via formed m the first dielect nc layer, and a source pad formed m the source via, the conductive source in terconnects each hav in g a second end m elect ri cal contact with the source pad
The FET of claim 13 further comp nsin g at least one set of finger arrays which in cludes one of the source, gate and dra m electrodes 5 Seri al No 13/965,87 1
The FET of claim 13 fu rt her comp risin g a gate via formed m the first dielectric layer, one of the conductive gate connect strips be in g connected to one of the gate nodes through the gate via
The FET of claim 13 where in the gate pads and the source pad do not overlap one another
The FET of claim 13 where in one of the gate pads and the source pad overlap at least m part
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based semiconductor device (heterostructure FET with mesa, interdigitated electrodes)
GaN-based FET with finger arrays, mesa, source/gate/drain interconnects
Materials described outside the worked examples.
heterostructure channel layer
group III nitride semiconductor
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-section through two GaN-based FET cells constructed in accordance with the present invention. As shown, a heterojunction structure is formed …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 250000–1000000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,729,565Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-section through two GaN-based FET cells constructed in accordance with the present invention. As shown, a heterojunction structure is formed …
FIG. 2. In some embodiments of the invention the source and drain electrodes 50 and 70 extend about 2 -3 microns beyond the edge of the mesa. The gate …
FIG. 3, which is a cross-sectional view taken along line A- A in
FIG. 4. A source pad via 158 is formed in the dielectric layer 155. The source pad 150 is formed in and above the source pad via 158 and electrically contacts …
FIG. 5 is an even more greatly expanded plan view of the GaN-based FET showing two gate pads 120, source pad 150 and drain pad 162.
FIG. 6 is cross-sectional view of the FET taken along line C- C in
FIG. 7 is cross-sectional view of the FET taken along line D-D in
FIG. 8.
FIG. 9. One advantage of the embodiments of the invention shown in FIG s. 8-11 is that a relatively low spreading resistance can be achieved between the …
FIG. 10 is cross-section view of a FET through line E-E in
FIG. 11 is cross-sectional view of a FET through line F-F in
FIG. 12(b) shows the dependence of the breakdown voltage on the gate-to-drain spacing Lgd. These results, based on simulations, show that a low on-resistance …
FIG. 13 shows the dependence of the cut-off frequency of the device on the gate- to-drain spacing Lgd f o r two different gate lengths Lg. These simulated …
FIG. 14 is a plan view of an alternative embodiment of a FET layout in which there are two sets of fingers 145 instead of the single set of fingers shown in …
FIG. 15 shows yet another embodiment similar to
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comp nsing a heterostructure that in cludes a channel layer extend ing m a longitud in al direction, a first portion of the channel layer be in g located on a mesa and a second portion of the channel layer bein g located off the mesa, a se n es of m terdigitated gate, source and dra in electrodes extend ing m the longitud inal direction and be in g disposed over the first portion of the channel layer located on the mesa, the source and dra in electrodes extend ing m the longitud in al direction beyond an edge of the mesa and extend in g over the second portion of the channel layer, the gate electrodes extend in g along a sidewall of the mesa, a source pad located off the mesa, a conductive source in terconnect hav in g a first portion elect ri cally connected to one of the source electrodes and a second portion elect n cally connected to the source pad, a gate pad located off the mesa and overlapp in g the source pad at least m part, and a conductive gate in terconnect hav in g a first portion elect n cally connected to a portion of the gate electrode extend in g along the mesa sidewall, the conductive gate in terconnect hav in g a second portion elect ri cally commu ni cat in g with the gate pad
The semiconductor device of claim 1 further comp nsing a first dielect ric layer disposed under the conductive source in terconnect, and a source pad via formed m the first dielect nc layer, the source pad be in g located formed m the source pad via
The semiconductor device of claim 1 where in the conductive gate connect st ri p at least partially overlaps the conductive source in terconnect
The semiconductor device of claim 1 where in the channel layer comp ri ses a group III nitn de semiconductor mate nal
The semiconductor device of claim 1 where in the channel layer comp n ses GaN
The semiconductor device of claim 1 where in one of the gate electrodes has a length of about 3 microns
The semiconductor device of claim 1 where in the source electrodes extend beyond the edge of the mesa by about 2-3 microns
The semiconductor device of claim 1 where in the source, gate and dra m electrodes extend m the longitud in al direction between about 250 microns and 1mm 4 Sen al No 13/965,87 1
The semiconductor device of claim 1 where in a distance between one of the gate electrodes and one of the dra m electrodes is less than about 15 microns
The FET of claim 1 where in at least one of the conductive gate connect strip at least partially overlaps at least one of the conductive source in terconnects 6
A FET, comp rising a substrate, a channel layer disposed on the substrate and a ba rn er layer disposed over the channel layer, a plura li ty of source, gate and dra m electrodes located over the bar ri er layer and extend ing m a longitud in al direction thereon, where in a portion of the channel and bar ri er layers define a mesa extend ing m the longitud in al direction and the source and dra m electrodes extend beyond an edge of the mesa and where in the gate electrodes extends along an edge sidewall of the mesa, a plura li ty of conductive source in terconnects each hav in g a first end elect ri cally connected to one of the source electrodes, a first dielect ric layer disposed over the conductive source in terconnect, a plura li ty of conductive gate nodes, each of the conductive gate nodes elect n cally connect in g the portions of a pair of adjacent gate electrodes extend in g along the sidewall of the mesa, a plura li ty of gate pads disposed on the first dielect nc layer adjacent the mesa, a plura li ty of conductive gate connect st ri ps m contact with the conductive gate nodes, said conductive gate connect st ri ps each be ing m elect n cal contact with one of the gate pads, a source via formed m the first dielect nc layer, and a source pad formed m the source via, the conductive source in terconnects each hav in g a second end m elect ri cal contact with the source pad
The FET of claim 13 further comp nsin g at least one set of finger arrays which in cludes one of the source, gate and dra m electrodes 5 Seri al No 13/965,87 1
The FET of claim 13 fu rt her comp risin g a gate via formed m the first dielectric layer, one of the conductive gate connect strips be in g connected to one of the gate nodes through the gate via
The FET of claim 13 where in the gate pads and the source pad do not overlap one another
The FET of claim 13 where in one of the gate pads and the source pad overlap at least m part
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based semiconductor device (heterostructure FET with mesa, interdigitated electrodes)
GaN-based FET with finger arrays, mesa, source/gate/drain interconnects
Materials described outside the worked examples.
heterostructure channel layer
group III nitride semiconductor
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-section through two GaN-based FET cells constructed in accordance with the present invention. As shown, a heterojunction structure is formed …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 250000–1000000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
AlGaN barrier layer
AlGaN
FIG. 2. In some embodiments of the invention the source and drain electrodes 50 and 70 extend about 2 -3 microns beyond the edge of the mesa. The gate …
FIG. 4. A source pad via 158 is formed in the dielectric layer 155. The source pad 150 is formed in and above the source pad via 158 and electrically contacts …
FIG. 5 is an even more greatly expanded plan view of the GaN-based FET showing two gate pads 120, source pad 150 and drain pad 162.
FIG. 6 is cross-sectional view of the FET taken along line C- C in
FIG. 7 is cross-sectional view of the FET taken along line D-D in
FIG. 9. One advantage of the embodiments of the invention shown in FIG s. 8-11 is that a relatively low spreading resistance can be achieved between the …
FIG. 10 is cross-section view of a FET through line E-E in
FIG. 11 is cross-sectional view of a FET through line F-F in
FIG. 14 is a plan view of an alternative embodiment of a FET layout in which there are two sets of fingers 145 instead of the single set of fingers shown in …
| — |
Thickness | ≤ 15 µm | — |
AlGaN barrier layer
AlGaN
FIG. 2. In some embodiments of the invention the source and drain electrodes 50 and 70 extend about 2 -3 microns beyond the edge of the mesa. The gate …
FIG. 4. A source pad via 158 is formed in the dielectric layer 155. The source pad 150 is formed in and above the source pad via 158 and electrically contacts …
FIG. 5 is an even more greatly expanded plan view of the GaN-based FET showing two gate pads 120, source pad 150 and drain pad 162.
FIG. 6 is cross-sectional view of the FET taken along line C- C in
FIG. 7 is cross-sectional view of the FET taken along line D-D in
FIG. 9. One advantage of the embodiments of the invention shown in FIG s. 8-11 is that a relatively low spreading resistance can be achieved between the …
FIG. 10 is cross-section view of a FET through line E-E in
FIG. 11 is cross-sectional view of a FET through line F-F in
FIG. 14 is a plan view of an alternative embodiment of a FET layout in which there are two sets of fingers 145 instead of the single set of fingers shown in …
| — |
Thickness | ≤ 15 µm | — |
AlGaN barrier layer
AlGaN
FIG. 2. In some embodiments of the invention the source and drain electrodes 50 and 70 extend about 2 -3 microns beyond the edge of the mesa. The gate …
FIG. 4. A source pad via 158 is formed in the dielectric layer 155. The source pad 150 is formed in and above the source pad via 158 and electrically contacts …
FIG. 5 is an even more greatly expanded plan view of the GaN-based FET showing two gate pads 120, source pad 150 and drain pad 162.
FIG. 6 is cross-sectional view of the FET taken along line C- C in
FIG. 7 is cross-sectional view of the FET taken along line D-D in
FIG. 9. One advantage of the embodiments of the invention shown in FIG s. 8-11 is that a relatively low spreading resistance can be achieved between the …
FIG. 10 is cross-section view of a FET through line E-E in
FIG. 11 is cross-sectional view of a FET through line F-F in
FIG. 14 is a plan view of an alternative embodiment of a FET layout in which there are two sets of fingers 145 instead of the single set of fingers shown in …
| — |
Thickness | ≤ 15 µm | — |
AlGaN barrier layer
AlGaN
FIG. 2. In some embodiments of the invention the source and drain electrodes 50 and 70 extend about 2 -3 microns beyond the edge of the mesa. The gate …
FIG. 4. A source pad via 158 is formed in the dielectric layer 155. The source pad 150 is formed in and above the source pad via 158 and electrically contacts …
FIG. 5 is an even more greatly expanded plan view of the GaN-based FET showing two gate pads 120, source pad 150 and drain pad 162.
FIG. 6 is cross-sectional view of the FET taken along line C- C in
FIG. 7 is cross-sectional view of the FET taken along line D-D in
FIG. 9. One advantage of the embodiments of the invention shown in FIG s. 8-11 is that a relatively low spreading resistance can be achieved between the …
FIG. 10 is cross-section view of a FET through line E-E in
FIG. 11 is cross-sectional view of a FET through line F-F in
FIG. 14 is a plan view of an alternative embodiment of a FET layout in which there are two sets of fingers 145 instead of the single set of fingers shown in …
| — |
Thickness | ≤ 15 µm | — |