Patent
US 8,405,133SEMICONDUCTOR DEVICE INCLUDING GRAPHENE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
Hyun-jong Chung
US
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US 8,405,133Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a semiconductor device including graphene according to example embodiments; [0012]
FIG. 2 is a schematic perspective view of a semiconductor device including graphene according to example embodiments; [0013]
FIG. 3A is a cross-sectional view of a semiconductor device including graphene and a plurality of gate fingers according to example embodiments; [0014]
FIGS. 4A to 4E are sectional views for illustrating a method of manufacturing a semiconductor device including graphene according to example embodiments; and …
FIG. 5 is a simulation graph of current gains of a semiconductor device including graphene according to example embodiments and an RF device in which a gate …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a gate electrode on a substrate; a gate insulating layer on the gate electrode; an interlayer dielectric layer between the substrate and the gate electrode, and on side portions of the gate electrode and the gate insulating layer, the interlayer dielectric layer including a material that has a lower dielectric permittivity than the gate insulating layer; a graphene layer on the gate insulating layer and the interlayer dielectric layer; and a source and a drain on the graphene layer.
The semiconductor device of claim 1, wherein the gate electrode has at least one gate finger protruding from the gate electrode.
The semiconductor device of claim 1, wherein a portion of the graphene layer between the source and the drain is a channel region.
The semiconductor device of claim 1, wherein the semiconductor device is a radio frequency (RF) device.
A method of manufacturing a semiconductor device including graphene, the method comprising: forming a dielectric layer by doping a substrate with a first insulating material; forming a gate electrode and a gate insulating layer on the dielectric layer; 10 Atty. Dkt. No. 2557S 1 -001675/US forming an interlayer dielectric layer and exposing the gate insulating layer by doping the gate electrode and the gate insulating layer with a second insulating material; forming a graphene layer on the interlayer dielectric layer and the gate insulating layer; and forming a source and a drain on the graphene layer.
The method of claim 8, wherein the gate insulating layer comprises a material that has a higher dielectric permittivity than the interlayer dielectric layer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (graphene FET)
Materials described outside the worked examples.
graphene
gate insulating material (high-k)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a simulation graph of current gains of a semiconductor device including graphene according to example embodiments and an RF device in which a gate …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,405,133Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a semiconductor device including graphene according to example embodiments; [0012]
FIG. 2 is a schematic perspective view of a semiconductor device including graphene according to example embodiments; [0013]
FIG. 3A is a cross-sectional view of a semiconductor device including graphene and a plurality of gate fingers according to example embodiments; [0014]
FIGS. 4A to 4E are sectional views for illustrating a method of manufacturing a semiconductor device including graphene according to example embodiments; and …
FIG. 5 is a simulation graph of current gains of a semiconductor device including graphene according to example embodiments and an RF device in which a gate …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a gate electrode on a substrate; a gate insulating layer on the gate electrode; an interlayer dielectric layer between the substrate and the gate electrode, and on side portions of the gate electrode and the gate insulating layer, the interlayer dielectric layer including a material that has a lower dielectric permittivity than the gate insulating layer; a graphene layer on the gate insulating layer and the interlayer dielectric layer; and a source and a drain on the graphene layer.
The semiconductor device of claim 1, wherein the gate electrode has at least one gate finger protruding from the gate electrode.
The semiconductor device of claim 1, wherein a portion of the graphene layer between the source and the drain is a channel region.
The semiconductor device of claim 1, wherein the semiconductor device is a radio frequency (RF) device.
A method of manufacturing a semiconductor device including graphene, the method comprising: forming a dielectric layer by doping a substrate with a first insulating material; forming a gate electrode and a gate insulating layer on the dielectric layer; 10 Atty. Dkt. No. 2557S 1 -001675/US forming an interlayer dielectric layer and exposing the gate insulating layer by doping the gate electrode and the gate insulating layer with a second insulating material; forming a graphene layer on the interlayer dielectric layer and the gate insulating layer; and forming a source and a drain on the graphene layer.
The method of claim 8, wherein the gate insulating layer comprises a material that has a higher dielectric permittivity than the interlayer dielectric layer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (graphene FET)
Materials described outside the worked examples.
graphene
gate insulating material (high-k)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a simulation graph of current gains of a semiconductor device including graphene according to example embodiments and an RF device in which a gate …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,405,133Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a semiconductor device including graphene according to example embodiments; [0012]
FIG. 2 is a schematic perspective view of a semiconductor device including graphene according to example embodiments; [0013]
FIG. 3A is a cross-sectional view of a semiconductor device including graphene and a plurality of gate fingers according to example embodiments; [0014]
FIGS. 4A to 4E are sectional views for illustrating a method of manufacturing a semiconductor device including graphene according to example embodiments; and …
FIG. 5 is a simulation graph of current gains of a semiconductor device including graphene according to example embodiments and an RF device in which a gate …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a gate electrode on a substrate; a gate insulating layer on the gate electrode; an interlayer dielectric layer between the substrate and the gate electrode, and on side portions of the gate electrode and the gate insulating layer, the interlayer dielectric layer including a material that has a lower dielectric permittivity than the gate insulating layer; a graphene layer on the gate insulating layer and the interlayer dielectric layer; and a source and a drain on the graphene layer.
The semiconductor device of claim 1, wherein the gate electrode has at least one gate finger protruding from the gate electrode.
The semiconductor device of claim 1, wherein a portion of the graphene layer between the source and the drain is a channel region.
The semiconductor device of claim 1, wherein the semiconductor device is a radio frequency (RF) device.
A method of manufacturing a semiconductor device including graphene, the method comprising: forming a dielectric layer by doping a substrate with a first insulating material; forming a gate electrode and a gate insulating layer on the dielectric layer; 10 Atty. Dkt. No. 2557S 1 -001675/US forming an interlayer dielectric layer and exposing the gate insulating layer by doping the gate electrode and the gate insulating layer with a second insulating material; forming a graphene layer on the interlayer dielectric layer and the gate insulating layer; and forming a source and a drain on the graphene layer.
The method of claim 8, wherein the gate insulating layer comprises a material that has a higher dielectric permittivity than the interlayer dielectric layer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (graphene FET)
Materials described outside the worked examples.
graphene
gate insulating material (high-k)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a simulation graph of current gains of a semiconductor device including graphene according to example embodiments and an RF device in which a gate …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,405,133Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a semiconductor device including graphene according to example embodiments; [0012]
FIG. 2 is a schematic perspective view of a semiconductor device including graphene according to example embodiments; [0013]
FIG. 3A is a cross-sectional view of a semiconductor device including graphene and a plurality of gate fingers according to example embodiments; [0014]
FIGS. 4A to 4E are sectional views for illustrating a method of manufacturing a semiconductor device including graphene according to example embodiments; and …
FIG. 5 is a simulation graph of current gains of a semiconductor device including graphene according to example embodiments and an RF device in which a gate …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a gate electrode on a substrate; a gate insulating layer on the gate electrode; an interlayer dielectric layer between the substrate and the gate electrode, and on side portions of the gate electrode and the gate insulating layer, the interlayer dielectric layer including a material that has a lower dielectric permittivity than the gate insulating layer; a graphene layer on the gate insulating layer and the interlayer dielectric layer; and a source and a drain on the graphene layer.
The semiconductor device of claim 1, wherein the gate electrode has at least one gate finger protruding from the gate electrode.
The semiconductor device of claim 1, wherein a portion of the graphene layer between the source and the drain is a channel region.
The semiconductor device of claim 1, wherein the semiconductor device is a radio frequency (RF) device.
A method of manufacturing a semiconductor device including graphene, the method comprising: forming a dielectric layer by doping a substrate with a first insulating material; forming a gate electrode and a gate insulating layer on the dielectric layer; 10 Atty. Dkt. No. 2557S 1 -001675/US forming an interlayer dielectric layer and exposing the gate insulating layer by doping the gate electrode and the gate insulating layer with a second insulating material; forming a graphene layer on the interlayer dielectric layer and the gate insulating layer; and forming a source and a drain on the graphene layer.
The method of claim 8, wherein the gate insulating layer comprises a material that has a higher dielectric permittivity than the interlayer dielectric layer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (graphene FET)
Materials described outside the worked examples.
graphene
gate insulating material (high-k)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a simulation graph of current gains of a semiconductor device including graphene according to example embodiments and an RF device in which a gate …
Related documents with shared materials, methods, properties, or citations.
interlayer dielectric material (low-k relative to gate insulator)
silicon oxide
SiO₂
silicon
Si
interlayer dielectric material (low-k relative to gate insulator)
silicon oxide
SiO₂
silicon
Si
interlayer dielectric material (low-k relative to gate insulator)
silicon oxide
SiO₂
silicon
Si
interlayer dielectric material (low-k relative to gate insulator)
silicon oxide
SiO₂
silicon
Si