Patent
US 9,105,556TUNNELING FIELD-EFFECT TRANSISTOR INCLUDING GRAPHENE CHANNEL
Jin-seong HEO
US
Copyright © 2026 Matter42. All rights reserved.
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view illustrating a tunneling field-effect transistor (TFET) including a graphene channel according to example embodiments; [0029]
FIGS. 2A through 2 C are energy band diagrams describing an operation of the TFET of
FIG. 3 is a graph illustrating I-V characteristics of a TFET including a graphene channel according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A tunneling field-effect transistor (TFET) comprising: a substrate; a first electrode on the substrate, the first electrode being a metal, the first electrode including a portion that is adjacent to a first area of the substrate; a semiconductor layer directly on top of the portion of the first electrode; a graphene channel on the semiconductor layer, the semiconductor layer being between the graphene channel and the portion of the first electrode, the graphene channel extending beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate; a second electrode on the graphene channel, the second electrode being over the first area of the substrate; a gate insulating layer on the graphene channel; and a gate electrode on the gate insulating layer. Application No. 13/906,657 Attorney Docket No. 2557 SI -001963-US Page 3 of
The TFET of the claim 1, further comprising: a first insulating layer between the graphene channel and the first area of the substrate.
The TFET of claim 1, wherein the first electrode comprises a body portion and an extension portion, the extension portion extends from the body portion toward the first area, and the portion of the first electrode is the extension portion.
The TFET of claim 1, wherein a thickness of the semiconductor layer is about 1 n m to about 30 nm.
The T F ET of claim 1, wherein the first electrode includes at least one of Pt, Ni, Au, Pd, Co, Be, Cu, Re, Ru, Fe, W, Sb, Mo, Ag, and Cr.
The TFET of claim 1, wherein the semiconductor layer includes impurities, and the TFET is a unipolar transistor having a same polarity as a polarity of the impurities in the semiconductor layer.
The TFET of claim 1, wherein the gate electrode, depending on a gate voltage that is applied to the gate electrode, is configured to change a tunneling thickness of an energy band of the semiconductor layer between the first electrode and the graphene channel.
The TF ET of claim 1, a thickness of the graphene channel is 1 to 4 layers of graphene. Application No. 13/906,657 Attorney Docket No. 2557S I -001963-US Page 5 of
The TFET of claim 1, wherein a first energy ba rri er is formed at one of: an interface between the semiconductor layer and the first electrode; and an interface between the semiconductor layer and the graphene channel.
A tunneling field-effect transistor (T F ET) comprising: a substrate; a first electrode on the substrate, the first electrode including a portion that is adjacent to a first area of the substrate; a semiconductor layer on the portion of the first electrode, the semiconductor layer including at least one of gallium indium zin c oxide (GIZO), a-Si, Si, HIZO, MoS2, CdSe, ZnO, A J P,InP, S T'iO 3, Ge, GaAs, SiC, A l As, GaN, CdTe, CuO, NiO, and GaMnAs; a graphene channel on the semiconductor layer, the semiconductor layer being between the graphene channel and the portion of the first electrode, the graphene channel extending beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate; Application No. 13/906,657 Attorney Docket No. 2557S I -001963-US Page 4 of 20 a second electrode on the graphene channel, the second electrode being over the first area of the substrate; a gate insulating layer on the graphene channel; and a gate electrode on the gate insulating layer.
A tunneling field-effect transistor (TFET) comprising: a first electrode, the first electrode being a metal; a semiconductor layer directly on top of the first electrode; a graphene channel on the semiconductor layer, the graphene channel including a portion that extends away from at least one of the semiconductor layer and the first electrode; a second electrode on the portion of the graphene channel, the second electrode being spaced apart from the semiconductor layer Application No. 13/906,657 Attorney Docket No. 2557S I -001963-US Page 6 of 20 and the first electrode; a gate electrode on the graphene channel; a gate insulating layer between the gate electrode and at least one of the first electrode, the graphene channel, and the second electrode.
The TFET of claim 14, further comprising: a first insulating layer, wherein the portion of the graphene channel is on the first insulating layer.
The TFET of claim 14, wherein the gate electrode, depending on a gate voltage that is applied to the gate electrode, is configured to change a tunneling thickness of an energy band of the semiconductor layer between the first electrode and the graphene channel.
The TFET of claim 14, wherein a first energy barrier is for m ed at an interface between the semiconductor layer and the first electrode, second energy ba rri er is formed at an interface between the semiconductor layer and the graphene channel, and a level of the first energy barrier is different than a level of the second energy barri er.
The TFET of claim 14, wherein the first electrode comprises a body portion and an extension portion, the semiconductor layer is on the extension portion, and Application No. 13/906,657 Attorney Docket No. 2557S I -001963-US Page 7 of 20 a thickness of the extension portion is less than a thickness of the body portion.
The TFET of claim 14, wherein the semiconductor layer includes impurities, and the TFET is a unipolar transistor having a same polarity as a polarity of the impurities in the semiconductor layer.
The T F ET of claim 14, wherein a thic k ness of the graphene channel is 1 to 4 layers of graphene; and the semiconductor layer includes at least one of gallium indium zinc oxide (GIZO), a-Si, Si, HIZO, M o S 2, CdSe, ZnO, A 1 P,InP, S i''i0 3, Ge, GaAs, SiC, AlAs, GaN, CdTe, CuO, NiO, and GaMnAs.
- 22.. canceled
The TFET of claim [[2 SVG 13906657.03-12-2015.I₇₇VBLV₀PXXIFW1.CLM.6.15.1573.2001.1662.2046.svg 0.15 0.297 Chemistry Black and white wherein the first electrode is directly on the substrate, the graphene channel is not in direct contact with the first semiconductor layer and the first electrode, the graphene channel, the portion of the first electrode, gate insulating layer isolates the first and second Docket No. 2557S I -001963-US Page 8 of
The T F ET of claim [[22]].14, wherein the first electrode, and the gate insulating layer is the graphene channel, a portion of the first electrode, END CLAIM LISTING *** electrode, the second electrode is spaced apart from gate insulating layer covers a portion of the and a portion of the second electrode, and the electrode. Application No. 13/906,657 Attorney graphene channel is not in direct contact with between the gate electrode and the portion of and a portion of the second electrode.
Layer stacks claimed or described, ordered top of device to substrate.
tunneling field-effect transistor (TFET) with substrate
tunneling field-effect transistor (TFET) without explicit substrate recitation
Materials described outside the worked examples.
graphene
semiconductor layer
gallium indium zinc oxide (GIZO)
amorphous silicon
a-Si
silicon
Si
HIZO
molybdenum disulfide
MoS₂
cadmium selenide
CdSe
zinc oxide
ZnO
aluminum phosphide
AlP
indium phosphide
InP
strontium titanate
SrTiO₃
germanium
Ge
gallium arsenide
GaAs
silicon carbide
SiC
aluminum arsenide
AlAs
gallium nitride
GaN
cadmium telluride
CdTe
copper oxide
CuO
nickel oxide
NiO
first electrode metal
gallium manganese arsenide
GaMnAs
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view illustrating a tunneling field-effect transistor (TFET) including a graphene channel according to example embodiments; [0029]
FIG. 3 is a graph illustrating I-V characteristics of a TFET including a graphene channel according to example embodiments.
FIG. 3 is a graph illustrating I-V characteristics of a TFET including a graphene channel according to example embodiments.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
second energy barrier at semiconductor/electrode or semiconductor/graphene interface | ≤ 0.3 eV | semiconductor layer |
semiconductor layer thickness range | 1–30 nm | semiconductor layer |
graphene channel thickness | 1–4 layers | graphene |
Voltage | 9–9 V | — |
Related documents with shared materials, methods, properties, or citations.
GRAPHENE FET DEVICES, SYSTEMS, AND METHODS OF USING THE SAME FOR SEQUENCING NUCLEIC ACIDS
ELECTRONIC DEVICE INCLUDING GRAPHENE
GRAPHENE ELECTRONIC DEVICES HAVING MULTI-LAYERED GATE INSULATING LAYER
GRAPHENE TRANSISTOR AND TERNARY LOGIC DEVICE USING THE SAME
GRAPHITE AND/OR GRAPHENE SEMICONDUCTOR DEVICES
GRAPHENE-BASED EFUSE DEVICE
GRAPHENE-ENCAPSULATED NANOPARTICLE-BASED BIOSENSOR FOR THE SELECTIVE DETECTION OF BIOMARKERS
CASCODE STRUCTURES WITH GaN CAP LAYERS
GRAPHENE ELECTRONIC DEVICE HAVING CHANNEL LAYER INCLUDING GRAPHENE ISLANDS AND METHOD OF FABRICATING THE SAME
METHOD OF MANUFACTURING GRAPHENE, CARBON NANOTUBES, FULLERENE, GRAPHITE OR A COMBINATION THEREOF HAVING A POSITION SPECIFICALLY REGULATED RESISTANCE
Graphene Electronic Devices
TUNABLE GRAPHENE LIGHT-EMITTING DEVICE
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view illustrating a tunneling field-effect transistor (TFET) including a graphene channel according to example embodiments; [0029]
FIGS. 2A through 2 C are energy band diagrams describing an operation of the TFET of
FIG. 3 is a graph illustrating I-V characteristics of a TFET including a graphene channel according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A tunneling field-effect transistor (TFET) comprising: a substrate; a first electrode on the substrate, the first electrode being a metal, the first electrode including a portion that is adjacent to a first area of the substrate; a semiconductor layer directly on top of the portion of the first electrode; a graphene channel on the semiconductor layer, the semiconductor layer being between the graphene channel and the portion of the first electrode, the graphene channel extending beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate; a second electrode on the graphene channel, the second electrode being over the first area of the substrate; a gate insulating layer on the graphene channel; and a gate electrode on the gate insulating layer. Application No. 13/906,657 Attorney Docket No. 2557 SI -001963-US Page 3 of
The TFET of the claim 1, further comprising: a first insulating layer between the graphene channel and the first area of the substrate.
The TFET of claim 1, wherein the first electrode comprises a body portion and an extension portion, the extension portion extends from the body portion toward the first area, and the portion of the first electrode is the extension portion.
The TFET of claim 1, wherein a thickness of the semiconductor layer is about 1 n m to about 30 nm.
The T F ET of claim 1, wherein the first electrode includes at least one of Pt, Ni, Au, Pd, Co, Be, Cu, Re, Ru, Fe, W, Sb, Mo, Ag, and Cr.
The TFET of claim 1, wherein the semiconductor layer includes impurities, and the TFET is a unipolar transistor having a same polarity as a polarity of the impurities in the semiconductor layer.
The TFET of claim 1, wherein the gate electrode, depending on a gate voltage that is applied to the gate electrode, is configured to change a tunneling thickness of an energy band of the semiconductor layer between the first electrode and the graphene channel.
The TF ET of claim 1, a thickness of the graphene channel is 1 to 4 layers of graphene. Application No. 13/906,657 Attorney Docket No. 2557S I -001963-US Page 5 of
The TFET of claim 1, wherein a first energy ba rri er is formed at one of: an interface between the semiconductor layer and the first electrode; and an interface between the semiconductor layer and the graphene channel.
A tunneling field-effect transistor (T F ET) comprising: a substrate; a first electrode on the substrate, the first electrode including a portion that is adjacent to a first area of the substrate; a semiconductor layer on the portion of the first electrode, the semiconductor layer including at least one of gallium indium zin c oxide (GIZO), a-Si, Si, HIZO, MoS2, CdSe, ZnO, A J P,InP, S T'iO 3, Ge, GaAs, SiC, A l As, GaN, CdTe, CuO, NiO, and GaMnAs; a graphene channel on the semiconductor layer, the semiconductor layer being between the graphene channel and the portion of the first electrode, the graphene channel extending beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate; Application No. 13/906,657 Attorney Docket No. 2557S I -001963-US Page 4 of 20 a second electrode on the graphene channel, the second electrode being over the first area of the substrate; a gate insulating layer on the graphene channel; and a gate electrode on the gate insulating layer.
A tunneling field-effect transistor (TFET) comprising: a first electrode, the first electrode being a metal; a semiconductor layer directly on top of the first electrode; a graphene channel on the semiconductor layer, the graphene channel including a portion that extends away from at least one of the semiconductor layer and the first electrode; a second electrode on the portion of the graphene channel, the second electrode being spaced apart from the semiconductor layer Application No. 13/906,657 Attorney Docket No. 2557S I -001963-US Page 6 of 20 and the first electrode; a gate electrode on the graphene channel; a gate insulating layer between the gate electrode and at least one of the first electrode, the graphene channel, and the second electrode.
The TFET of claim 14, further comprising: a first insulating layer, wherein the portion of the graphene channel is on the first insulating layer.
The TFET of claim 14, wherein the gate electrode, depending on a gate voltage that is applied to the gate electrode, is configured to change a tunneling thickness of an energy band of the semiconductor layer between the first electrode and the graphene channel.
The TFET of claim 14, wherein a first energy barrier is for m ed at an interface between the semiconductor layer and the first electrode, second energy ba rri er is formed at an interface between the semiconductor layer and the graphene channel, and a level of the first energy barrier is different than a level of the second energy barri er.
The TFET of claim 14, wherein the first electrode comprises a body portion and an extension portion, the semiconductor layer is on the extension portion, and Application No. 13/906,657 Attorney Docket No. 2557S I -001963-US Page 7 of 20 a thickness of the extension portion is less than a thickness of the body portion.
The TFET of claim 14, wherein the semiconductor layer includes impurities, and the TFET is a unipolar transistor having a same polarity as a polarity of the impurities in the semiconductor layer.
The T F ET of claim 14, wherein a thic k ness of the graphene channel is 1 to 4 layers of graphene; and the semiconductor layer includes at least one of gallium indium zinc oxide (GIZO), a-Si, Si, HIZO, M o S 2, CdSe, ZnO, A 1 P,InP, S i''i0 3, Ge, GaAs, SiC, AlAs, GaN, CdTe, CuO, NiO, and GaMnAs.
- 22.. canceled
The TFET of claim [[2 SVG 13906657.03-12-2015.I₇₇VBLV₀PXXIFW1.CLM.6.15.1573.2001.1662.2046.svg 0.15 0.297 Chemistry Black and white wherein the first electrode is directly on the substrate, the graphene channel is not in direct contact with the first semiconductor layer and the first electrode, the graphene channel, the portion of the first electrode, gate insulating layer isolates the first and second Docket No. 2557S I -001963-US Page 8 of
The T F ET of claim [[22]].14, wherein the first electrode, and the gate insulating layer is the graphene channel, a portion of the first electrode, END CLAIM LISTING *** electrode, the second electrode is spaced apart from gate insulating layer covers a portion of the and a portion of the second electrode, and the electrode. Application No. 13/906,657 Attorney graphene channel is not in direct contact with between the gate electrode and the portion of and a portion of the second electrode.
Layer stacks claimed or described, ordered top of device to substrate.
tunneling field-effect transistor (TFET) with substrate
tunneling field-effect transistor (TFET) without explicit substrate recitation
Materials described outside the worked examples.
graphene
semiconductor layer
gallium indium zinc oxide (GIZO)
amorphous silicon
a-Si
silicon
Si
HIZO
molybdenum disulfide
MoS₂
cadmium selenide
CdSe
zinc oxide
ZnO
aluminum phosphide
AlP
indium phosphide
InP
strontium titanate
SrTiO₃
germanium
Ge
gallium arsenide
GaAs
silicon carbide
SiC
aluminum arsenide
AlAs
gallium nitride
GaN
cadmium telluride
CdTe
copper oxide
CuO
nickel oxide
NiO
first electrode metal
gallium manganese arsenide
GaMnAs
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view illustrating a tunneling field-effect transistor (TFET) including a graphene channel according to example embodiments; [0029]
FIG. 3 is a graph illustrating I-V characteristics of a TFET including a graphene channel according to example embodiments.
FIG. 3 is a graph illustrating I-V characteristics of a TFET including a graphene channel according to example embodiments.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
second energy barrier at semiconductor/electrode or semiconductor/graphene interface | ≤ 0.3 eV | semiconductor layer |
semiconductor layer thickness range | 1–30 nm | semiconductor layer |
graphene channel thickness | 1–4 layers | graphene |
Voltage | 9–9 V | — |
Related documents with shared materials, methods, properties, or citations.
GRAPHENE FET DEVICES, SYSTEMS, AND METHODS OF USING THE SAME FOR SEQUENCING NUCLEIC ACIDS
ELECTRONIC DEVICE INCLUDING GRAPHENE
GRAPHENE ELECTRONIC DEVICES HAVING MULTI-LAYERED GATE INSULATING LAYER
GRAPHENE TRANSISTOR AND TERNARY LOGIC DEVICE USING THE SAME
GRAPHITE AND/OR GRAPHENE SEMICONDUCTOR DEVICES
GRAPHENE-BASED EFUSE DEVICE
GRAPHENE-ENCAPSULATED NANOPARTICLE-BASED BIOSENSOR FOR THE SELECTIVE DETECTION OF BIOMARKERS
CASCODE STRUCTURES WITH GaN CAP LAYERS
GRAPHENE ELECTRONIC DEVICE HAVING CHANNEL LAYER INCLUDING GRAPHENE ISLANDS AND METHOD OF FABRICATING THE SAME
METHOD OF MANUFACTURING GRAPHENE, CARBON NANOTUBES, FULLERENE, GRAPHITE OR A COMBINATION THEREOF HAVING A POSITION SPECIFICALLY REGULATED RESISTANCE
Graphene Electronic Devices
TUNABLE GRAPHENE LIGHT-EMITTING DEVICE
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view illustrating a tunneling field-effect transistor (TFET) including a graphene channel according to example embodiments; [0029]
FIGS. 2A through 2 C are energy band diagrams describing an operation of the TFET of
FIG. 3 is a graph illustrating I-V characteristics of a TFET including a graphene channel according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A tunneling field-effect transistor (TFET) comprising: a substrate; a first electrode on the substrate, the first electrode being a metal, the first electrode including a portion that is adjacent to a first area of the substrate; a semiconductor layer directly on top of the portion of the first electrode; a graphene channel on the semiconductor layer, the semiconductor layer being between the graphene channel and the portion of the first electrode, the graphene channel extending beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate; a second electrode on the graphene channel, the second electrode being over the first area of the substrate; a gate insulating layer on the graphene channel; and a gate electrode on the gate insulating layer. Application No. 13/906,657 Attorney Docket No. 2557 SI -001963-US Page 3 of
The TFET of the claim 1, further comprising: a first insulating layer between the graphene channel and the first area of the substrate.
The TFET of claim 1, wherein the first electrode comprises a body portion and an extension portion, the extension portion extends from the body portion toward the first area, and the portion of the first electrode is the extension portion.
The TFET of claim 1, wherein a thickness of the semiconductor layer is about 1 n m to about 30 nm.
The T F ET of claim 1, wherein the first electrode includes at least one of Pt, Ni, Au, Pd, Co, Be, Cu, Re, Ru, Fe, W, Sb, Mo, Ag, and Cr.
The TFET of claim 1, wherein the semiconductor layer includes impurities, and the TFET is a unipolar transistor having a same polarity as a polarity of the impurities in the semiconductor layer.
The TFET of claim 1, wherein the gate electrode, depending on a gate voltage that is applied to the gate electrode, is configured to change a tunneling thickness of an energy band of the semiconductor layer between the first electrode and the graphene channel.
The TF ET of claim 1, a thickness of the graphene channel is 1 to 4 layers of graphene. Application No. 13/906,657 Attorney Docket No. 2557S I -001963-US Page 5 of
The TFET of claim 1, wherein a first energy ba rri er is formed at one of: an interface between the semiconductor layer and the first electrode; and an interface between the semiconductor layer and the graphene channel.
A tunneling field-effect transistor (T F ET) comprising: a substrate; a first electrode on the substrate, the first electrode including a portion that is adjacent to a first area of the substrate; a semiconductor layer on the portion of the first electrode, the semiconductor layer including at least one of gallium indium zin c oxide (GIZO), a-Si, Si, HIZO, MoS2, CdSe, ZnO, A J P,InP, S T'iO 3, Ge, GaAs, SiC, A l As, GaN, CdTe, CuO, NiO, and GaMnAs; a graphene channel on the semiconductor layer, the semiconductor layer being between the graphene channel and the portion of the first electrode, the graphene channel extending beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate; Application No. 13/906,657 Attorney Docket No. 2557S I -001963-US Page 4 of 20 a second electrode on the graphene channel, the second electrode being over the first area of the substrate; a gate insulating layer on the graphene channel; and a gate electrode on the gate insulating layer.
A tunneling field-effect transistor (TFET) comprising: a first electrode, the first electrode being a metal; a semiconductor layer directly on top of the first electrode; a graphene channel on the semiconductor layer, the graphene channel including a portion that extends away from at least one of the semiconductor layer and the first electrode; a second electrode on the portion of the graphene channel, the second electrode being spaced apart from the semiconductor layer Application No. 13/906,657 Attorney Docket No. 2557S I -001963-US Page 6 of 20 and the first electrode; a gate electrode on the graphene channel; a gate insulating layer between the gate electrode and at least one of the first electrode, the graphene channel, and the second electrode.
The TFET of claim 14, further comprising: a first insulating layer, wherein the portion of the graphene channel is on the first insulating layer.
The TFET of claim 14, wherein the gate electrode, depending on a gate voltage that is applied to the gate electrode, is configured to change a tunneling thickness of an energy band of the semiconductor layer between the first electrode and the graphene channel.
The TFET of claim 14, wherein a first energy barrier is for m ed at an interface between the semiconductor layer and the first electrode, second energy ba rri er is formed at an interface between the semiconductor layer and the graphene channel, and a level of the first energy barrier is different than a level of the second energy barri er.
The TFET of claim 14, wherein the first electrode comprises a body portion and an extension portion, the semiconductor layer is on the extension portion, and Application No. 13/906,657 Attorney Docket No. 2557S I -001963-US Page 7 of 20 a thickness of the extension portion is less than a thickness of the body portion.
The TFET of claim 14, wherein the semiconductor layer includes impurities, and the TFET is a unipolar transistor having a same polarity as a polarity of the impurities in the semiconductor layer.
The T F ET of claim 14, wherein a thic k ness of the graphene channel is 1 to 4 layers of graphene; and the semiconductor layer includes at least one of gallium indium zinc oxide (GIZO), a-Si, Si, HIZO, M o S 2, CdSe, ZnO, A 1 P,InP, S i''i0 3, Ge, GaAs, SiC, AlAs, GaN, CdTe, CuO, NiO, and GaMnAs.
- 22.. canceled
The TFET of claim [[2 SVG 13906657.03-12-2015.I₇₇VBLV₀PXXIFW1.CLM.6.15.1573.2001.1662.2046.svg 0.15 0.297 Chemistry Black and white wherein the first electrode is directly on the substrate, the graphene channel is not in direct contact with the first semiconductor layer and the first electrode, the graphene channel, the portion of the first electrode, gate insulating layer isolates the first and second Docket No. 2557S I -001963-US Page 8 of
The T F ET of claim [[22]].14, wherein the first electrode, and the gate insulating layer is the graphene channel, a portion of the first electrode, END CLAIM LISTING *** electrode, the second electrode is spaced apart from gate insulating layer covers a portion of the and a portion of the second electrode, and the electrode. Application No. 13/906,657 Attorney graphene channel is not in direct contact with between the gate electrode and the portion of and a portion of the second electrode.
Layer stacks claimed or described, ordered top of device to substrate.
tunneling field-effect transistor (TFET) with substrate
tunneling field-effect transistor (TFET) without explicit substrate recitation
Materials described outside the worked examples.
graphene
semiconductor layer
gallium indium zinc oxide (GIZO)
amorphous silicon
a-Si
silicon
Si
HIZO
molybdenum disulfide
MoS₂
cadmium selenide
CdSe
zinc oxide
ZnO
aluminum phosphide
AlP
indium phosphide
InP
strontium titanate
SrTiO₃
germanium
Ge
gallium arsenide
GaAs
silicon carbide
SiC
aluminum arsenide
AlAs
gallium nitride
GaN
cadmium telluride
CdTe
copper oxide
CuO
nickel oxide
NiO
first electrode metal
gallium manganese arsenide
GaMnAs
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view illustrating a tunneling field-effect transistor (TFET) including a graphene channel according to example embodiments; [0029]
FIG. 3 is a graph illustrating I-V characteristics of a TFET including a graphene channel according to example embodiments.
FIG. 3 is a graph illustrating I-V characteristics of a TFET including a graphene channel according to example embodiments.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
second energy barrier at semiconductor/electrode or semiconductor/graphene interface | ≤ 0.3 eV | semiconductor layer |
semiconductor layer thickness range | 1–30 nm | semiconductor layer |
graphene channel thickness | 1–4 layers | graphene |
Voltage | 9–9 V | — |
Related documents with shared materials, methods, properties, or citations.
GRAPHENE FET DEVICES, SYSTEMS, AND METHODS OF USING THE SAME FOR SEQUENCING NUCLEIC ACIDS
ELECTRONIC DEVICE INCLUDING GRAPHENE
GRAPHENE ELECTRONIC DEVICES HAVING MULTI-LAYERED GATE INSULATING LAYER
GRAPHENE TRANSISTOR AND TERNARY LOGIC DEVICE USING THE SAME
GRAPHITE AND/OR GRAPHENE SEMICONDUCTOR DEVICES
GRAPHENE-BASED EFUSE DEVICE
GRAPHENE-ENCAPSULATED NANOPARTICLE-BASED BIOSENSOR FOR THE SELECTIVE DETECTION OF BIOMARKERS
CASCODE STRUCTURES WITH GaN CAP LAYERS
GRAPHENE ELECTRONIC DEVICE HAVING CHANNEL LAYER INCLUDING GRAPHENE ISLANDS AND METHOD OF FABRICATING THE SAME
METHOD OF MANUFACTURING GRAPHENE, CARBON NANOTUBES, FULLERENE, GRAPHITE OR A COMBINATION THEREOF HAVING A POSITION SPECIFICALLY REGULATED RESISTANCE
Graphene Electronic Devices
TUNABLE GRAPHENE LIGHT-EMITTING DEVICE
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view illustrating a tunneling field-effect transistor (TFET) including a graphene channel according to example embodiments; [0029]
FIGS. 2A through 2 C are energy band diagrams describing an operation of the TFET of
FIG. 3 is a graph illustrating I-V characteristics of a TFET including a graphene channel according to example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A tunneling field-effect transistor (TFET) comprising: a substrate; a first electrode on the substrate, the first electrode being a metal, the first electrode including a portion that is adjacent to a first area of the substrate; a semiconductor layer directly on top of the portion of the first electrode; a graphene channel on the semiconductor layer, the semiconductor layer being between the graphene channel and the portion of the first electrode, the graphene channel extending beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate; a second electrode on the graphene channel, the second electrode being over the first area of the substrate; a gate insulating layer on the graphene channel; and a gate electrode on the gate insulating layer. Application No. 13/906,657 Attorney Docket No. 2557 SI -001963-US Page 3 of
The TFET of the claim 1, further comprising: a first insulating layer between the graphene channel and the first area of the substrate.
The TFET of claim 1, wherein the first electrode comprises a body portion and an extension portion, the extension portion extends from the body portion toward the first area, and the portion of the first electrode is the extension portion.
The TFET of claim 1, wherein a thickness of the semiconductor layer is about 1 n m to about 30 nm.
The T F ET of claim 1, wherein the first electrode includes at least one of Pt, Ni, Au, Pd, Co, Be, Cu, Re, Ru, Fe, W, Sb, Mo, Ag, and Cr.
The TFET of claim 1, wherein the semiconductor layer includes impurities, and the TFET is a unipolar transistor having a same polarity as a polarity of the impurities in the semiconductor layer.
The TFET of claim 1, wherein the gate electrode, depending on a gate voltage that is applied to the gate electrode, is configured to change a tunneling thickness of an energy band of the semiconductor layer between the first electrode and the graphene channel.
The TF ET of claim 1, a thickness of the graphene channel is 1 to 4 layers of graphene. Application No. 13/906,657 Attorney Docket No. 2557S I -001963-US Page 5 of
The TFET of claim 1, wherein a first energy ba rri er is formed at one of: an interface between the semiconductor layer and the first electrode; and an interface between the semiconductor layer and the graphene channel.
A tunneling field-effect transistor (T F ET) comprising: a substrate; a first electrode on the substrate, the first electrode including a portion that is adjacent to a first area of the substrate; a semiconductor layer on the portion of the first electrode, the semiconductor layer including at least one of gallium indium zin c oxide (GIZO), a-Si, Si, HIZO, MoS2, CdSe, ZnO, A J P,InP, S T'iO 3, Ge, GaAs, SiC, A l As, GaN, CdTe, CuO, NiO, and GaMnAs; a graphene channel on the semiconductor layer, the semiconductor layer being between the graphene channel and the portion of the first electrode, the graphene channel extending beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate; Application No. 13/906,657 Attorney Docket No. 2557S I -001963-US Page 4 of 20 a second electrode on the graphene channel, the second electrode being over the first area of the substrate; a gate insulating layer on the graphene channel; and a gate electrode on the gate insulating layer.
A tunneling field-effect transistor (TFET) comprising: a first electrode, the first electrode being a metal; a semiconductor layer directly on top of the first electrode; a graphene channel on the semiconductor layer, the graphene channel including a portion that extends away from at least one of the semiconductor layer and the first electrode; a second electrode on the portion of the graphene channel, the second electrode being spaced apart from the semiconductor layer Application No. 13/906,657 Attorney Docket No. 2557S I -001963-US Page 6 of 20 and the first electrode; a gate electrode on the graphene channel; a gate insulating layer between the gate electrode and at least one of the first electrode, the graphene channel, and the second electrode.
The TFET of claim 14, further comprising: a first insulating layer, wherein the portion of the graphene channel is on the first insulating layer.
The TFET of claim 14, wherein the gate electrode, depending on a gate voltage that is applied to the gate electrode, is configured to change a tunneling thickness of an energy band of the semiconductor layer between the first electrode and the graphene channel.
The TFET of claim 14, wherein a first energy barrier is for m ed at an interface between the semiconductor layer and the first electrode, second energy ba rri er is formed at an interface between the semiconductor layer and the graphene channel, and a level of the first energy barrier is different than a level of the second energy barri er.
The TFET of claim 14, wherein the first electrode comprises a body portion and an extension portion, the semiconductor layer is on the extension portion, and Application No. 13/906,657 Attorney Docket No. 2557S I -001963-US Page 7 of 20 a thickness of the extension portion is less than a thickness of the body portion.
The TFET of claim 14, wherein the semiconductor layer includes impurities, and the TFET is a unipolar transistor having a same polarity as a polarity of the impurities in the semiconductor layer.
The T F ET of claim 14, wherein a thic k ness of the graphene channel is 1 to 4 layers of graphene; and the semiconductor layer includes at least one of gallium indium zinc oxide (GIZO), a-Si, Si, HIZO, M o S 2, CdSe, ZnO, A 1 P,InP, S i''i0 3, Ge, GaAs, SiC, AlAs, GaN, CdTe, CuO, NiO, and GaMnAs.
- 22.. canceled
The TFET of claim [[2 SVG 13906657.03-12-2015.I₇₇VBLV₀PXXIFW1.CLM.6.15.1573.2001.1662.2046.svg 0.15 0.297 Chemistry Black and white wherein the first electrode is directly on the substrate, the graphene channel is not in direct contact with the first semiconductor layer and the first electrode, the graphene channel, the portion of the first electrode, gate insulating layer isolates the first and second Docket No. 2557S I -001963-US Page 8 of
The T F ET of claim [[22]].14, wherein the first electrode, and the gate insulating layer is the graphene channel, a portion of the first electrode, END CLAIM LISTING *** electrode, the second electrode is spaced apart from gate insulating layer covers a portion of the and a portion of the second electrode, and the electrode. Application No. 13/906,657 Attorney graphene channel is not in direct contact with between the gate electrode and the portion of and a portion of the second electrode.
Layer stacks claimed or described, ordered top of device to substrate.
tunneling field-effect transistor (TFET) with substrate
tunneling field-effect transistor (TFET) without explicit substrate recitation
Materials described outside the worked examples.
graphene
semiconductor layer
gallium indium zinc oxide (GIZO)
amorphous silicon
a-Si
silicon
Si
HIZO
molybdenum disulfide
MoS₂
cadmium selenide
CdSe
zinc oxide
ZnO
aluminum phosphide
AlP
indium phosphide
InP
strontium titanate
SrTiO₃
germanium
Ge
gallium arsenide
GaAs
silicon carbide
SiC
aluminum arsenide
AlAs
gallium nitride
GaN
cadmium telluride
CdTe
copper oxide
CuO
nickel oxide
NiO
first electrode metal
gallium manganese arsenide
GaMnAs
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view illustrating a tunneling field-effect transistor (TFET) including a graphene channel according to example embodiments; [0029]
FIG. 3 is a graph illustrating I-V characteristics of a TFET including a graphene channel according to example embodiments.
FIG. 3 is a graph illustrating I-V characteristics of a TFET including a graphene channel according to example embodiments.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
second energy barrier at semiconductor/electrode or semiconductor/graphene interface | ≤ 0.3 eV | semiconductor layer |
semiconductor layer thickness range | 1–30 nm | semiconductor layer |
graphene channel thickness | 1–4 layers | graphene |
Voltage | 9–9 V | — |
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