Patent
US 10,777,672GALLIUM NITRIDE TRANSISTORS FOR HIGH-VOLTAGE RADIO FREQUENCY SWITCHES
Han Wui Then
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,777,672Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a gallium nitride transistor in accordance with embodiments of the present disclosure. [0004]
FIG. 2 is a schematic diagram of a top-down view of a set of multi-gate gallium nitride transistor in accordance with embodiments of the present disclosure. …
FIG. 3. Additionally, the A l N layer 112 can act as part of the gate electrode and can enhance the electron mobility in the GaN channel. [0024] Also shown in
FIG. 4 is an interposer implementing one or more embodiments of the disclosure. [0007]
FIG. 5 is a computing device built in accordance with an embodiment of the disclosure. [0008]
FIG. 6 is a schematic diagram of an example circuit for a radio frequency frontend for a communication device in accordance with embodiments of the present …
FIG. 7A-C are a schematic diagrams of example radio frequency circuits with multi-gate transistors in accordance with embodiments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A multi-gate gallium nitride transistor, comprising: a gallium nitride layer; a drain electrode electrically coupled to the gallium nitride layer; a source electrode electrically coupled to the gallium nitride layer; a first gate electrode located adjacent to the drain electrode; a second gate electrode located between the first gate electrode and the source electrode; a polarization layer located between the first gate electrode and the second gate electrode; an isolation la y er, where the polarization la y er is between the isolation la y er and the gallium nitride la y er; a first dielectric material, having a first portion between the first gate electrode and the gallium nitride la y er, and having a second portion between the first gate electrode material and the isolation la y er; and a second dielectric material, having a first portion between the second gate electrode and the gallium nitride la y er, and having a second portion between the second gate electrode material and the isolation la y er. Currently amended
The gallium nitride transistor of claim 1, further comprising a two dimensional electron gas (2DEG) at an interface between the polarization layer and the gallium nitride layer, the 2DEG electrically coupling the first gate electrode and the second gate electrode. Original
The gallium nitride transistor of claim 1, further comprising a drain-side polarization layer located between the drain electrode and the first gate electrode. Currently amended
The gallium nitride transistor of claim 1, further comprising a source-side polarization layer located between the source electrode and the second gate electrode. Previously presented
The gallium nitride transistor of claim 1, further comprising an aluminum nitride layer disposed between the gallium nitride layer and the polarization layer. Previously presented
The gallium nitride transistor of claim 1, further comprising: a silicon nitride spacer in contact with sidewalls of the first gate electrode, and a silicon nitride in contact with sidewalls of the second gate electrode. Currently amended
The gallium nitride transistor of claim 1, wherein one or both of the drain electrode or the source electrode comprises a metal contact located on a doped semiconducting material. Previously presented
The gallium nitride transistor of claim 1, wherein the polarization layer comprises aluminum indium nitride or aluminum gallium nitride. Original
The gallium nitride transistor of claim 1, wherein the first dielectric material is not continuous with the second dielectric material. New
Canceled
13-25. Canceled
Canceled
A method for fabricating a multi-gate gallium nitride transistor on a gallium nitride layer, the method comprising: providing a drain electrode electrically coupled to the gallium nitride layer; providing a source electrode electrically coupled to the gallium nitride layer; providing a first gate electrode located adjacent to the drain electrode; providing a second gate electrode located between the first gate electrode and the source electrode; providing a polarization layer located between the first gate electrode and the second gate electrode; providing an isolation layer, where the polarization layer is between the isolation layer and the gallium nitride layer; providing a first dielectric material, having a first portion between the first gate electrode and the gallium nitride layer, and having a second portion between the first gate electrode material and the isolation layer; and providing a second dielectric material, having a first portion between the second gate electrode and the gallium nitride layer, and having a second portion between the second gate electrode material and the isolation layer. New
The method of claim 27, further comprising providing a drain-side polarization layer located between the drain electrode and the first gate electrode. New
The method of claim 27, further comprising providing a source-side polarization layer located between the source electrode and the second gate electrode. New
The method of claim 27, further comprising providing an aluminum nitride layer disposed between the gallium nitride layer and the polarization layer. New
The method of claim 27, further comprising providing: a silicon nitride spacer in contact with sidewalls of the first gate electrode, and a silicon nitride in contact with sidewalls of the second gate electrode. New
The method of claim 27, wherein one or both of the drain electrode or the source electrode comprises a metal contact located on a doped semiconducting material. New
The method of claim 27, wherein the doped semiconducting material comprises indium gallium nitride. New
The method of claim 27, wherein the polarization layer comprises aluminum indium nitride or aluminum gallium nitride. New
A computing device, comprising a multi-gate gallium nitride transistor, the multi-gate gallium nitride transistor comprising: a gallium nitride layer; a drain electrode electrically coupled to the gallium nitride layer; a source electrode electrically coupled to the gallium nitride layer; a first gate electrode located adjacent to the drain electrode; a second gate electrode located between the first gate electrode and the source electrode; a polarization layer located between the first gate electrode and the second gate electrode; an isolation layer, where the polarization layer is between the isolation layer and the gallium nitride layer; a first dielectric material, having a first portion between the first gate electrode and the gallium nitride layer, and having a second portion between the first gate electrode material and the isolation layer; and a second dielectric material, having a first portion between the second gate electrode and the gallium nitride layer, and having a second portion between the second gate electrode material and the isolation layer. New
The computing device of claim 35, wherein the computing device includes a processor, and the multi-gate gallium nitride transistor is included in the processor. New
The computing device of claim 35, wherein the multi-gate gallium nitride transistor further includes a drain-side polarization layer located between the drain electrode and the first gate electrode. New
Layer stacks claimed or described, ordered top of device to substrate.
multi-gate gallium nitride transistor
Materials described outside the worked examples.
gallium nitride
GaN
polarization layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic diagram of a gallium nitride transistor in accordance with embodiments of the present disclosure. [0004]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
2DEG Sheet Charge Density | 10000000000000–20000000000000 cm⁻² | GaN |
2DEG Sheet Charge Density | 1000000000000–5000000000000 cm⁻² | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
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US 10,777,672Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a gallium nitride transistor in accordance with embodiments of the present disclosure. [0004]
FIG. 2 is a schematic diagram of a top-down view of a set of multi-gate gallium nitride transistor in accordance with embodiments of the present disclosure. …
FIG. 3. Additionally, the A l N layer 112 can act as part of the gate electrode and can enhance the electron mobility in the GaN channel. [0024] Also shown in
FIG. 4 is an interposer implementing one or more embodiments of the disclosure. [0007]
FIG. 5 is a computing device built in accordance with an embodiment of the disclosure. [0008]
FIG. 6 is a schematic diagram of an example circuit for a radio frequency frontend for a communication device in accordance with embodiments of the present …
FIG. 7A-C are a schematic diagrams of example radio frequency circuits with multi-gate transistors in accordance with embodiments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A multi-gate gallium nitride transistor, comprising: a gallium nitride layer; a drain electrode electrically coupled to the gallium nitride layer; a source electrode electrically coupled to the gallium nitride layer; a first gate electrode located adjacent to the drain electrode; a second gate electrode located between the first gate electrode and the source electrode; a polarization layer located between the first gate electrode and the second gate electrode; an isolation la y er, where the polarization la y er is between the isolation la y er and the gallium nitride la y er; a first dielectric material, having a first portion between the first gate electrode and the gallium nitride la y er, and having a second portion between the first gate electrode material and the isolation la y er; and a second dielectric material, having a first portion between the second gate electrode and the gallium nitride la y er, and having a second portion between the second gate electrode material and the isolation la y er. Currently amended
The gallium nitride transistor of claim 1, further comprising a two dimensional electron gas (2DEG) at an interface between the polarization layer and the gallium nitride layer, the 2DEG electrically coupling the first gate electrode and the second gate electrode. Original
The gallium nitride transistor of claim 1, further comprising a drain-side polarization layer located between the drain electrode and the first gate electrode. Currently amended
The gallium nitride transistor of claim 1, further comprising a source-side polarization layer located between the source electrode and the second gate electrode. Previously presented
The gallium nitride transistor of claim 1, further comprising an aluminum nitride layer disposed between the gallium nitride layer and the polarization layer. Previously presented
The gallium nitride transistor of claim 1, further comprising: a silicon nitride spacer in contact with sidewalls of the first gate electrode, and a silicon nitride in contact with sidewalls of the second gate electrode. Currently amended
The gallium nitride transistor of claim 1, wherein one or both of the drain electrode or the source electrode comprises a metal contact located on a doped semiconducting material. Previously presented
The gallium nitride transistor of claim 1, wherein the polarization layer comprises aluminum indium nitride or aluminum gallium nitride. Original
The gallium nitride transistor of claim 1, wherein the first dielectric material is not continuous with the second dielectric material. New
Canceled
13-25. Canceled
Canceled
A method for fabricating a multi-gate gallium nitride transistor on a gallium nitride layer, the method comprising: providing a drain electrode electrically coupled to the gallium nitride layer; providing a source electrode electrically coupled to the gallium nitride layer; providing a first gate electrode located adjacent to the drain electrode; providing a second gate electrode located between the first gate electrode and the source electrode; providing a polarization layer located between the first gate electrode and the second gate electrode; providing an isolation layer, where the polarization layer is between the isolation layer and the gallium nitride layer; providing a first dielectric material, having a first portion between the first gate electrode and the gallium nitride layer, and having a second portion between the first gate electrode material and the isolation layer; and providing a second dielectric material, having a first portion between the second gate electrode and the gallium nitride layer, and having a second portion between the second gate electrode material and the isolation layer. New
The method of claim 27, further comprising providing a drain-side polarization layer located between the drain electrode and the first gate electrode. New
The method of claim 27, further comprising providing a source-side polarization layer located between the source electrode and the second gate electrode. New
The method of claim 27, further comprising providing an aluminum nitride layer disposed between the gallium nitride layer and the polarization layer. New
The method of claim 27, further comprising providing: a silicon nitride spacer in contact with sidewalls of the first gate electrode, and a silicon nitride in contact with sidewalls of the second gate electrode. New
The method of claim 27, wherein one or both of the drain electrode or the source electrode comprises a metal contact located on a doped semiconducting material. New
The method of claim 27, wherein the doped semiconducting material comprises indium gallium nitride. New
The method of claim 27, wherein the polarization layer comprises aluminum indium nitride or aluminum gallium nitride. New
A computing device, comprising a multi-gate gallium nitride transistor, the multi-gate gallium nitride transistor comprising: a gallium nitride layer; a drain electrode electrically coupled to the gallium nitride layer; a source electrode electrically coupled to the gallium nitride layer; a first gate electrode located adjacent to the drain electrode; a second gate electrode located between the first gate electrode and the source electrode; a polarization layer located between the first gate electrode and the second gate electrode; an isolation layer, where the polarization layer is between the isolation layer and the gallium nitride layer; a first dielectric material, having a first portion between the first gate electrode and the gallium nitride layer, and having a second portion between the first gate electrode material and the isolation layer; and a second dielectric material, having a first portion between the second gate electrode and the gallium nitride layer, and having a second portion between the second gate electrode material and the isolation layer. New
The computing device of claim 35, wherein the computing device includes a processor, and the multi-gate gallium nitride transistor is included in the processor. New
The computing device of claim 35, wherein the multi-gate gallium nitride transistor further includes a drain-side polarization layer located between the drain electrode and the first gate electrode. New
Layer stacks claimed or described, ordered top of device to substrate.
multi-gate gallium nitride transistor
Materials described outside the worked examples.
gallium nitride
GaN
polarization layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic diagram of a gallium nitride transistor in accordance with embodiments of the present disclosure. [0004]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
2DEG Sheet Charge Density | 10000000000000–20000000000000 cm⁻² | GaN |
2DEG Sheet Charge Density | 1000000000000–5000000000000 cm⁻² | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,777,672Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a gallium nitride transistor in accordance with embodiments of the present disclosure. [0004]
FIG. 2 is a schematic diagram of a top-down view of a set of multi-gate gallium nitride transistor in accordance with embodiments of the present disclosure. …
FIG. 3. Additionally, the A l N layer 112 can act as part of the gate electrode and can enhance the electron mobility in the GaN channel. [0024] Also shown in
FIG. 4 is an interposer implementing one or more embodiments of the disclosure. [0007]
FIG. 5 is a computing device built in accordance with an embodiment of the disclosure. [0008]
FIG. 6 is a schematic diagram of an example circuit for a radio frequency frontend for a communication device in accordance with embodiments of the present …
FIG. 7A-C are a schematic diagrams of example radio frequency circuits with multi-gate transistors in accordance with embodiments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A multi-gate gallium nitride transistor, comprising: a gallium nitride layer; a drain electrode electrically coupled to the gallium nitride layer; a source electrode electrically coupled to the gallium nitride layer; a first gate electrode located adjacent to the drain electrode; a second gate electrode located between the first gate electrode and the source electrode; a polarization layer located between the first gate electrode and the second gate electrode; an isolation la y er, where the polarization la y er is between the isolation la y er and the gallium nitride la y er; a first dielectric material, having a first portion between the first gate electrode and the gallium nitride la y er, and having a second portion between the first gate electrode material and the isolation la y er; and a second dielectric material, having a first portion between the second gate electrode and the gallium nitride la y er, and having a second portion between the second gate electrode material and the isolation la y er. Currently amended
The gallium nitride transistor of claim 1, further comprising a two dimensional electron gas (2DEG) at an interface between the polarization layer and the gallium nitride layer, the 2DEG electrically coupling the first gate electrode and the second gate electrode. Original
The gallium nitride transistor of claim 1, further comprising a drain-side polarization layer located between the drain electrode and the first gate electrode. Currently amended
The gallium nitride transistor of claim 1, further comprising a source-side polarization layer located between the source electrode and the second gate electrode. Previously presented
The gallium nitride transistor of claim 1, further comprising an aluminum nitride layer disposed between the gallium nitride layer and the polarization layer. Previously presented
The gallium nitride transistor of claim 1, further comprising: a silicon nitride spacer in contact with sidewalls of the first gate electrode, and a silicon nitride in contact with sidewalls of the second gate electrode. Currently amended
The gallium nitride transistor of claim 1, wherein one or both of the drain electrode or the source electrode comprises a metal contact located on a doped semiconducting material. Previously presented
The gallium nitride transistor of claim 1, wherein the polarization layer comprises aluminum indium nitride or aluminum gallium nitride. Original
The gallium nitride transistor of claim 1, wherein the first dielectric material is not continuous with the second dielectric material. New
Canceled
13-25. Canceled
Canceled
A method for fabricating a multi-gate gallium nitride transistor on a gallium nitride layer, the method comprising: providing a drain electrode electrically coupled to the gallium nitride layer; providing a source electrode electrically coupled to the gallium nitride layer; providing a first gate electrode located adjacent to the drain electrode; providing a second gate electrode located between the first gate electrode and the source electrode; providing a polarization layer located between the first gate electrode and the second gate electrode; providing an isolation layer, where the polarization layer is between the isolation layer and the gallium nitride layer; providing a first dielectric material, having a first portion between the first gate electrode and the gallium nitride layer, and having a second portion between the first gate electrode material and the isolation layer; and providing a second dielectric material, having a first portion between the second gate electrode and the gallium nitride layer, and having a second portion between the second gate electrode material and the isolation layer. New
The method of claim 27, further comprising providing a drain-side polarization layer located between the drain electrode and the first gate electrode. New
The method of claim 27, further comprising providing a source-side polarization layer located between the source electrode and the second gate electrode. New
The method of claim 27, further comprising providing an aluminum nitride layer disposed between the gallium nitride layer and the polarization layer. New
The method of claim 27, further comprising providing: a silicon nitride spacer in contact with sidewalls of the first gate electrode, and a silicon nitride in contact with sidewalls of the second gate electrode. New
The method of claim 27, wherein one or both of the drain electrode or the source electrode comprises a metal contact located on a doped semiconducting material. New
The method of claim 27, wherein the doped semiconducting material comprises indium gallium nitride. New
The method of claim 27, wherein the polarization layer comprises aluminum indium nitride or aluminum gallium nitride. New
A computing device, comprising a multi-gate gallium nitride transistor, the multi-gate gallium nitride transistor comprising: a gallium nitride layer; a drain electrode electrically coupled to the gallium nitride layer; a source electrode electrically coupled to the gallium nitride layer; a first gate electrode located adjacent to the drain electrode; a second gate electrode located between the first gate electrode and the source electrode; a polarization layer located between the first gate electrode and the second gate electrode; an isolation layer, where the polarization layer is between the isolation layer and the gallium nitride layer; a first dielectric material, having a first portion between the first gate electrode and the gallium nitride layer, and having a second portion between the first gate electrode material and the isolation layer; and a second dielectric material, having a first portion between the second gate electrode and the gallium nitride layer, and having a second portion between the second gate electrode material and the isolation layer. New
The computing device of claim 35, wherein the computing device includes a processor, and the multi-gate gallium nitride transistor is included in the processor. New
The computing device of claim 35, wherein the multi-gate gallium nitride transistor further includes a drain-side polarization layer located between the drain electrode and the first gate electrode. New
Layer stacks claimed or described, ordered top of device to substrate.
multi-gate gallium nitride transistor
Materials described outside the worked examples.
gallium nitride
GaN
polarization layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic diagram of a gallium nitride transistor in accordance with embodiments of the present disclosure. [0004]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
2DEG Sheet Charge Density | 10000000000000–20000000000000 cm⁻² | GaN |
2DEG Sheet Charge Density | 1000000000000–5000000000000 cm⁻² | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,777,672Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a gallium nitride transistor in accordance with embodiments of the present disclosure. [0004]
FIG. 2 is a schematic diagram of a top-down view of a set of multi-gate gallium nitride transistor in accordance with embodiments of the present disclosure. …
FIG. 3. Additionally, the A l N layer 112 can act as part of the gate electrode and can enhance the electron mobility in the GaN channel. [0024] Also shown in
FIG. 4 is an interposer implementing one or more embodiments of the disclosure. [0007]
FIG. 5 is a computing device built in accordance with an embodiment of the disclosure. [0008]
FIG. 6 is a schematic diagram of an example circuit for a radio frequency frontend for a communication device in accordance with embodiments of the present …
FIG. 7A-C are a schematic diagrams of example radio frequency circuits with multi-gate transistors in accordance with embodiments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A multi-gate gallium nitride transistor, comprising: a gallium nitride layer; a drain electrode electrically coupled to the gallium nitride layer; a source electrode electrically coupled to the gallium nitride layer; a first gate electrode located adjacent to the drain electrode; a second gate electrode located between the first gate electrode and the source electrode; a polarization layer located between the first gate electrode and the second gate electrode; an isolation la y er, where the polarization la y er is between the isolation la y er and the gallium nitride la y er; a first dielectric material, having a first portion between the first gate electrode and the gallium nitride la y er, and having a second portion between the first gate electrode material and the isolation la y er; and a second dielectric material, having a first portion between the second gate electrode and the gallium nitride la y er, and having a second portion between the second gate electrode material and the isolation la y er. Currently amended
The gallium nitride transistor of claim 1, further comprising a two dimensional electron gas (2DEG) at an interface between the polarization layer and the gallium nitride layer, the 2DEG electrically coupling the first gate electrode and the second gate electrode. Original
The gallium nitride transistor of claim 1, further comprising a drain-side polarization layer located between the drain electrode and the first gate electrode. Currently amended
The gallium nitride transistor of claim 1, further comprising a source-side polarization layer located between the source electrode and the second gate electrode. Previously presented
The gallium nitride transistor of claim 1, further comprising an aluminum nitride layer disposed between the gallium nitride layer and the polarization layer. Previously presented
The gallium nitride transistor of claim 1, further comprising: a silicon nitride spacer in contact with sidewalls of the first gate electrode, and a silicon nitride in contact with sidewalls of the second gate electrode. Currently amended
The gallium nitride transistor of claim 1, wherein one or both of the drain electrode or the source electrode comprises a metal contact located on a doped semiconducting material. Previously presented
The gallium nitride transistor of claim 1, wherein the polarization layer comprises aluminum indium nitride or aluminum gallium nitride. Original
The gallium nitride transistor of claim 1, wherein the first dielectric material is not continuous with the second dielectric material. New
Canceled
13-25. Canceled
Canceled
A method for fabricating a multi-gate gallium nitride transistor on a gallium nitride layer, the method comprising: providing a drain electrode electrically coupled to the gallium nitride layer; providing a source electrode electrically coupled to the gallium nitride layer; providing a first gate electrode located adjacent to the drain electrode; providing a second gate electrode located between the first gate electrode and the source electrode; providing a polarization layer located between the first gate electrode and the second gate electrode; providing an isolation layer, where the polarization layer is between the isolation layer and the gallium nitride layer; providing a first dielectric material, having a first portion between the first gate electrode and the gallium nitride layer, and having a second portion between the first gate electrode material and the isolation layer; and providing a second dielectric material, having a first portion between the second gate electrode and the gallium nitride layer, and having a second portion between the second gate electrode material and the isolation layer. New
The method of claim 27, further comprising providing a drain-side polarization layer located between the drain electrode and the first gate electrode. New
The method of claim 27, further comprising providing a source-side polarization layer located between the source electrode and the second gate electrode. New
The method of claim 27, further comprising providing an aluminum nitride layer disposed between the gallium nitride layer and the polarization layer. New
The method of claim 27, further comprising providing: a silicon nitride spacer in contact with sidewalls of the first gate electrode, and a silicon nitride in contact with sidewalls of the second gate electrode. New
The method of claim 27, wherein one or both of the drain electrode or the source electrode comprises a metal contact located on a doped semiconducting material. New
The method of claim 27, wherein the doped semiconducting material comprises indium gallium nitride. New
The method of claim 27, wherein the polarization layer comprises aluminum indium nitride or aluminum gallium nitride. New
A computing device, comprising a multi-gate gallium nitride transistor, the multi-gate gallium nitride transistor comprising: a gallium nitride layer; a drain electrode electrically coupled to the gallium nitride layer; a source electrode electrically coupled to the gallium nitride layer; a first gate electrode located adjacent to the drain electrode; a second gate electrode located between the first gate electrode and the source electrode; a polarization layer located between the first gate electrode and the second gate electrode; an isolation layer, where the polarization layer is between the isolation layer and the gallium nitride layer; a first dielectric material, having a first portion between the first gate electrode and the gallium nitride layer, and having a second portion between the first gate electrode material and the isolation layer; and a second dielectric material, having a first portion between the second gate electrode and the gallium nitride layer, and having a second portion between the second gate electrode material and the isolation layer. New
The computing device of claim 35, wherein the computing device includes a processor, and the multi-gate gallium nitride transistor is included in the processor. New
The computing device of claim 35, wherein the multi-gate gallium nitride transistor further includes a drain-side polarization layer located between the drain electrode and the first gate electrode. New
Layer stacks claimed or described, ordered top of device to substrate.
multi-gate gallium nitride transistor
Materials described outside the worked examples.
gallium nitride
GaN
polarization layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic diagram of a gallium nitride transistor in accordance with embodiments of the present disclosure. [0004]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
2DEG Sheet Charge Density | 10000000000000–20000000000000 cm⁻² | GaN |
2DEG Sheet Charge Density | 1000000000000–5000000000000 cm⁻² | — |
Related documents with shared materials, methods, properties, or citations.
computing device with multi-gate gallium nitride transistor
gate dielectric material
aluminum nitride
AlN
silicon nitride
Si₃N₄
indium gallium nitride
InGaN
aluminum indium nitride
AlInN
aluminum gallium nitride
AlGaN
aluminum indium nitride
AlxIn₁-xN (0.8 < x < 0.9)
aluminum gallium nitride
AlxGa₁-xN (0.1 < x < 0.5)
indium gallium nitride
InxGa₁-xN (5% < x < 15%)
titanium nitride
TiN
silicon dioxide
SiO₂
FIG. 2 is a schematic diagram of a top-down view of a set of multi-gate gallium nitride transistor in accordance with embodiments of the present disclosure. …
FIG. 3. Additionally, the A l N layer 112 can act as part of the gate electrode and can enhance the electron mobility in the GaN channel. [0024] Also shown in
FIG. 7A-C are a schematic diagrams of example radio frequency circuits with multi-gate transistors in accordance with embodiments of the present disclosure.
Thickness | 5–30 nm | — |
Thickness | 1–2 nm | — |
N-CHANNEL GALLIUM NITRIDE TRANSISTORS
computing device with multi-gate gallium nitride transistor
gate dielectric material
aluminum nitride
AlN
silicon nitride
Si₃N₄
indium gallium nitride
InGaN
aluminum indium nitride
AlInN
aluminum gallium nitride
AlGaN
aluminum indium nitride
AlxIn₁-xN (0.8 < x < 0.9)
aluminum gallium nitride
AlxGa₁-xN (0.1 < x < 0.5)
indium gallium nitride
InxGa₁-xN (5% < x < 15%)
titanium nitride
TiN
silicon dioxide
SiO₂
FIG. 2 is a schematic diagram of a top-down view of a set of multi-gate gallium nitride transistor in accordance with embodiments of the present disclosure. …
FIG. 3. Additionally, the A l N layer 112 can act as part of the gate electrode and can enhance the electron mobility in the GaN channel. [0024] Also shown in
FIG. 7A-C are a schematic diagrams of example radio frequency circuits with multi-gate transistors in accordance with embodiments of the present disclosure.
Thickness | 5–30 nm | — |
Thickness | 1–2 nm | — |
N-CHANNEL GALLIUM NITRIDE TRANSISTORS
computing device with multi-gate gallium nitride transistor
gate dielectric material
aluminum nitride
AlN
silicon nitride
Si₃N₄
indium gallium nitride
InGaN
aluminum indium nitride
AlInN
aluminum gallium nitride
AlGaN
aluminum indium nitride
AlxIn₁-xN (0.8 < x < 0.9)
aluminum gallium nitride
AlxGa₁-xN (0.1 < x < 0.5)
indium gallium nitride
InxGa₁-xN (5% < x < 15%)
titanium nitride
TiN
silicon dioxide
SiO₂
FIG. 2 is a schematic diagram of a top-down view of a set of multi-gate gallium nitride transistor in accordance with embodiments of the present disclosure. …
FIG. 3. Additionally, the A l N layer 112 can act as part of the gate electrode and can enhance the electron mobility in the GaN channel. [0024] Also shown in
FIG. 7A-C are a schematic diagrams of example radio frequency circuits with multi-gate transistors in accordance with embodiments of the present disclosure.
Thickness | 5–30 nm | — |
Thickness | 1–2 nm | — |
N-CHANNEL GALLIUM NITRIDE TRANSISTORS
computing device with multi-gate gallium nitride transistor
gate dielectric material
aluminum nitride
AlN
silicon nitride
Si₃N₄
indium gallium nitride
InGaN
aluminum indium nitride
AlInN
aluminum gallium nitride
AlGaN
aluminum indium nitride
AlxIn₁-xN (0.8 < x < 0.9)
aluminum gallium nitride
AlxGa₁-xN (0.1 < x < 0.5)
indium gallium nitride
InxGa₁-xN (5% < x < 15%)
titanium nitride
TiN
silicon dioxide
SiO₂
FIG. 2 is a schematic diagram of a top-down view of a set of multi-gate gallium nitride transistor in accordance with embodiments of the present disclosure. …
FIG. 3. Additionally, the A l N layer 112 can act as part of the gate electrode and can enhance the electron mobility in the GaN channel. [0024] Also shown in
FIG. 7A-C are a schematic diagrams of example radio frequency circuits with multi-gate transistors in accordance with embodiments of the present disclosure.
Thickness | 5–30 nm | — |
Thickness | 1–2 nm | — |