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Jump to sectionPatent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic structural diagram of a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of a cap layer provided by an embodiment of the present disclosure;
FIG. 3 is a flowchart of one preparation method for a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present …
FIG. 4 is a flow chart of another preparation method for a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN-based high electron mobility transistor epitaxial wafer, comprising: a substrate; and a plurality of layers further including a buffer layer, a high-resistance buffer layer, a channel layer, an AlGaN barrier layer, and a cap layer, the plurality of layers being successively stacked on the substrate; wherein: the cap layer comprises first sublayers and second sublayers, the first sublayers and the second sublay-ers being alternately arranged; the first sublayers are GaN layers; the second sublayers are InGaN layers, wherein a dopant concentration of In in the second sublayers ranges from 10 cm⁻³ to 104 cm⁻³; both the first sublayers and the second sublayers are doped with a main doping element; the main doping element is at least one of Be and Mg; the second sublayers are further doped with an auxil-iary doping element; and the auxiliary doping element is at least one of O, Mg, Si and Zn.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein dopant concentrations of the main doping element in the first sublayers and the second sublayers all range from 1*1019 cm⁻³ to 9*1021 cm⁻³.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein dopant concentrations of the auxiliary doping element in the second sublayers range from 1*1018 cm⁻³ to 5*1021 cm⁻³.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein a ratio of a dopant concen-tration of the main doping element to a dopant concentration of the auxiliary doping element in the second sublayers ranges from 1:1 to 5:1.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein the cap layer comprises n periods of alternately grown first sublayers and second sublayers, 1≤n≤10.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein a total thickness of the cap layer ranges from 50 nm to 150 nm.
A method for preparing a GaN-based high electron mobility transistor epitaxial wafer, comprising: providing a substrate; and successively growing a buffer layer, a high-resistance buffer layer, a channel layer, an AlGaN barrier layer, and a cap layer on the substrate, wherein: the cap layer comprises first sublayers and second sublayers which are grown alternately; the first sublayers are GaN layers; the second sublayers are InGaN layers wherein a dop-ant concentration of In in the second sublayers ranges from 10 cm⁻³ to 104 cm⁻³; both the first sublayers and the second sublayers are doped with a main doping element; the main doping element is at least one of Be and Mg; the second sublayers are further doped with an auxil-iary doping element; and the auxiliary doping element is at least one of O, Mg, Si and Zn.
The method of claim 8, wherein the step of successively growing the buffer layer, the high-resistance buffer layer, the channel layer, the AlGaN barrier layer and the cap layer on the substrate further comprises: growing the cap layer on the AlGaN barrier layer under conditions where a growth temperature ranges from 800° C. to 1050° C. and a growth pressure ranges from 50 torr to 600 torr.
The method of claim 8, further comprising: performing furnace annealing for the GaN-based high electron mobility transistor epitaxial wafer after grow-ing the cap layer.
The method of claim 8, wherein the cap layer com-prises n periods of alternately grown first sublayers and second sublayers, 1≤n≤10.
The method of claim 8, wherein a thickness of each of the first sublayers ranges from 5 nm to 20 nm, and a thickness of each of the second sublayers ranges from 10 nm to 30 nm.
An electronic device, comprising: a substrate; and a plurality of layers further including a buffer layer, a high-resistance buffer layer, a channel layer, an AlGaN barrier layer, and a cap layer, the plurality of layers being successively stacked on the substrate; wherein: the cap layer comprises first sublayers and second sublayers, the first sublayers and the second sublay-ers being alternately arranged; the first sublayers are GaN layers; the second sublayers are InGaN layers, wherein a dopant concentration of In in the second sublayers ranges from 10 cm⁻³ to 104 cm⁻³; both the first sublayers and the second sublayers are doped with a main doping element; the main doping element is at least one of Be and Mg; the second sublayers are further doped with an auxil-iary doping element; and the auxiliary doping element is at least one of O, Mg, Si and Zn.
The electronic device of claim 14, wherein dopant concentrations of the main doping element in the first sublayers and the second sublayers all range from 1*1019 cm⁻³ to 9*1021 cm⁻³.
The electronic device of claim 14, wherein dopant concentrations of the auxiliary doping element in the second sublayers range from 1*1018 cm⁻³ to 5*1021 cm⁻³.
The electronic device of claim 14, wherein a ratio of a dopant concentration of the main doping element to a dopant concentration of the auxiliary doping element in the second sublayers ranges from 1:1 to 5:1.
The electronic device of claim 14, wherein the cap layer comprises n periods of alternately grown first sublay-ers and second sublayers, 1≤n≤10.
The electronic device of claim 14, wherein a total thickness of the cap layer ranges from 50 nm to 150 nm.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based HEMT epitaxial wafer
Electronic device (GaN-based HEMT)
Materials described outside the worked examples.
GaN (first sublayers, cap layer)
GaN
InGaN (second sublayers, cap layer)
InGaN
AlGaN barrier layer
AlGaN
buffer layer
high-resistance buffer layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic structural diagram of a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present disclosure;
FIG. 3 is a flowchart of one preparation method for a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present …
FIG. 4 is a flow chart of another preparation method for a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50–150 nm | — |
Thickness | 100–300 nm | — |
Thickness | 0.5–1.5 um | — |
Thickness | 50–300 nm | — |
Thickness | 0.2–2 nm | — |
Thickness | 30–100 nm | — |
Temperature | 1000–1100 °C | — |
Pressure | 200–500 torr | — |
Temperature | 600–900 °C | — |
Pressure | 25–200 torr | — |
Temperature | 950–1050 °C | — |
Thickness | 5–20 nm | — |
Thickness | 10–30 nm | — |
Temperature | 1000–1200 °C | — |
Pressure | 100–500 torr | — |
Temperature | 800–1050 °C | — |
Pressure | 50–200 torr | — |
Temperature | 950–1000 °C | — |
Pressure | 100–200 torr | — |
Pressure | 50–600 torr | — |
Pressure | 50–300 torr | — |
Duration | 5–15 minutes | — |
Thickness | 3–104 cm | — |
Thickness | 3–103 cm | — |
Duration | 5–6 minutes | — |
Voltage | ≤ 0 V | — |
Thickness | ≤ 50 nm | — |
Voltage | ≥ 0 V | — |
Thickness | ≥ 150 nm | — |
Duration | 5–10 min | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 13
Cited non-patent literature · 4
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Explore this record
Jump to sectionPatent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic structural diagram of a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of a cap layer provided by an embodiment of the present disclosure;
FIG. 3 is a flowchart of one preparation method for a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present …
FIG. 4 is a flow chart of another preparation method for a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN-based high electron mobility transistor epitaxial wafer, comprising: a substrate; and a plurality of layers further including a buffer layer, a high-resistance buffer layer, a channel layer, an AlGaN barrier layer, and a cap layer, the plurality of layers being successively stacked on the substrate; wherein: the cap layer comprises first sublayers and second sublayers, the first sublayers and the second sublay-ers being alternately arranged; the first sublayers are GaN layers; the second sublayers are InGaN layers, wherein a dopant concentration of In in the second sublayers ranges from 10 cm⁻³ to 104 cm⁻³; both the first sublayers and the second sublayers are doped with a main doping element; the main doping element is at least one of Be and Mg; the second sublayers are further doped with an auxil-iary doping element; and the auxiliary doping element is at least one of O, Mg, Si and Zn.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein dopant concentrations of the main doping element in the first sublayers and the second sublayers all range from 1*1019 cm⁻³ to 9*1021 cm⁻³.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein dopant concentrations of the auxiliary doping element in the second sublayers range from 1*1018 cm⁻³ to 5*1021 cm⁻³.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein a ratio of a dopant concen-tration of the main doping element to a dopant concentration of the auxiliary doping element in the second sublayers ranges from 1:1 to 5:1.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein the cap layer comprises n periods of alternately grown first sublayers and second sublayers, 1≤n≤10.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein a total thickness of the cap layer ranges from 50 nm to 150 nm.
A method for preparing a GaN-based high electron mobility transistor epitaxial wafer, comprising: providing a substrate; and successively growing a buffer layer, a high-resistance buffer layer, a channel layer, an AlGaN barrier layer, and a cap layer on the substrate, wherein: the cap layer comprises first sublayers and second sublayers which are grown alternately; the first sublayers are GaN layers; the second sublayers are InGaN layers wherein a dop-ant concentration of In in the second sublayers ranges from 10 cm⁻³ to 104 cm⁻³; both the first sublayers and the second sublayers are doped with a main doping element; the main doping element is at least one of Be and Mg; the second sublayers are further doped with an auxil-iary doping element; and the auxiliary doping element is at least one of O, Mg, Si and Zn.
The method of claim 8, wherein the step of successively growing the buffer layer, the high-resistance buffer layer, the channel layer, the AlGaN barrier layer and the cap layer on the substrate further comprises: growing the cap layer on the AlGaN barrier layer under conditions where a growth temperature ranges from 800° C. to 1050° C. and a growth pressure ranges from 50 torr to 600 torr.
The method of claim 8, further comprising: performing furnace annealing for the GaN-based high electron mobility transistor epitaxial wafer after grow-ing the cap layer.
The method of claim 8, wherein the cap layer com-prises n periods of alternately grown first sublayers and second sublayers, 1≤n≤10.
The method of claim 8, wherein a thickness of each of the first sublayers ranges from 5 nm to 20 nm, and a thickness of each of the second sublayers ranges from 10 nm to 30 nm.
An electronic device, comprising: a substrate; and a plurality of layers further including a buffer layer, a high-resistance buffer layer, a channel layer, an AlGaN barrier layer, and a cap layer, the plurality of layers being successively stacked on the substrate; wherein: the cap layer comprises first sublayers and second sublayers, the first sublayers and the second sublay-ers being alternately arranged; the first sublayers are GaN layers; the second sublayers are InGaN layers, wherein a dopant concentration of In in the second sublayers ranges from 10 cm⁻³ to 104 cm⁻³; both the first sublayers and the second sublayers are doped with a main doping element; the main doping element is at least one of Be and Mg; the second sublayers are further doped with an auxil-iary doping element; and the auxiliary doping element is at least one of O, Mg, Si and Zn.
The electronic device of claim 14, wherein dopant concentrations of the main doping element in the first sublayers and the second sublayers all range from 1*1019 cm⁻³ to 9*1021 cm⁻³.
The electronic device of claim 14, wherein dopant concentrations of the auxiliary doping element in the second sublayers range from 1*1018 cm⁻³ to 5*1021 cm⁻³.
The electronic device of claim 14, wherein a ratio of a dopant concentration of the main doping element to a dopant concentration of the auxiliary doping element in the second sublayers ranges from 1:1 to 5:1.
The electronic device of claim 14, wherein the cap layer comprises n periods of alternately grown first sublay-ers and second sublayers, 1≤n≤10.
The electronic device of claim 14, wherein a total thickness of the cap layer ranges from 50 nm to 150 nm.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based HEMT epitaxial wafer
Electronic device (GaN-based HEMT)
Materials described outside the worked examples.
GaN (first sublayers, cap layer)
GaN
InGaN (second sublayers, cap layer)
InGaN
AlGaN barrier layer
AlGaN
buffer layer
high-resistance buffer layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic structural diagram of a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present disclosure;
FIG. 3 is a flowchart of one preparation method for a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present …
FIG. 4 is a flow chart of another preparation method for a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50–150 nm | — |
Thickness | 100–300 nm | — |
Thickness | 0.5–1.5 um | — |
Thickness | 50–300 nm | — |
Thickness | 0.2–2 nm | — |
Thickness | 30–100 nm | — |
Temperature | 1000–1100 °C | — |
Pressure | 200–500 torr | — |
Temperature | 600–900 °C | — |
Pressure | 25–200 torr | — |
Temperature | 950–1050 °C | — |
Thickness | 5–20 nm | — |
Thickness | 10–30 nm | — |
Temperature | 1000–1200 °C | — |
Pressure | 100–500 torr | — |
Temperature | 800–1050 °C | — |
Pressure | 50–200 torr | — |
Temperature | 950–1000 °C | — |
Pressure | 100–200 torr | — |
Pressure | 50–600 torr | — |
Pressure | 50–300 torr | — |
Duration | 5–15 minutes | — |
Thickness | 3–104 cm | — |
Thickness | 3–103 cm | — |
Duration | 5–6 minutes | — |
Voltage | ≤ 0 V | — |
Thickness | ≤ 50 nm | — |
Voltage | ≥ 0 V | — |
Thickness | ≥ 150 nm | — |
Duration | 5–10 min | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 13
Cited non-patent literature · 4
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Explore this record
Jump to sectionPatent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic structural diagram of a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of a cap layer provided by an embodiment of the present disclosure;
FIG. 3 is a flowchart of one preparation method for a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present …
FIG. 4 is a flow chart of another preparation method for a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN-based high electron mobility transistor epitaxial wafer, comprising: a substrate; and a plurality of layers further including a buffer layer, a high-resistance buffer layer, a channel layer, an AlGaN barrier layer, and a cap layer, the plurality of layers being successively stacked on the substrate; wherein: the cap layer comprises first sublayers and second sublayers, the first sublayers and the second sublay-ers being alternately arranged; the first sublayers are GaN layers; the second sublayers are InGaN layers, wherein a dopant concentration of In in the second sublayers ranges from 10 cm⁻³ to 104 cm⁻³; both the first sublayers and the second sublayers are doped with a main doping element; the main doping element is at least one of Be and Mg; the second sublayers are further doped with an auxil-iary doping element; and the auxiliary doping element is at least one of O, Mg, Si and Zn.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein dopant concentrations of the main doping element in the first sublayers and the second sublayers all range from 1*1019 cm⁻³ to 9*1021 cm⁻³.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein dopant concentrations of the auxiliary doping element in the second sublayers range from 1*1018 cm⁻³ to 5*1021 cm⁻³.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein a ratio of a dopant concen-tration of the main doping element to a dopant concentration of the auxiliary doping element in the second sublayers ranges from 1:1 to 5:1.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein the cap layer comprises n periods of alternately grown first sublayers and second sublayers, 1≤n≤10.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein a total thickness of the cap layer ranges from 50 nm to 150 nm.
A method for preparing a GaN-based high electron mobility transistor epitaxial wafer, comprising: providing a substrate; and successively growing a buffer layer, a high-resistance buffer layer, a channel layer, an AlGaN barrier layer, and a cap layer on the substrate, wherein: the cap layer comprises first sublayers and second sublayers which are grown alternately; the first sublayers are GaN layers; the second sublayers are InGaN layers wherein a dop-ant concentration of In in the second sublayers ranges from 10 cm⁻³ to 104 cm⁻³; both the first sublayers and the second sublayers are doped with a main doping element; the main doping element is at least one of Be and Mg; the second sublayers are further doped with an auxil-iary doping element; and the auxiliary doping element is at least one of O, Mg, Si and Zn.
The method of claim 8, wherein the step of successively growing the buffer layer, the high-resistance buffer layer, the channel layer, the AlGaN barrier layer and the cap layer on the substrate further comprises: growing the cap layer on the AlGaN barrier layer under conditions where a growth temperature ranges from 800° C. to 1050° C. and a growth pressure ranges from 50 torr to 600 torr.
The method of claim 8, further comprising: performing furnace annealing for the GaN-based high electron mobility transistor epitaxial wafer after grow-ing the cap layer.
The method of claim 8, wherein the cap layer com-prises n periods of alternately grown first sublayers and second sublayers, 1≤n≤10.
The method of claim 8, wherein a thickness of each of the first sublayers ranges from 5 nm to 20 nm, and a thickness of each of the second sublayers ranges from 10 nm to 30 nm.
An electronic device, comprising: a substrate; and a plurality of layers further including a buffer layer, a high-resistance buffer layer, a channel layer, an AlGaN barrier layer, and a cap layer, the plurality of layers being successively stacked on the substrate; wherein: the cap layer comprises first sublayers and second sublayers, the first sublayers and the second sublay-ers being alternately arranged; the first sublayers are GaN layers; the second sublayers are InGaN layers, wherein a dopant concentration of In in the second sublayers ranges from 10 cm⁻³ to 104 cm⁻³; both the first sublayers and the second sublayers are doped with a main doping element; the main doping element is at least one of Be and Mg; the second sublayers are further doped with an auxil-iary doping element; and the auxiliary doping element is at least one of O, Mg, Si and Zn.
The electronic device of claim 14, wherein dopant concentrations of the main doping element in the first sublayers and the second sublayers all range from 1*1019 cm⁻³ to 9*1021 cm⁻³.
The electronic device of claim 14, wherein dopant concentrations of the auxiliary doping element in the second sublayers range from 1*1018 cm⁻³ to 5*1021 cm⁻³.
The electronic device of claim 14, wherein a ratio of a dopant concentration of the main doping element to a dopant concentration of the auxiliary doping element in the second sublayers ranges from 1:1 to 5:1.
The electronic device of claim 14, wherein the cap layer comprises n periods of alternately grown first sublay-ers and second sublayers, 1≤n≤10.
The electronic device of claim 14, wherein a total thickness of the cap layer ranges from 50 nm to 150 nm.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based HEMT epitaxial wafer
Electronic device (GaN-based HEMT)
Materials described outside the worked examples.
GaN (first sublayers, cap layer)
GaN
InGaN (second sublayers, cap layer)
InGaN
AlGaN barrier layer
AlGaN
buffer layer
high-resistance buffer layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic structural diagram of a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present disclosure;
FIG. 3 is a flowchart of one preparation method for a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present …
FIG. 4 is a flow chart of another preparation method for a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50–150 nm | — |
Thickness | 100–300 nm | — |
Thickness | 0.5–1.5 um | — |
Thickness | 50–300 nm | — |
Thickness | 0.2–2 nm | — |
Thickness | 30–100 nm | — |
Temperature | 1000–1100 °C | — |
Pressure | 200–500 torr | — |
Temperature | 600–900 °C | — |
Pressure | 25–200 torr | — |
Temperature | 950–1050 °C | — |
Thickness | 5–20 nm | — |
Thickness | 10–30 nm | — |
Temperature | 1000–1200 °C | — |
Pressure | 100–500 torr | — |
Temperature | 800–1050 °C | — |
Pressure | 50–200 torr | — |
Temperature | 950–1000 °C | — |
Pressure | 100–200 torr | — |
Pressure | 50–600 torr | — |
Pressure | 50–300 torr | — |
Duration | 5–15 minutes | — |
Thickness | 3–104 cm | — |
Thickness | 3–103 cm | — |
Duration | 5–6 minutes | — |
Voltage | ≤ 0 V | — |
Thickness | ≤ 50 nm | — |
Voltage | ≥ 0 V | — |
Thickness | ≥ 150 nm | — |
Duration | 5–10 min | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 13
Cited non-patent literature · 4
Related documents with shared materials, methods, properties, or citations.
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Explore this record
Jump to sectionPatent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic structural diagram of a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of a cap layer provided by an embodiment of the present disclosure;
FIG. 3 is a flowchart of one preparation method for a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present …
FIG. 4 is a flow chart of another preparation method for a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN-based high electron mobility transistor epitaxial wafer, comprising: a substrate; and a plurality of layers further including a buffer layer, a high-resistance buffer layer, a channel layer, an AlGaN barrier layer, and a cap layer, the plurality of layers being successively stacked on the substrate; wherein: the cap layer comprises first sublayers and second sublayers, the first sublayers and the second sublay-ers being alternately arranged; the first sublayers are GaN layers; the second sublayers are InGaN layers, wherein a dopant concentration of In in the second sublayers ranges from 10 cm⁻³ to 104 cm⁻³; both the first sublayers and the second sublayers are doped with a main doping element; the main doping element is at least one of Be and Mg; the second sublayers are further doped with an auxil-iary doping element; and the auxiliary doping element is at least one of O, Mg, Si and Zn.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein dopant concentrations of the main doping element in the first sublayers and the second sublayers all range from 1*1019 cm⁻³ to 9*1021 cm⁻³.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein dopant concentrations of the auxiliary doping element in the second sublayers range from 1*1018 cm⁻³ to 5*1021 cm⁻³.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein a ratio of a dopant concen-tration of the main doping element to a dopant concentration of the auxiliary doping element in the second sublayers ranges from 1:1 to 5:1.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein the cap layer comprises n periods of alternately grown first sublayers and second sublayers, 1≤n≤10.
The GaN-based high electron mobility transistor epi-taxial wafer of claim 1, wherein a total thickness of the cap layer ranges from 50 nm to 150 nm.
A method for preparing a GaN-based high electron mobility transistor epitaxial wafer, comprising: providing a substrate; and successively growing a buffer layer, a high-resistance buffer layer, a channel layer, an AlGaN barrier layer, and a cap layer on the substrate, wherein: the cap layer comprises first sublayers and second sublayers which are grown alternately; the first sublayers are GaN layers; the second sublayers are InGaN layers wherein a dop-ant concentration of In in the second sublayers ranges from 10 cm⁻³ to 104 cm⁻³; both the first sublayers and the second sublayers are doped with a main doping element; the main doping element is at least one of Be and Mg; the second sublayers are further doped with an auxil-iary doping element; and the auxiliary doping element is at least one of O, Mg, Si and Zn.
The method of claim 8, wherein the step of successively growing the buffer layer, the high-resistance buffer layer, the channel layer, the AlGaN barrier layer and the cap layer on the substrate further comprises: growing the cap layer on the AlGaN barrier layer under conditions where a growth temperature ranges from 800° C. to 1050° C. and a growth pressure ranges from 50 torr to 600 torr.
The method of claim 8, further comprising: performing furnace annealing for the GaN-based high electron mobility transistor epitaxial wafer after grow-ing the cap layer.
The method of claim 8, wherein the cap layer com-prises n periods of alternately grown first sublayers and second sublayers, 1≤n≤10.
The method of claim 8, wherein a thickness of each of the first sublayers ranges from 5 nm to 20 nm, and a thickness of each of the second sublayers ranges from 10 nm to 30 nm.
An electronic device, comprising: a substrate; and a plurality of layers further including a buffer layer, a high-resistance buffer layer, a channel layer, an AlGaN barrier layer, and a cap layer, the plurality of layers being successively stacked on the substrate; wherein: the cap layer comprises first sublayers and second sublayers, the first sublayers and the second sublay-ers being alternately arranged; the first sublayers are GaN layers; the second sublayers are InGaN layers, wherein a dopant concentration of In in the second sublayers ranges from 10 cm⁻³ to 104 cm⁻³; both the first sublayers and the second sublayers are doped with a main doping element; the main doping element is at least one of Be and Mg; the second sublayers are further doped with an auxil-iary doping element; and the auxiliary doping element is at least one of O, Mg, Si and Zn.
The electronic device of claim 14, wherein dopant concentrations of the main doping element in the first sublayers and the second sublayers all range from 1*1019 cm⁻³ to 9*1021 cm⁻³.
The electronic device of claim 14, wherein dopant concentrations of the auxiliary doping element in the second sublayers range from 1*1018 cm⁻³ to 5*1021 cm⁻³.
The electronic device of claim 14, wherein a ratio of a dopant concentration of the main doping element to a dopant concentration of the auxiliary doping element in the second sublayers ranges from 1:1 to 5:1.
The electronic device of claim 14, wherein the cap layer comprises n periods of alternately grown first sublay-ers and second sublayers, 1≤n≤10.
The electronic device of claim 14, wherein a total thickness of the cap layer ranges from 50 nm to 150 nm.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based HEMT epitaxial wafer
Electronic device (GaN-based HEMT)
Materials described outside the worked examples.
GaN (first sublayers, cap layer)
GaN
InGaN (second sublayers, cap layer)
InGaN
AlGaN barrier layer
AlGaN
buffer layer
high-resistance buffer layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic structural diagram of a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present disclosure;
FIG. 3 is a flowchart of one preparation method for a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present …
FIG. 4 is a flow chart of another preparation method for a GaN-based high electron mobility transistor epitaxial wafer provided by an embodiment of the present …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50–150 nm | — |
Thickness | 100–300 nm | — |
Thickness | 0.5–1.5 um | — |
Thickness | 50–300 nm | — |
Thickness | 0.2–2 nm | — |
Thickness | 30–100 nm | — |
Temperature | 1000–1100 °C | — |
Pressure | 200–500 torr | — |
Temperature | 600–900 °C | — |
Pressure | 25–200 torr | — |
Temperature | 950–1050 °C | — |
Thickness | 5–20 nm | — |
Thickness | 10–30 nm | — |
Temperature | 1000–1200 °C | — |
Pressure | 100–500 torr | — |
Temperature | 800–1050 °C | — |
Pressure | 50–200 torr | — |
Temperature | 950–1000 °C | — |
Pressure | 100–200 torr | — |
Pressure | 50–600 torr | — |
Pressure | 50–300 torr | — |
Duration | 5–15 minutes | — |
Thickness | 3–104 cm | — |
Thickness | 3–103 cm | — |
Duration | 5–6 minutes | — |
Voltage | ≤ 0 V | — |
Thickness | ≤ 50 nm | — |
Voltage | ≥ 0 V | — |
Thickness | ≥ 150 nm | — |
Duration | 5–10 min | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 13
Cited non-patent literature · 4
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