Patent
US 9,111,851Enhancement Mode Gallium Nitride Based Transistor Device
Wei-Hung Kuo
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,111,851Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a single-layer p-type metal 10 oxide layer with extension parts according to a first embodiment.
Figure 1 A is a top view along the line I-I of
Figure 2 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a multi-layer p-type metal 15 oxide layer with extension parts according to a second embodiment.
Figure 3 is a schematic diagram illustrating a cross-sectional view of a recessed enhancement mode GaN-based transistor device having a multi-layer p-type metal oxide layer according to a third embodiment.
Figure 4 shows the current decay performance of the MOS-HEMT device 20 structure of Example 1 in which the gate region has a nanoporous pattern.
Figure 5 shows the current decay performance of the conventional MOS-HEMT.
Figure 6 shows the gate leakage current of each of the transistor having a recessed gate of Example 2 and the conventional transistor having a recessed Schottky 3 File: 44030usf gate.
Figure 7 shows the transfer I-V characteristic curve of each of the transistor having a recessed gate of Example 3 and the conventional transistor having a recessed Schottky gate.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An enhancement mode GaN-based transistor device, comprising: an epitaxial stacked layer, disposed on a substrate and comprising an undoped GaN layer, the e p itaxial stacked la y er having a continuous pattern and comprising a plurality of mesh holes separated from one another; a source layer and a drain layer, disposed on a surface of the epitaxial stacked layer; a p-type metal oxide layer, disposed between the source layer and the drain layer and comprising: one body part, disposed on the surface of the epitaxial stacked layer; and a plurality of extension columns, the extension columns being separated from one another, wherein the extension columns extend into the mesh holes of the epitaxial stacked la y er from the body part, and the extension columns are in contact with and surrounded by the epitaxial stacked la yerparts, wherein cach of the SVG 13686935.04-20-2015.I₈PQ₂₅₄₈PXXIFW3.CLM.1.svg 0.16 5.53 Black and white sepa r ated by the epita x ial sta cked laye r; and a gate layer, disposed on the p-type metal oxide layer.
The enhancement mode GaN-based transistor device of claim 1, 2 Customer No.: 3 1561 Docket No.: 44030-US-PA Application No.: 13/686,93 5 wherein the epitaxial stacked layer comp ri ses: a buffer layer; the undoped G aN layer, disposed on the buffer layer; and a barrier layer, disposed on the undoped G aN layer.
The enhancement mode G aN-based transistor device of claim 1, wherein the p-type metal oxide layer comprises a NiO y layer having a p-type carrier concentration of 1 x101 to 5 x1019/cm3, and 1 y 1.2.
The enhancement mode GaN-based transistor device of claim 1, wherein the p-type metal oxide layer comprises a plurality of NiO y layers with different p-type carrier concentrations, and 1 < y _ 1.2, and wherein one NiO y layer has a p-type carrier concentration of less than lX 1015/cm3, another NiO y layer has a p-type carrier concentration of lX 1015 to 1x 10 11/cm3, and yet another NiO y layer has a p-type carrier 3 Customer No.:31561 Docket No.: 44030-US-PA Application No.: 13/686,935 concentration of more than 1 x 1017/cm3.
The e nh ancement mode GaN-based transistor device of claim 1, further comprising a dielectric layer disposed between the p-type metal oxide layer and the source layer and between the p-type metal oxide layer and the drain layer.
2-3. canceled
canceled
(wit h drawn) An enhancement mode GaN-based transistor device, comprising: an epitaxial stacked layer, disposed on a substrate, comprising an undoped GaN layer and having a recess on a surface of the epitaxial stacked layer; a source layer and a drain layer, disposed on the surface of the epitaxial stacked layer beside the recess; a plurality of p-type metal oxide layers, disposed on the recess between the source layer and the drain layer and having different p-type carrier concentrations from each other; and a gate layer, disposed on the p-type metal oxide layers. withdrawn
The enhancement mode GaN-based transistor device of claim 12, wherein the P-type metal oxide layers comprise a plurality of NiO y layers with different p-type ca rr ier concentrations, and 1 y < 1.2, and wherein one NiO y layer has a p-type ca rri er concentration of less than 1 x1015/cm3, another NiO y layer has a p-type carrier concentration of lX 1015 to 1x 1017/cm3, and yet another NiO y layer has a p-type carrier concentration of more than lX 1017/cm3. withdrawn
The enhancement mode GaN-based transistor device of claim 12, wherein the epitaxial stacked layer comprises: a buffer layer; the undoped GaN layer, disposed on the buffer layer; and 4 Customer No.: 3 1561 Docket No.: 44030-US-PA Application No.: 13/686,935 a ba rr ier layer, disposed on the undoped GaN layer. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
enhancement mode GaN-based transistor (mesh-hole extension column structure)
Materials described outside the worked examples.
undoped GaN
GaN
p-type metal oxide
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a single-layer p-type metal 10 oxide layer with extension parts according to a first embodiment.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
P Type Carrier Concentration | 100000000000000000–50000000000000000000 | NiOy |
P Type Carrier Concentration Layer1 | ≤ 1000000000000000 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,111,851Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a single-layer p-type metal 10 oxide layer with extension parts according to a first embodiment.
Figure 1 A is a top view along the line I-I of
Figure 2 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a multi-layer p-type metal 15 oxide layer with extension parts according to a second embodiment.
Figure 3 is a schematic diagram illustrating a cross-sectional view of a recessed enhancement mode GaN-based transistor device having a multi-layer p-type metal oxide layer according to a third embodiment.
Figure 4 shows the current decay performance of the MOS-HEMT device 20 structure of Example 1 in which the gate region has a nanoporous pattern.
Figure 5 shows the current decay performance of the conventional MOS-HEMT.
Figure 6 shows the gate leakage current of each of the transistor having a recessed gate of Example 2 and the conventional transistor having a recessed Schottky 3 File: 44030usf gate.
Figure 7 shows the transfer I-V characteristic curve of each of the transistor having a recessed gate of Example 3 and the conventional transistor having a recessed Schottky gate.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An enhancement mode GaN-based transistor device, comprising: an epitaxial stacked layer, disposed on a substrate and comprising an undoped GaN layer, the e p itaxial stacked la y er having a continuous pattern and comprising a plurality of mesh holes separated from one another; a source layer and a drain layer, disposed on a surface of the epitaxial stacked layer; a p-type metal oxide layer, disposed between the source layer and the drain layer and comprising: one body part, disposed on the surface of the epitaxial stacked layer; and a plurality of extension columns, the extension columns being separated from one another, wherein the extension columns extend into the mesh holes of the epitaxial stacked la y er from the body part, and the extension columns are in contact with and surrounded by the epitaxial stacked la yerparts, wherein cach of the SVG 13686935.04-20-2015.I₈PQ₂₅₄₈PXXIFW3.CLM.1.svg 0.16 5.53 Black and white sepa r ated by the epita x ial sta cked laye r; and a gate layer, disposed on the p-type metal oxide layer.
The enhancement mode GaN-based transistor device of claim 1, 2 Customer No.: 3 1561 Docket No.: 44030-US-PA Application No.: 13/686,93 5 wherein the epitaxial stacked layer comp ri ses: a buffer layer; the undoped G aN layer, disposed on the buffer layer; and a barrier layer, disposed on the undoped G aN layer.
The enhancement mode G aN-based transistor device of claim 1, wherein the p-type metal oxide layer comprises a NiO y layer having a p-type carrier concentration of 1 x101 to 5 x1019/cm3, and 1 y 1.2.
The enhancement mode GaN-based transistor device of claim 1, wherein the p-type metal oxide layer comprises a plurality of NiO y layers with different p-type carrier concentrations, and 1 < y _ 1.2, and wherein one NiO y layer has a p-type carrier concentration of less than lX 1015/cm3, another NiO y layer has a p-type carrier concentration of lX 1015 to 1x 10 11/cm3, and yet another NiO y layer has a p-type carrier 3 Customer No.:31561 Docket No.: 44030-US-PA Application No.: 13/686,935 concentration of more than 1 x 1017/cm3.
The e nh ancement mode GaN-based transistor device of claim 1, further comprising a dielectric layer disposed between the p-type metal oxide layer and the source layer and between the p-type metal oxide layer and the drain layer.
2-3. canceled
canceled
(wit h drawn) An enhancement mode GaN-based transistor device, comprising: an epitaxial stacked layer, disposed on a substrate, comprising an undoped GaN layer and having a recess on a surface of the epitaxial stacked layer; a source layer and a drain layer, disposed on the surface of the epitaxial stacked layer beside the recess; a plurality of p-type metal oxide layers, disposed on the recess between the source layer and the drain layer and having different p-type carrier concentrations from each other; and a gate layer, disposed on the p-type metal oxide layers. withdrawn
The enhancement mode GaN-based transistor device of claim 12, wherein the P-type metal oxide layers comprise a plurality of NiO y layers with different p-type ca rr ier concentrations, and 1 y < 1.2, and wherein one NiO y layer has a p-type ca rri er concentration of less than 1 x1015/cm3, another NiO y layer has a p-type carrier concentration of lX 1015 to 1x 1017/cm3, and yet another NiO y layer has a p-type carrier concentration of more than lX 1017/cm3. withdrawn
The enhancement mode GaN-based transistor device of claim 12, wherein the epitaxial stacked layer comprises: a buffer layer; the undoped GaN layer, disposed on the buffer layer; and 4 Customer No.: 3 1561 Docket No.: 44030-US-PA Application No.: 13/686,935 a ba rr ier layer, disposed on the undoped GaN layer. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
enhancement mode GaN-based transistor (mesh-hole extension column structure)
Materials described outside the worked examples.
undoped GaN
GaN
p-type metal oxide
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a single-layer p-type metal 10 oxide layer with extension parts according to a first embodiment.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
P Type Carrier Concentration | 100000000000000000–50000000000000000000 | NiOy |
P Type Carrier Concentration Layer1 | ≤ 1000000000000000 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,111,851Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a single-layer p-type metal 10 oxide layer with extension parts according to a first embodiment.
Figure 1 A is a top view along the line I-I of
Figure 2 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a multi-layer p-type metal 15 oxide layer with extension parts according to a second embodiment.
Figure 3 is a schematic diagram illustrating a cross-sectional view of a recessed enhancement mode GaN-based transistor device having a multi-layer p-type metal oxide layer according to a third embodiment.
Figure 4 shows the current decay performance of the MOS-HEMT device 20 structure of Example 1 in which the gate region has a nanoporous pattern.
Figure 5 shows the current decay performance of the conventional MOS-HEMT.
Figure 6 shows the gate leakage current of each of the transistor having a recessed gate of Example 2 and the conventional transistor having a recessed Schottky 3 File: 44030usf gate.
Figure 7 shows the transfer I-V characteristic curve of each of the transistor having a recessed gate of Example 3 and the conventional transistor having a recessed Schottky gate.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An enhancement mode GaN-based transistor device, comprising: an epitaxial stacked layer, disposed on a substrate and comprising an undoped GaN layer, the e p itaxial stacked la y er having a continuous pattern and comprising a plurality of mesh holes separated from one another; a source layer and a drain layer, disposed on a surface of the epitaxial stacked layer; a p-type metal oxide layer, disposed between the source layer and the drain layer and comprising: one body part, disposed on the surface of the epitaxial stacked layer; and a plurality of extension columns, the extension columns being separated from one another, wherein the extension columns extend into the mesh holes of the epitaxial stacked la y er from the body part, and the extension columns are in contact with and surrounded by the epitaxial stacked la yerparts, wherein cach of the SVG 13686935.04-20-2015.I₈PQ₂₅₄₈PXXIFW3.CLM.1.svg 0.16 5.53 Black and white sepa r ated by the epita x ial sta cked laye r; and a gate layer, disposed on the p-type metal oxide layer.
The enhancement mode GaN-based transistor device of claim 1, 2 Customer No.: 3 1561 Docket No.: 44030-US-PA Application No.: 13/686,93 5 wherein the epitaxial stacked layer comp ri ses: a buffer layer; the undoped G aN layer, disposed on the buffer layer; and a barrier layer, disposed on the undoped G aN layer.
The enhancement mode G aN-based transistor device of claim 1, wherein the p-type metal oxide layer comprises a NiO y layer having a p-type carrier concentration of 1 x101 to 5 x1019/cm3, and 1 y 1.2.
The enhancement mode GaN-based transistor device of claim 1, wherein the p-type metal oxide layer comprises a plurality of NiO y layers with different p-type carrier concentrations, and 1 < y _ 1.2, and wherein one NiO y layer has a p-type carrier concentration of less than lX 1015/cm3, another NiO y layer has a p-type carrier concentration of lX 1015 to 1x 10 11/cm3, and yet another NiO y layer has a p-type carrier 3 Customer No.:31561 Docket No.: 44030-US-PA Application No.: 13/686,935 concentration of more than 1 x 1017/cm3.
The e nh ancement mode GaN-based transistor device of claim 1, further comprising a dielectric layer disposed between the p-type metal oxide layer and the source layer and between the p-type metal oxide layer and the drain layer.
2-3. canceled
canceled
(wit h drawn) An enhancement mode GaN-based transistor device, comprising: an epitaxial stacked layer, disposed on a substrate, comprising an undoped GaN layer and having a recess on a surface of the epitaxial stacked layer; a source layer and a drain layer, disposed on the surface of the epitaxial stacked layer beside the recess; a plurality of p-type metal oxide layers, disposed on the recess between the source layer and the drain layer and having different p-type carrier concentrations from each other; and a gate layer, disposed on the p-type metal oxide layers. withdrawn
The enhancement mode GaN-based transistor device of claim 12, wherein the P-type metal oxide layers comprise a plurality of NiO y layers with different p-type ca rr ier concentrations, and 1 y < 1.2, and wherein one NiO y layer has a p-type ca rri er concentration of less than 1 x1015/cm3, another NiO y layer has a p-type carrier concentration of lX 1015 to 1x 1017/cm3, and yet another NiO y layer has a p-type carrier concentration of more than lX 1017/cm3. withdrawn
The enhancement mode GaN-based transistor device of claim 12, wherein the epitaxial stacked layer comprises: a buffer layer; the undoped GaN layer, disposed on the buffer layer; and 4 Customer No.: 3 1561 Docket No.: 44030-US-PA Application No.: 13/686,935 a ba rr ier layer, disposed on the undoped GaN layer. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
enhancement mode GaN-based transistor (mesh-hole extension column structure)
Materials described outside the worked examples.
undoped GaN
GaN
p-type metal oxide
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a single-layer p-type metal 10 oxide layer with extension parts according to a first embodiment.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
P Type Carrier Concentration | 100000000000000000–50000000000000000000 | NiOy |
P Type Carrier Concentration Layer1 | ≤ 1000000000000000 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,111,851Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a single-layer p-type metal 10 oxide layer with extension parts according to a first embodiment.
Figure 1 A is a top view along the line I-I of
Figure 2 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a multi-layer p-type metal 15 oxide layer with extension parts according to a second embodiment.
Figure 3 is a schematic diagram illustrating a cross-sectional view of a recessed enhancement mode GaN-based transistor device having a multi-layer p-type metal oxide layer according to a third embodiment.
Figure 4 shows the current decay performance of the MOS-HEMT device 20 structure of Example 1 in which the gate region has a nanoporous pattern.
Figure 5 shows the current decay performance of the conventional MOS-HEMT.
Figure 6 shows the gate leakage current of each of the transistor having a recessed gate of Example 2 and the conventional transistor having a recessed Schottky 3 File: 44030usf gate.
Figure 7 shows the transfer I-V characteristic curve of each of the transistor having a recessed gate of Example 3 and the conventional transistor having a recessed Schottky gate.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An enhancement mode GaN-based transistor device, comprising: an epitaxial stacked layer, disposed on a substrate and comprising an undoped GaN layer, the e p itaxial stacked la y er having a continuous pattern and comprising a plurality of mesh holes separated from one another; a source layer and a drain layer, disposed on a surface of the epitaxial stacked layer; a p-type metal oxide layer, disposed between the source layer and the drain layer and comprising: one body part, disposed on the surface of the epitaxial stacked layer; and a plurality of extension columns, the extension columns being separated from one another, wherein the extension columns extend into the mesh holes of the epitaxial stacked la y er from the body part, and the extension columns are in contact with and surrounded by the epitaxial stacked la yerparts, wherein cach of the SVG 13686935.04-20-2015.I₈PQ₂₅₄₈PXXIFW3.CLM.1.svg 0.16 5.53 Black and white sepa r ated by the epita x ial sta cked laye r; and a gate layer, disposed on the p-type metal oxide layer.
The enhancement mode GaN-based transistor device of claim 1, 2 Customer No.: 3 1561 Docket No.: 44030-US-PA Application No.: 13/686,93 5 wherein the epitaxial stacked layer comp ri ses: a buffer layer; the undoped G aN layer, disposed on the buffer layer; and a barrier layer, disposed on the undoped G aN layer.
The enhancement mode G aN-based transistor device of claim 1, wherein the p-type metal oxide layer comprises a NiO y layer having a p-type carrier concentration of 1 x101 to 5 x1019/cm3, and 1 y 1.2.
The enhancement mode GaN-based transistor device of claim 1, wherein the p-type metal oxide layer comprises a plurality of NiO y layers with different p-type carrier concentrations, and 1 < y _ 1.2, and wherein one NiO y layer has a p-type carrier concentration of less than lX 1015/cm3, another NiO y layer has a p-type carrier concentration of lX 1015 to 1x 10 11/cm3, and yet another NiO y layer has a p-type carrier 3 Customer No.:31561 Docket No.: 44030-US-PA Application No.: 13/686,935 concentration of more than 1 x 1017/cm3.
The e nh ancement mode GaN-based transistor device of claim 1, further comprising a dielectric layer disposed between the p-type metal oxide layer and the source layer and between the p-type metal oxide layer and the drain layer.
2-3. canceled
canceled
(wit h drawn) An enhancement mode GaN-based transistor device, comprising: an epitaxial stacked layer, disposed on a substrate, comprising an undoped GaN layer and having a recess on a surface of the epitaxial stacked layer; a source layer and a drain layer, disposed on the surface of the epitaxial stacked layer beside the recess; a plurality of p-type metal oxide layers, disposed on the recess between the source layer and the drain layer and having different p-type carrier concentrations from each other; and a gate layer, disposed on the p-type metal oxide layers. withdrawn
The enhancement mode GaN-based transistor device of claim 12, wherein the P-type metal oxide layers comprise a plurality of NiO y layers with different p-type ca rr ier concentrations, and 1 y < 1.2, and wherein one NiO y layer has a p-type ca rri er concentration of less than 1 x1015/cm3, another NiO y layer has a p-type carrier concentration of lX 1015 to 1x 1017/cm3, and yet another NiO y layer has a p-type carrier concentration of more than lX 1017/cm3. withdrawn
The enhancement mode GaN-based transistor device of claim 12, wherein the epitaxial stacked layer comprises: a buffer layer; the undoped GaN layer, disposed on the buffer layer; and 4 Customer No.: 3 1561 Docket No.: 44030-US-PA Application No.: 13/686,935 a ba rr ier layer, disposed on the undoped GaN layer. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
enhancement mode GaN-based transistor (mesh-hole extension column structure)
Materials described outside the worked examples.
undoped GaN
GaN
p-type metal oxide
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a single-layer p-type metal 10 oxide layer with extension parts according to a first embodiment.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
P Type Carrier Concentration | 100000000000000000–50000000000000000000 | NiOy |
P Type Carrier Concentration Layer1 | ≤ 1000000000000000 |
Related documents with shared materials, methods, properties, or citations.
enhancement mode GaN-based transistor (recess with multiple p-type oxide layers, withdrawn)
epitaxial stacked layer (GaN-based)
buffer layer
barrier layer
AlN-based buffer layer
AlN
undoped AlxGa₁-xN barrier layer
AlxGa₁-xN
NiOy p-type metal oxide layer
NiOy
dielectric layer
SiO₂ dielectric
SiO₂
Si₃N₄ dielectric
Si₃N₄
Figure 2 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a multi-layer p-type metal 15 oxide layer with extension parts according to a second embodiment.
Figure 3 is a schematic diagram illustrating a cross-sectional view of a recessed enhancement mode GaN-based transistor device having a multi-layer p-type metal oxide layer according to a third embodiment.
Figure 4 shows the current decay performance of the MOS-HEMT device 20 structure of Example 1 in which the gate region has a nanoporous pattern.
Figure 5 shows the current decay performance of the conventional MOS-HEMT.
Figure 6 shows the gate leakage current of each of the transistor having a recessed gate of Example 2 and the conventional transistor having a recessed Schottky 3 File: 44030usf gate.
Figure 7 shows the transfer I-V characteristic curve of each of the transistor having a recessed gate of Example 3 and the conventional transistor having a recessed Schottky gate.
P Type Carrier Concentration Layer2 | 1000000000000000–100000000000000000 | NiOy |
P Type Carrier Concentration Layer3 | ≥ 100000000000000000 | NiOy |
Thickness | 5–40 nm | — |
Thickness | 5–50 nm | — |
Thickness | 50–500 nm | — |
Duration | 1–30 minutes | — |
Thickness | 1–200 nm | — |
Thickness | 10–500 nm | — |
Temperature | 600–1000 °C | — |
enhancement mode GaN-based transistor (recess with multiple p-type oxide layers, withdrawn)
epitaxial stacked layer (GaN-based)
buffer layer
barrier layer
AlN-based buffer layer
AlN
undoped AlxGa₁-xN barrier layer
AlxGa₁-xN
NiOy p-type metal oxide layer
NiOy
dielectric layer
SiO₂ dielectric
SiO₂
Si₃N₄ dielectric
Si₃N₄
Figure 2 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a multi-layer p-type metal 15 oxide layer with extension parts according to a second embodiment.
Figure 3 is a schematic diagram illustrating a cross-sectional view of a recessed enhancement mode GaN-based transistor device having a multi-layer p-type metal oxide layer according to a third embodiment.
Figure 4 shows the current decay performance of the MOS-HEMT device 20 structure of Example 1 in which the gate region has a nanoporous pattern.
Figure 5 shows the current decay performance of the conventional MOS-HEMT.
Figure 6 shows the gate leakage current of each of the transistor having a recessed gate of Example 2 and the conventional transistor having a recessed Schottky 3 File: 44030usf gate.
Figure 7 shows the transfer I-V characteristic curve of each of the transistor having a recessed gate of Example 3 and the conventional transistor having a recessed Schottky gate.
P Type Carrier Concentration Layer2 | 1000000000000000–100000000000000000 | NiOy |
P Type Carrier Concentration Layer3 | ≥ 100000000000000000 | NiOy |
Thickness | 5–40 nm | — |
Thickness | 5–50 nm | — |
Thickness | 50–500 nm | — |
Duration | 1–30 minutes | — |
Thickness | 1–200 nm | — |
Thickness | 10–500 nm | — |
Temperature | 600–1000 °C | — |
enhancement mode GaN-based transistor (recess with multiple p-type oxide layers, withdrawn)
epitaxial stacked layer (GaN-based)
buffer layer
barrier layer
AlN-based buffer layer
AlN
undoped AlxGa₁-xN barrier layer
AlxGa₁-xN
NiOy p-type metal oxide layer
NiOy
dielectric layer
SiO₂ dielectric
SiO₂
Si₃N₄ dielectric
Si₃N₄
Figure 2 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a multi-layer p-type metal 15 oxide layer with extension parts according to a second embodiment.
Figure 3 is a schematic diagram illustrating a cross-sectional view of a recessed enhancement mode GaN-based transistor device having a multi-layer p-type metal oxide layer according to a third embodiment.
Figure 4 shows the current decay performance of the MOS-HEMT device 20 structure of Example 1 in which the gate region has a nanoporous pattern.
Figure 5 shows the current decay performance of the conventional MOS-HEMT.
Figure 6 shows the gate leakage current of each of the transistor having a recessed gate of Example 2 and the conventional transistor having a recessed Schottky 3 File: 44030usf gate.
Figure 7 shows the transfer I-V characteristic curve of each of the transistor having a recessed gate of Example 3 and the conventional transistor having a recessed Schottky gate.
P Type Carrier Concentration Layer2 | 1000000000000000–100000000000000000 | NiOy |
P Type Carrier Concentration Layer3 | ≥ 100000000000000000 | NiOy |
Thickness | 5–40 nm | — |
Thickness | 5–50 nm | — |
Thickness | 50–500 nm | — |
Duration | 1–30 minutes | — |
Thickness | 1–200 nm | — |
Thickness | 10–500 nm | — |
Temperature | 600–1000 °C | — |
enhancement mode GaN-based transistor (recess with multiple p-type oxide layers, withdrawn)
epitaxial stacked layer (GaN-based)
buffer layer
barrier layer
AlN-based buffer layer
AlN
undoped AlxGa₁-xN barrier layer
AlxGa₁-xN
NiOy p-type metal oxide layer
NiOy
dielectric layer
SiO₂ dielectric
SiO₂
Si₃N₄ dielectric
Si₃N₄
Figure 2 is a schematic diagram illustrating a cross-sectional view of an enhancement mode GaN-based transistor device having a multi-layer p-type metal 15 oxide layer with extension parts according to a second embodiment.
Figure 3 is a schematic diagram illustrating a cross-sectional view of a recessed enhancement mode GaN-based transistor device having a multi-layer p-type metal oxide layer according to a third embodiment.
Figure 4 shows the current decay performance of the MOS-HEMT device 20 structure of Example 1 in which the gate region has a nanoporous pattern.
Figure 5 shows the current decay performance of the conventional MOS-HEMT.
Figure 6 shows the gate leakage current of each of the transistor having a recessed gate of Example 2 and the conventional transistor having a recessed Schottky 3 File: 44030usf gate.
Figure 7 shows the transfer I-V characteristic curve of each of the transistor having a recessed gate of Example 3 and the conventional transistor having a recessed Schottky gate.
P Type Carrier Concentration Layer2 | 1000000000000000–100000000000000000 | NiOy |
P Type Carrier Concentration Layer3 | ≥ 100000000000000000 | NiOy |
Thickness | 5–40 nm | — |
Thickness | 5–50 nm | — |
Thickness | 50–500 nm | — |
Duration | 1–30 minutes | — |
Thickness | 1–200 nm | — |
Thickness | 10–500 nm | — |
Temperature | 600–1000 °C | — |