GAN DEVICES ON ENGINEERED SILICON SUBSTRATES

Sansaptak DASGUPTA

Patent

Atlas literature

Patent

US 10,692,839

GAN DEVICES ON ENGINEERED SILICON SUBSTRATES

Sansaptak DASGUPTA

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 1 is a ﬂow diagram illustrating back-side processing of GOS substrates and integrating devices made on such substrates, in accordance with embodiments. …

FIG. 2

FIG. 2. In some embodiments, silicon substrate 205 is monocrystalline having a predetermined crystal orientation. Crystallographic orientation of a …

FIG. 3

FIG. 3 is a ﬂow diagram illustrating back-side processing of GOS substrates and integrating devices made on such substrates, in accordance with some …

FIG. 4

FIG. 4, back-side trenches 441 may have a wide range of dimensions. In exemplary embodiments, back-side trenches 441 have critical lateral dimensions in the …

FIG. 5

FIG. 5 B, GOS substrate 505 has a back-side 206 comprising a grid of back-side trenches 441 extending over a majority of the substrate area. The grid pattern …

FIG. 6

FIG. 6B. As further shown in

FIG. 7

FIG. 7 illustrates a mobile computing platform and a data server machine employing a 3D IC including silicon FETs on a thin silicon substrate and GaN HFETs on …

FIG. 8

FIG. 8 is a functional block diagram of an electronic computing device, in accordance with an embodiment of the present invention. DETAILED DESCRIPTION One or …

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

10 independent · 11 dependent

21
IndependentIII-N semiconductor materialGaNfirst stress-tuning materialsecond stress-tuning materialsemiconductor device structure with III-N and Si-MOSFET regions and dual back-side stress-tuning
A semiconductor device structure, comprising: one or more single-crystalline I II -N semiconductor material layers in a ﬁrst region of over a front-side of a substrate comprising silicon; one or more silicon-channeled MOSFETs in a second region over the front-side of the substrate; a microelectronic device over the front-side of the substrate and incorporating at least one of the III -N semiconductor material layers; and a ﬁrst stress-tuning material within a ﬁrst trench on a back-side of the substrate opposite the ﬁrst region and a second stress-tuning material, diﬀerent than the ﬁrst stress-tuning material, within a second trench on a back-side of the substrate opposite the second region, at least the ﬁrst stress-tuning material to counter stress in the substrate induced by the I II -N semiconductor material layers. Currently amended
1. 22
  Dependent← claim 21first stress-tuning materialsemiconductor device structure with III-N and Si-MOSFET regions and dual back-side stress-tuning
  The device structure of claim 21, wherein the ﬁrst stress-tuning material has a linear coeﬃcient of thermal expansion between 4 and 6 ppm/°C. Currently amended
2. 24
  Dependent← claim 21III-N semiconductor materialGaNfirst stress-tuning materialsemiconductor device structure with III-N and Si-MOSFET regions and dual back-side stress-tuning
  The device structure of claim 21, wherein: the substrate has a thickness of at least 775 m; the I II -N semiconductor material layers include a layer comprising Ga and N that has a thickness of at least 1 m; and the ﬁrst stress-tuning material has a thickness of at least 0.25 m. Currently amended
3. 41
  Dependent← claim 21first stress-tuning materialsecond stress-tuning materialsemiconductor device structure with III-N and Si-MOSFET regions and dual back-side stress-tuning
  The semiconductor device structure of claim 21, wherein the ﬁrst stress tuning material induces more stress within the ﬁrst region than the second stress tuning material induces within the second region. New
4. 42
  Dependent← claim 21second stress-tuning materialsemiconductor device structure with III-N and Si-MOSFET regions and dual back-side stress-tuning
  The semiconductor device structure of claim 21, wherein the second stress tuning material induces a stress within the second region. New
25
Independent
-27.. Canceled
27
Independent
Canceled
28
IndependentIII-N semiconductor materialGaNstress-tuning metalGOS semiconductor device structure with metal stress-tuning trench and through-substrate via
A semiconductor device structure, comprising: one or more single-crystalline I II -N semiconductor material layers over a front-side of a substrate comprising silicon; a microelectronic device over the front-side of the substrate and incorporating at least one of the III -N semiconductor material layers; and a stress-tuning material located within a trench in a back-side of the substrate that counters stress in the substrate induced by the I II -N semiconductor material layers, wherein: the stress-tuning material is a metal; the trench extends into the substrate from the back-side to a depth of at least 50 m; and a metal-ﬁlled via extends through the substrate between the front-side and the backside, and the metal-ﬁlled via intersects the metal stress-tuning material. Currently amended
29
IndependentIII-N semiconductor materialGaNstress-tuning metalCMOS die with silicon MOSFETs on thin silicon substratehigh voltage die with GaN HEMTs on GOS substrate with back-side stress-tuning metal
A three-dimensional integrated circuit (3 D IC), comprising: a CMOS die comprising plurality of silicon MOSFETs disposed on a ﬁrst substrate comprising silicon; a high voltage die stacked with the CMOS die, the high voltage die comprising a plurality of III- N-channeled high electron mobility transistors (HEMTs) disposed on a GaN-On-Silicon (GOS) substrate having one or more single-crystalline I II -N semiconductor material layers, wherein: the GOS substrate includes a second substrate comprising silicon, the second substrate of greater thickness than the ﬁrst substrate; and a stress-tuning material is disposed on a back-side of the GOS substrate, opposite the HEMTs, that counters stress in the GOS substrate induced by the I II-N semiconductor material layers. Currently amended
1. 30
  Dependent← claim 29stress-tuning metalCMOS die with silicon MOSFETs on thin silicon substratehigh voltage die with GaN HEMTs on GOS substrate with back-side stress-tuning metal
  The 3D IC of claim 29, wherein: the stress-tuning material is a metal within a trench embedded in the back-side of the GOS substrate; and a bump metal joins the stress-tuning material to the CMOS die or to a heat sink. Previously presented
2. 32
  Dependent← claim 29CMOS die with silicon MOSFETs on thin silicon substratehigh voltage die with GaN HEMTs on GOS substrate with back-side stress-tuning metal
  The 3D IC of claim 29, wherein: the ﬁrst substrate is bonded to the high voltage die on a side of the second substrate opposite the stress-tuning layer; and a through via extends through the ﬁrst substrate and couples with the high voltage die. Previously presented
3. 33
  Dependent← claim 29stress-tuning metalCMOS die with silicon MOSFETs on thin silicon substratehigh voltage die with GaN HEMTs on GOS substrate with back-side stress-tuning metal
  The 3D IC of claim 29, wherein: the stress-tuning material has a linear coeﬃcient of thermal expansion between 4 and 6 ppm/°C; the second substrate has a thickness of at least 775 m; and the ﬁrst substrate has a thickness less than 100 m. Previously presented
34
Independent
-35. Cancelled Canceled
35
Independent
Canceled
36
IndependentIII-N semiconductor materialGaNstress-tuning metalGOS semiconductor device structure with metal stress-tuning trench and through-substrate via
A method of forming a GaN-On-Silicon (GOS) structure, the method comprising: receiving a substrate having a diameter of at least 300 mm, wherein the substrate comprises monocrystalline silicon; etching a trench on a back-side of the substrate; depositing a stress-tuning material into the trench, the stress tuning material comprising a metal and inducing a ﬁrst stress on the silicon substrate; epitaxially growing on a front-side of the substrate one or more single-crystalline III-N material layers including a GaN layer having a thickness of at least 1 [a m, the 111-N material layers inducing a second stress on the substrate, that is countered, at least in part, by the ﬁrst stress, forming a microelectronic device over the front-side of the substrate, the microelectronic device incorporating at least one of the I II -N semiconductor material layers; and forming an electrical interconnect through the substrate to the microelectronic device, wherein the electrical interconnect comprises the stress tuning material. Currently amended
1. 38
  Dependent← claim 36TiWTiWNiV
  The method of claim 36, wherein depositing the stress-tuning material further comprises depositing at least one of titanium, tungsten, TiW, chromium, or nickel-vanadium. Currently amended
37
Independent
. Canceled
39
IndependentIII-N semiconductor materialGaNstress-tuning metalCMOS die with silicon MOSFETs on thin silicon substratehigh voltage die with GaN HEMTs on GOS substrate with back-side stress-tuning metal
A method of forming a 3D IC, the method comprising: receiving a silicon CMOS die comprising plurality of silicon MOSFETs on a ﬁrst substrate comprising silicon; receiving a high voltage die comprising a plurality of GaN-channeled high electron mobility transistors (HEMTs) on a GaN-On-Silicon (GOS) substrate having one or more single- crystalline III -N semiconductor material layers, wherein: the GOS substrate includes a second substrate comprising silicon and of greater thickness than the ﬁrst substrate; and a stress-tuning metal is disposed on a back-side of the GOS substrate opposite the HEMTs; and joining the silicon CMOS die to the high voltage die with a bump metal that makes contact to the stress-tuning metal. Previously presented
1. 40
  Dependent← claim 39
  The method of claim 39, wherein the ﬁrst substrate has a thickness of at least 775 m, and the second substrate has a thickness less than 100 m. Previously presented

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

semiconductor device structure with III-N and Si-MOSFET regions and dual back-side stress-tuning

second stress-tuning materialsecond stress-tuning trench fill (back-side, opposite second region)

first stress-tuning materialfirst stress-tuning trench fill (back-side, opposite first region)

III-N semiconductor materialIII-N epitaxial layers (first region front-side)

Sisubstrate

GOS semiconductor device structure with metal stress-tuning trench and through-substrate via

stress-tuning metal

Materials

Materials described outside the worked examples.

III-N semiconductor material

Epitaxial Layer

GaN

Epitaxial Channel Layer

Process steps

Additional fabrication and treatment steps described in the patent.

Epitaxial Growth

Step 1

Process details

note:front-side epitaxial growth on pre-processed silicon substrate

layer:single-crystalline III-N including GaN, thickness >= 1 µm

substrate:

Characterization

Measurements and analyses referenced in the patent, with their drawing references.

fet electrical

Fet Electrical

FIG. 2. In some embodiments, silicon substrate 205 is monocrystalline having a predetermined crystal orientation. Crystallographic orientation of a …

Figure references

FIG. 2

GaNGaN

Reported properties

Performance values and ranges asserted in the specification or claims.

Property	Value	Material
Linear Coefficient Of Thermal Expansion	—	first stress-tuning material
Temperature	25–30 °C

Why these are connected

Related documents with shared materials, methods, properties, or citations.

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