Patent
US 9,559,012GALLIUM NITRIDE COMPLEMENTARY TRANSISTORS
Rongming CHU
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,559,012Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-section of a GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit with N-channel and P-channel transistors in …
FIG. 2D, on top of the remaining portion 56 of the buffer layer 12, a I II -N P- barrier layer 20 may be grown by MOCVD or MBE. The P-barrier layer 20 can be …
FIG. 20, the N-gate trench 64 is filled with metal 32 to form a gate contact for the N- channel transistor, and the P-gate trench 62 is filled with metal 42 to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a substrate; a I II -nitride buffer layer on the substrate; an N-channel transistor comprising: a I II -nitride N-channel layer on one portion of the buffer layer; and a I II -nitride N-barrier layer for providing electrons on top of the N-channel layer, wherein the N- barrier layer has a wider bandgap than the N-channel layer; a P-channel transistor comprising: a I II -nitride P-barrier layer on another portion of the buffer layer for assisting accumulation of holes; a I II -nitride P-channel layer on top of the P- barrier layer, wherein the P-barrier layer has a wider bandgap than the P-channel layer; and a I II -nitride cap layer doped with P-type dopants on top of the P-channel layer.
The semiconductor device of claim 1 wherein: the N-channel transistor comprises a first mesa on the buffer layer; and the P-channel transistor comprises a second mesa on the buffer layer.
The semiconductor device of claim 1 wherein: the substrate comprises GaN, A l N, Sapphire, SiC, or Si.
The semiconductor device of claim 1 wherein: the I II -nitride buffer layer comprises GaN.
The semiconductor device of claim 1 wherein: the I II -N N-channel layer comprises GaN.
The semiconductor device of claim 1: wherein the I II -N N-barrier layer comprises one of more of AlGaN, AlInN, AlInGaN, or AlN; and wherein the N-barrier layer has a wider bandgap than the N-channel layer.
The semiconductor device of claim 1: wherein the P-barrier layer comprises one or more of AlGaN, AlInN, AlInGaN, or AlN.
The semiconductor device of claim 1: wherein the P-channel layer comprises GaN; and wherein the P-channel layer has a narrower bandgap than the P-barrier layer.
The semiconductor device of claim 1: wherein the P-cap layer comprises Mg.
The semiconductor device of claim 1 further comprising: an N-gate trench extending partially or entirely through the N-barrier layer, and partially or entirely through the N- channel layer, so that a bottom of the N-gate trench stops 13 anywhere between a top surface of the N-barrier layer and a top surface of the buffer layer; a P-gate trench extending partially or entirely through the P-cap layer, and partially through the P-channel layer, so that a bottom of the P-gate trench stops anywhere between a top surface of the P-cap layer and within the P-channel layer; a dielectric lining the N-gate trench and the P-gate trench; and first metal in the N-gate trench for an N-gate contact; second metal in the P-gate trench for a P-gate contact; source and drain N-ohmic contacts on opposite sides of the N-gate contact on the N-barrier layer or the on the N- channel layer; and source and drain P-ohmic contacts on opposite sides of the P-gate contact on the P-cap layer or the on the P-channel layer.
A method for providing a semiconductor device comprising: forming a I II -nitride (I II -N) layer buffer layer on a substrate; forming a I II -N N-channel layer on the buffer layer; forming a I II -N N-barrier layer on the N-channel layer; forming a first dielectric layer on top of the N-barrier layer; etching the first dielectric layer, the N-barrier layer, and the N-channel layer to form a first mesa for an N-channel transistor and to expose a portion of the buffer layer; 14 forming a second dielectric layer over the first mesa and over a first area of the exposed portion of the buffer layer, wherein the first area is adjacent the first mesa, and wherein a remaining portion of the buffer layer is exposed; forming on top of the remaining exposed portion of the buffer layer a I II -N P-barrier layer; forming on top of the I II -N P-barrier layer a I II -N P- channel layer; forming on top of the I II -N P-channel layer a I II -N P- cap layer, wherein the I II -N P-barrier layer, the I II -N P-channel layer, and the I II -N P-cap layer form a second mesa for a P-channel transistor, and wherein the first and second mesa are separated by the first area on the buffer layer; removing the second dielectric; and implanting ions in the buffer layer between the first mesa and the second mesa for providing isolation between the N-channel transistor and the P-channel transistor.
The method of claim 12 further comprising: forming a third dielectric over the P-cap layer and over a portion of the first area between the first and second mesas; forming a P-gate trench 62 in the third dielectric, wherein a bottom of the P-gate trench extends partially or entirely through the P-cap layer, or extends partially through the P-channel layer; and forming an N-gate trench in the first dielectric, wherein the bottom of the N-gate trench extends partially or entirely through the first dielectric, partially or entirely 15 through the N-barrier layer, or partially or entirely through the N-channel layer, so that the N-gate trench stops anywhere between a top surface of the first dielectric and a top surface of the buffer layer; and forming a fourth dielectric on top of the first dielectric, over the bottom and sides of the N-gate trench, on top of the third dielectric, and over the bottom and sides of the P-gate trench.
The method of claim 12 wherein: the substrate comprises GaN, AlN, Sapphire, SiC, or Si. 16
The method of claim 12 wherein: the I II -N buffer layer comprises GaN.
The method of claim 12 wherein: the I II -N N-channel layer comprises GaN.
The method of claim 12 wherein: wherein the I II -N N-barrier layer comprises one of more of AlGaN, AlInN, AlInGaN, or AlN; and wherein the N-barrier layer has a wider bandgap than the N-channel layer.
The method of claim 12 wherein: wherein the P-barrier layer comprises one or more of AlGaN, AlInN, AlInGaN, or AlN.
The method of claim 12 wherein: wherein the P-channel layer comprises GaN; and wherein the P-channel layer has a narrower bandgap than the P-barrier layer.
The method of claim 12 wherein: wherein the P-cap layer comprises Mg. 17
Layer stacks claimed or described, ordered top of device to substrate.
GaN CMOS integrated circuit with N-channel and P-channel transistors
Materials described outside the worked examples.
GaN buffer layer
GaN
III-N N-barrier layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows a cross-section of a GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit with N-channel and P-channel transistors in …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,559,012Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-section of a GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit with N-channel and P-channel transistors in …
FIG. 2D, on top of the remaining portion 56 of the buffer layer 12, a I II -N P- barrier layer 20 may be grown by MOCVD or MBE. The P-barrier layer 20 can be …
FIG. 20, the N-gate trench 64 is filled with metal 32 to form a gate contact for the N- channel transistor, and the P-gate trench 62 is filled with metal 42 to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a substrate; a I II -nitride buffer layer on the substrate; an N-channel transistor comprising: a I II -nitride N-channel layer on one portion of the buffer layer; and a I II -nitride N-barrier layer for providing electrons on top of the N-channel layer, wherein the N- barrier layer has a wider bandgap than the N-channel layer; a P-channel transistor comprising: a I II -nitride P-barrier layer on another portion of the buffer layer for assisting accumulation of holes; a I II -nitride P-channel layer on top of the P- barrier layer, wherein the P-barrier layer has a wider bandgap than the P-channel layer; and a I II -nitride cap layer doped with P-type dopants on top of the P-channel layer.
The semiconductor device of claim 1 wherein: the N-channel transistor comprises a first mesa on the buffer layer; and the P-channel transistor comprises a second mesa on the buffer layer.
The semiconductor device of claim 1 wherein: the substrate comprises GaN, A l N, Sapphire, SiC, or Si.
The semiconductor device of claim 1 wherein: the I II -nitride buffer layer comprises GaN.
The semiconductor device of claim 1 wherein: the I II -N N-channel layer comprises GaN.
The semiconductor device of claim 1: wherein the I II -N N-barrier layer comprises one of more of AlGaN, AlInN, AlInGaN, or AlN; and wherein the N-barrier layer has a wider bandgap than the N-channel layer.
The semiconductor device of claim 1: wherein the P-barrier layer comprises one or more of AlGaN, AlInN, AlInGaN, or AlN.
The semiconductor device of claim 1: wherein the P-channel layer comprises GaN; and wherein the P-channel layer has a narrower bandgap than the P-barrier layer.
The semiconductor device of claim 1: wherein the P-cap layer comprises Mg.
The semiconductor device of claim 1 further comprising: an N-gate trench extending partially or entirely through the N-barrier layer, and partially or entirely through the N- channel layer, so that a bottom of the N-gate trench stops 13 anywhere between a top surface of the N-barrier layer and a top surface of the buffer layer; a P-gate trench extending partially or entirely through the P-cap layer, and partially through the P-channel layer, so that a bottom of the P-gate trench stops anywhere between a top surface of the P-cap layer and within the P-channel layer; a dielectric lining the N-gate trench and the P-gate trench; and first metal in the N-gate trench for an N-gate contact; second metal in the P-gate trench for a P-gate contact; source and drain N-ohmic contacts on opposite sides of the N-gate contact on the N-barrier layer or the on the N- channel layer; and source and drain P-ohmic contacts on opposite sides of the P-gate contact on the P-cap layer or the on the P-channel layer.
A method for providing a semiconductor device comprising: forming a I II -nitride (I II -N) layer buffer layer on a substrate; forming a I II -N N-channel layer on the buffer layer; forming a I II -N N-barrier layer on the N-channel layer; forming a first dielectric layer on top of the N-barrier layer; etching the first dielectric layer, the N-barrier layer, and the N-channel layer to form a first mesa for an N-channel transistor and to expose a portion of the buffer layer; 14 forming a second dielectric layer over the first mesa and over a first area of the exposed portion of the buffer layer, wherein the first area is adjacent the first mesa, and wherein a remaining portion of the buffer layer is exposed; forming on top of the remaining exposed portion of the buffer layer a I II -N P-barrier layer; forming on top of the I II -N P-barrier layer a I II -N P- channel layer; forming on top of the I II -N P-channel layer a I II -N P- cap layer, wherein the I II -N P-barrier layer, the I II -N P-channel layer, and the I II -N P-cap layer form a second mesa for a P-channel transistor, and wherein the first and second mesa are separated by the first area on the buffer layer; removing the second dielectric; and implanting ions in the buffer layer between the first mesa and the second mesa for providing isolation between the N-channel transistor and the P-channel transistor.
The method of claim 12 further comprising: forming a third dielectric over the P-cap layer and over a portion of the first area between the first and second mesas; forming a P-gate trench 62 in the third dielectric, wherein a bottom of the P-gate trench extends partially or entirely through the P-cap layer, or extends partially through the P-channel layer; and forming an N-gate trench in the first dielectric, wherein the bottom of the N-gate trench extends partially or entirely through the first dielectric, partially or entirely 15 through the N-barrier layer, or partially or entirely through the N-channel layer, so that the N-gate trench stops anywhere between a top surface of the first dielectric and a top surface of the buffer layer; and forming a fourth dielectric on top of the first dielectric, over the bottom and sides of the N-gate trench, on top of the third dielectric, and over the bottom and sides of the P-gate trench.
The method of claim 12 wherein: the substrate comprises GaN, AlN, Sapphire, SiC, or Si. 16
The method of claim 12 wherein: the I II -N buffer layer comprises GaN.
The method of claim 12 wherein: the I II -N N-channel layer comprises GaN.
The method of claim 12 wherein: wherein the I II -N N-barrier layer comprises one of more of AlGaN, AlInN, AlInGaN, or AlN; and wherein the N-barrier layer has a wider bandgap than the N-channel layer.
The method of claim 12 wherein: wherein the P-barrier layer comprises one or more of AlGaN, AlInN, AlInGaN, or AlN.
The method of claim 12 wherein: wherein the P-channel layer comprises GaN; and wherein the P-channel layer has a narrower bandgap than the P-barrier layer.
The method of claim 12 wherein: wherein the P-cap layer comprises Mg. 17
Layer stacks claimed or described, ordered top of device to substrate.
GaN CMOS integrated circuit with N-channel and P-channel transistors
Materials described outside the worked examples.
GaN buffer layer
GaN
III-N N-barrier layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows a cross-section of a GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit with N-channel and P-channel transistors in …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,559,012Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-section of a GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit with N-channel and P-channel transistors in …
FIG. 2D, on top of the remaining portion 56 of the buffer layer 12, a I II -N P- barrier layer 20 may be grown by MOCVD or MBE. The P-barrier layer 20 can be …
FIG. 20, the N-gate trench 64 is filled with metal 32 to form a gate contact for the N- channel transistor, and the P-gate trench 62 is filled with metal 42 to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a substrate; a I II -nitride buffer layer on the substrate; an N-channel transistor comprising: a I II -nitride N-channel layer on one portion of the buffer layer; and a I II -nitride N-barrier layer for providing electrons on top of the N-channel layer, wherein the N- barrier layer has a wider bandgap than the N-channel layer; a P-channel transistor comprising: a I II -nitride P-barrier layer on another portion of the buffer layer for assisting accumulation of holes; a I II -nitride P-channel layer on top of the P- barrier layer, wherein the P-barrier layer has a wider bandgap than the P-channel layer; and a I II -nitride cap layer doped with P-type dopants on top of the P-channel layer.
The semiconductor device of claim 1 wherein: the N-channel transistor comprises a first mesa on the buffer layer; and the P-channel transistor comprises a second mesa on the buffer layer.
The semiconductor device of claim 1 wherein: the substrate comprises GaN, A l N, Sapphire, SiC, or Si.
The semiconductor device of claim 1 wherein: the I II -nitride buffer layer comprises GaN.
The semiconductor device of claim 1 wherein: the I II -N N-channel layer comprises GaN.
The semiconductor device of claim 1: wherein the I II -N N-barrier layer comprises one of more of AlGaN, AlInN, AlInGaN, or AlN; and wherein the N-barrier layer has a wider bandgap than the N-channel layer.
The semiconductor device of claim 1: wherein the P-barrier layer comprises one or more of AlGaN, AlInN, AlInGaN, or AlN.
The semiconductor device of claim 1: wherein the P-channel layer comprises GaN; and wherein the P-channel layer has a narrower bandgap than the P-barrier layer.
The semiconductor device of claim 1: wherein the P-cap layer comprises Mg.
The semiconductor device of claim 1 further comprising: an N-gate trench extending partially or entirely through the N-barrier layer, and partially or entirely through the N- channel layer, so that a bottom of the N-gate trench stops 13 anywhere between a top surface of the N-barrier layer and a top surface of the buffer layer; a P-gate trench extending partially or entirely through the P-cap layer, and partially through the P-channel layer, so that a bottom of the P-gate trench stops anywhere between a top surface of the P-cap layer and within the P-channel layer; a dielectric lining the N-gate trench and the P-gate trench; and first metal in the N-gate trench for an N-gate contact; second metal in the P-gate trench for a P-gate contact; source and drain N-ohmic contacts on opposite sides of the N-gate contact on the N-barrier layer or the on the N- channel layer; and source and drain P-ohmic contacts on opposite sides of the P-gate contact on the P-cap layer or the on the P-channel layer.
A method for providing a semiconductor device comprising: forming a I II -nitride (I II -N) layer buffer layer on a substrate; forming a I II -N N-channel layer on the buffer layer; forming a I II -N N-barrier layer on the N-channel layer; forming a first dielectric layer on top of the N-barrier layer; etching the first dielectric layer, the N-barrier layer, and the N-channel layer to form a first mesa for an N-channel transistor and to expose a portion of the buffer layer; 14 forming a second dielectric layer over the first mesa and over a first area of the exposed portion of the buffer layer, wherein the first area is adjacent the first mesa, and wherein a remaining portion of the buffer layer is exposed; forming on top of the remaining exposed portion of the buffer layer a I II -N P-barrier layer; forming on top of the I II -N P-barrier layer a I II -N P- channel layer; forming on top of the I II -N P-channel layer a I II -N P- cap layer, wherein the I II -N P-barrier layer, the I II -N P-channel layer, and the I II -N P-cap layer form a second mesa for a P-channel transistor, and wherein the first and second mesa are separated by the first area on the buffer layer; removing the second dielectric; and implanting ions in the buffer layer between the first mesa and the second mesa for providing isolation between the N-channel transistor and the P-channel transistor.
The method of claim 12 further comprising: forming a third dielectric over the P-cap layer and over a portion of the first area between the first and second mesas; forming a P-gate trench 62 in the third dielectric, wherein a bottom of the P-gate trench extends partially or entirely through the P-cap layer, or extends partially through the P-channel layer; and forming an N-gate trench in the first dielectric, wherein the bottom of the N-gate trench extends partially or entirely through the first dielectric, partially or entirely 15 through the N-barrier layer, or partially or entirely through the N-channel layer, so that the N-gate trench stops anywhere between a top surface of the first dielectric and a top surface of the buffer layer; and forming a fourth dielectric on top of the first dielectric, over the bottom and sides of the N-gate trench, on top of the third dielectric, and over the bottom and sides of the P-gate trench.
The method of claim 12 wherein: the substrate comprises GaN, AlN, Sapphire, SiC, or Si. 16
The method of claim 12 wherein: the I II -N buffer layer comprises GaN.
The method of claim 12 wherein: the I II -N N-channel layer comprises GaN.
The method of claim 12 wherein: wherein the I II -N N-barrier layer comprises one of more of AlGaN, AlInN, AlInGaN, or AlN; and wherein the N-barrier layer has a wider bandgap than the N-channel layer.
The method of claim 12 wherein: wherein the P-barrier layer comprises one or more of AlGaN, AlInN, AlInGaN, or AlN.
The method of claim 12 wherein: wherein the P-channel layer comprises GaN; and wherein the P-channel layer has a narrower bandgap than the P-barrier layer.
The method of claim 12 wherein: wherein the P-cap layer comprises Mg. 17
Layer stacks claimed or described, ordered top of device to substrate.
GaN CMOS integrated circuit with N-channel and P-channel transistors
Materials described outside the worked examples.
GaN buffer layer
GaN
III-N N-barrier layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows a cross-section of a GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit with N-channel and P-channel transistors in …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,559,012Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-section of a GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit with N-channel and P-channel transistors in …
FIG. 2D, on top of the remaining portion 56 of the buffer layer 12, a I II -N P- barrier layer 20 may be grown by MOCVD or MBE. The P-barrier layer 20 can be …
FIG. 20, the N-gate trench 64 is filled with metal 32 to form a gate contact for the N- channel transistor, and the P-gate trench 62 is filled with metal 42 to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a substrate; a I II -nitride buffer layer on the substrate; an N-channel transistor comprising: a I II -nitride N-channel layer on one portion of the buffer layer; and a I II -nitride N-barrier layer for providing electrons on top of the N-channel layer, wherein the N- barrier layer has a wider bandgap than the N-channel layer; a P-channel transistor comprising: a I II -nitride P-barrier layer on another portion of the buffer layer for assisting accumulation of holes; a I II -nitride P-channel layer on top of the P- barrier layer, wherein the P-barrier layer has a wider bandgap than the P-channel layer; and a I II -nitride cap layer doped with P-type dopants on top of the P-channel layer.
The semiconductor device of claim 1 wherein: the N-channel transistor comprises a first mesa on the buffer layer; and the P-channel transistor comprises a second mesa on the buffer layer.
The semiconductor device of claim 1 wherein: the substrate comprises GaN, A l N, Sapphire, SiC, or Si.
The semiconductor device of claim 1 wherein: the I II -nitride buffer layer comprises GaN.
The semiconductor device of claim 1 wherein: the I II -N N-channel layer comprises GaN.
The semiconductor device of claim 1: wherein the I II -N N-barrier layer comprises one of more of AlGaN, AlInN, AlInGaN, or AlN; and wherein the N-barrier layer has a wider bandgap than the N-channel layer.
The semiconductor device of claim 1: wherein the P-barrier layer comprises one or more of AlGaN, AlInN, AlInGaN, or AlN.
The semiconductor device of claim 1: wherein the P-channel layer comprises GaN; and wherein the P-channel layer has a narrower bandgap than the P-barrier layer.
The semiconductor device of claim 1: wherein the P-cap layer comprises Mg.
The semiconductor device of claim 1 further comprising: an N-gate trench extending partially or entirely through the N-barrier layer, and partially or entirely through the N- channel layer, so that a bottom of the N-gate trench stops 13 anywhere between a top surface of the N-barrier layer and a top surface of the buffer layer; a P-gate trench extending partially or entirely through the P-cap layer, and partially through the P-channel layer, so that a bottom of the P-gate trench stops anywhere between a top surface of the P-cap layer and within the P-channel layer; a dielectric lining the N-gate trench and the P-gate trench; and first metal in the N-gate trench for an N-gate contact; second metal in the P-gate trench for a P-gate contact; source and drain N-ohmic contacts on opposite sides of the N-gate contact on the N-barrier layer or the on the N- channel layer; and source and drain P-ohmic contacts on opposite sides of the P-gate contact on the P-cap layer or the on the P-channel layer.
A method for providing a semiconductor device comprising: forming a I II -nitride (I II -N) layer buffer layer on a substrate; forming a I II -N N-channel layer on the buffer layer; forming a I II -N N-barrier layer on the N-channel layer; forming a first dielectric layer on top of the N-barrier layer; etching the first dielectric layer, the N-barrier layer, and the N-channel layer to form a first mesa for an N-channel transistor and to expose a portion of the buffer layer; 14 forming a second dielectric layer over the first mesa and over a first area of the exposed portion of the buffer layer, wherein the first area is adjacent the first mesa, and wherein a remaining portion of the buffer layer is exposed; forming on top of the remaining exposed portion of the buffer layer a I II -N P-barrier layer; forming on top of the I II -N P-barrier layer a I II -N P- channel layer; forming on top of the I II -N P-channel layer a I II -N P- cap layer, wherein the I II -N P-barrier layer, the I II -N P-channel layer, and the I II -N P-cap layer form a second mesa for a P-channel transistor, and wherein the first and second mesa are separated by the first area on the buffer layer; removing the second dielectric; and implanting ions in the buffer layer between the first mesa and the second mesa for providing isolation between the N-channel transistor and the P-channel transistor.
The method of claim 12 further comprising: forming a third dielectric over the P-cap layer and over a portion of the first area between the first and second mesas; forming a P-gate trench 62 in the third dielectric, wherein a bottom of the P-gate trench extends partially or entirely through the P-cap layer, or extends partially through the P-channel layer; and forming an N-gate trench in the first dielectric, wherein the bottom of the N-gate trench extends partially or entirely through the first dielectric, partially or entirely 15 through the N-barrier layer, or partially or entirely through the N-channel layer, so that the N-gate trench stops anywhere between a top surface of the first dielectric and a top surface of the buffer layer; and forming a fourth dielectric on top of the first dielectric, over the bottom and sides of the N-gate trench, on top of the third dielectric, and over the bottom and sides of the P-gate trench.
The method of claim 12 wherein: the substrate comprises GaN, AlN, Sapphire, SiC, or Si. 16
The method of claim 12 wherein: the I II -N buffer layer comprises GaN.
The method of claim 12 wherein: the I II -N N-channel layer comprises GaN.
The method of claim 12 wherein: wherein the I II -N N-barrier layer comprises one of more of AlGaN, AlInN, AlInGaN, or AlN; and wherein the N-barrier layer has a wider bandgap than the N-channel layer.
The method of claim 12 wherein: wherein the P-barrier layer comprises one or more of AlGaN, AlInN, AlInGaN, or AlN.
The method of claim 12 wherein: wherein the P-channel layer comprises GaN; and wherein the P-channel layer has a narrower bandgap than the P-barrier layer.
The method of claim 12 wherein: wherein the P-cap layer comprises Mg. 17
Layer stacks claimed or described, ordered top of device to substrate.
GaN CMOS integrated circuit with N-channel and P-channel transistors
Materials described outside the worked examples.
GaN buffer layer
GaN
III-N N-barrier layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows a cross-section of a GaN based complementary metal-oxide-semiconductor (CMOS) integrated circuit with N-channel and P-channel transistors in …
Related documents with shared materials, methods, properties, or citations.
III-N P-barrier layer
III-N P-cap layer doped with P-type dopants
AlN substrate
AlN
Sapphire substrate
SiC substrate
SiC
Si substrate
Si
AlGaN N-barrier layer
AlGaN
AlInN N-barrier layer
AlInN
AlInGaN N-barrier layer
AlInGaN
Mg-doped GaN P-cap layer
GaN:Mg
SiN dielectric
SiN
SiO₂ dielectric
SiO₂
AlN/SiN gate dielectric stack
FIG. 2D, on top of the remaining portion 56 of the buffer layer 12, a I II -N P- barrier layer 20 may be grown by MOCVD or MBE. The P-barrier layer 20 can be …
FIG. 2D, on top of the remaining portion 56 of the buffer layer 12, a I II -N P- barrier layer 20 may be grown by MOCVD or MBE. The P-barrier layer 20 can be …
FIG. 20, the N-gate trench 64 is filled with metal 32 to form a gate contact for the N- channel transistor, and the P-gate trench 62 is filled with metal 42 to …
GALLIUM NITRIDE VOLTAGE REGULATOR
III-N P-barrier layer
III-N P-cap layer doped with P-type dopants
AlN substrate
AlN
Sapphire substrate
SiC substrate
SiC
Si substrate
Si
AlGaN N-barrier layer
AlGaN
AlInN N-barrier layer
AlInN
AlInGaN N-barrier layer
AlInGaN
Mg-doped GaN P-cap layer
GaN:Mg
SiN dielectric
SiN
SiO₂ dielectric
SiO₂
AlN/SiN gate dielectric stack
FIG. 2D, on top of the remaining portion 56 of the buffer layer 12, a I II -N P- barrier layer 20 may be grown by MOCVD or MBE. The P-barrier layer 20 can be …
FIG. 2D, on top of the remaining portion 56 of the buffer layer 12, a I II -N P- barrier layer 20 may be grown by MOCVD or MBE. The P-barrier layer 20 can be …
FIG. 20, the N-gate trench 64 is filled with metal 32 to form a gate contact for the N- channel transistor, and the P-gate trench 62 is filled with metal 42 to …
GALLIUM NITRIDE VOLTAGE REGULATOR
III-N P-barrier layer
III-N P-cap layer doped with P-type dopants
AlN substrate
AlN
Sapphire substrate
SiC substrate
SiC
Si substrate
Si
AlGaN N-barrier layer
AlGaN
AlInN N-barrier layer
AlInN
AlInGaN N-barrier layer
AlInGaN
Mg-doped GaN P-cap layer
GaN:Mg
SiN dielectric
SiN
SiO₂ dielectric
SiO₂
AlN/SiN gate dielectric stack
FIG. 2D, on top of the remaining portion 56 of the buffer layer 12, a I II -N P- barrier layer 20 may be grown by MOCVD or MBE. The P-barrier layer 20 can be …
FIG. 2D, on top of the remaining portion 56 of the buffer layer 12, a I II -N P- barrier layer 20 may be grown by MOCVD or MBE. The P-barrier layer 20 can be …
FIG. 20, the N-gate trench 64 is filled with metal 32 to form a gate contact for the N- channel transistor, and the P-gate trench 62 is filled with metal 42 to …
GALLIUM NITRIDE VOLTAGE REGULATOR
III-N P-barrier layer
III-N P-cap layer doped with P-type dopants
AlN substrate
AlN
Sapphire substrate
SiC substrate
SiC
Si substrate
Si
AlGaN N-barrier layer
AlGaN
AlInN N-barrier layer
AlInN
AlInGaN N-barrier layer
AlInGaN
Mg-doped GaN P-cap layer
GaN:Mg
SiN dielectric
SiN
SiO₂ dielectric
SiO₂
AlN/SiN gate dielectric stack
FIG. 2D, on top of the remaining portion 56 of the buffer layer 12, a I II -N P- barrier layer 20 may be grown by MOCVD or MBE. The P-barrier layer 20 can be …
FIG. 2D, on top of the remaining portion 56 of the buffer layer 12, a I II -N P- barrier layer 20 may be grown by MOCVD or MBE. The P-barrier layer 20 can be …
FIG. 20, the N-gate trench 64 is filled with metal 32 to form a gate contact for the N- channel transistor, and the P-gate trench 62 is filled with metal 42 to …