Patent
US 8,946,724Monolithically integrated self-aligned GaN-HEMTs and Schottky diodes and a Method of making same
Keisuke Shinohara
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,946,724Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A HEMT and Schottky diode integrated circuit device comprising: a. a common substrate for said HEMT and Schottky diode; b. a bek b9arrieri layer d isp o sedl o n sa i dimmn substrate an d at l east undr said HEMT; eb. a 2DEG channel layer disposed e n- over said common substrate under said HEMT and adjacent an anode of said Schottky diode; d c. a low resistance layer disposed al so on sa id ba ck barrier layer over said common substrate, the low resistance layer having openings therein under said HEMT and under said Schottky diode, the opening therein under said HEMT having sidewalls which immediately abut sidewalls of said 2DEG channel layer disposed on said common substrate under said HEMT and the opening therein under said Schottky diode having sidewalls which immediately abut sidewalls of said 2DEG channel layer disposed on said common substrate in said opening under said Schottky diode, the 2DEG channel layer disposed on said common substrate in said opening under said Schottky diode having further sidewalls which abut said anode; ed. a top barrier layer disposed over said low resistance layer; -f e. a T-shaped gate, the T-shaped gate inluing havin g a le g projetion thero f disposed over said top barrier layer and over the 2DEG channel layer disposed on said common substrate under said HEMT; Amendment with RCE Re: USSN 13/907,704 Page 7 2f. drain and source electrodes disposed on said low resistance layer and spaced from said T-shaped gate; and 4q. one or more cathode electrodes disposed on said low resistance layer and spaced from said anode.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein said T-shaped gate is formed of two different metals, a first metal forming said projection of said T-shaped gate and a second different metal forming a majority of the remaining portions of the T-shaped gate.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the 2DEG channel layer disposed on said common substrate under said HEMT is essentially laterally centered with respect said projection of said T-shaped gate.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the 2DEG channel layer disposed on said common substrate com p rises two p orti ons di osed.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the low resistance layer comprises a layer of a doped semiconductor.
The HEMT and Schottky diode integrated circuit device of claim 1 further including a cap layer disposed on btceon said top barrier layer.
The HEMT and Schottky diode integrated circuit device of claim 1 further including a back barrier layer disposed on said common substrate and at least under said HEMT.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the low resistance layer is a layer of highly doped semiconductor material.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the T-shaped gate includes a pair of arms which extend laterall y of the le g thereof.
The HEMT and Schottky diode integrated circuit device of claim [[1]] 20 wherein at least a portion of said back barrier layer is disposed between said anode and said substrate.
A diode comprising: a. a metallic anode structure; b. an 2DEG carrier region disposed laterally of said anode structure, the 2DEG carrier region having a proximate edge at a first end said 2DEG carrier region, the first edge being in physical contact with said metallic anode structure, said 2DEG carrier region having a distal edge at a second end of said 2DEG carrier region which is laterally spaced from said proximate edge; c. a low resistance doped semiconductor region disposed laterally of said 2DEG carrier region and spaced from said metallic anode structure, the low resistance doped semiconductor region having a proximate edge in contact with the distal edge of said 2DEG carrier region; and Amendment with RCE Re: USSN 13/907,704 Page 9 d. a metallic cathode structure in contact with said low resistance doped semiconductor region.
An integrated circuit including at least one transistor and at least one diode, the integrated circuit comprising: a. metallic anode structure; b. an 2DEG carrier region disposed laterally of said anode structure, the 2DEG carrier region having a proximate edge at a first end said 2DEG carrier region, the firot proximate edge being in physical contact with said metallic anode structure, said 2DEG carrier region having a distal edge at a second end of said 2DEG carrier region which is laterally spaced from said proximate edge; c. a low resistance doped semiconductor region disposed laterally of said 2DEG carrier region and spaced from said metallic anode structure, the low resistance doped semiconductor region having a proximate edge in contact with the distal edge of said 2DEG carrier region; d. a metallic cathode structure in contact with said low resistance doped semiconductor region; e. a T-shaped gate having a leg which projects from a head portion of said T-shaped gate; f. another 2DEG carrier region disposed under said leg of said T-shaped gate; g. second and third low resistance doped semiconductor regions disposed laterally of said another 2DEG carrier region, the second and third low resistance doped semiconductor regions each having an edge in contact with an ed g e of said another 2DEG carrier re g ion; Amendment with RCE Re: USSN 13/907,704 Page 10 h. a metallic source and drain electrodes in contact respectively with said second and third low resistance doped semiconductor regions; i. said 2DEG carrier region, said low resistance doped semiconductor region disposed laterally of said 2DEG carrier region, said another 2DEG carrier region and said second and third low resistance doped semiconductor regions all supported by a common substrat e and wherein 2 aid 2DE C carrior region, sa id l ow reistance doped emiconductor region diopoeo d l ater ally of sa id 2 DEC carrier r egi on, said another 2DE C carrier regio n a nd said ocoon d and t hird low reistaneo dopodcomion ductor region all lie in a common
The integrated circuit of claim 17 further including a back barrier layer disposed on said common substrate and under said 2DEG carrier region.
The integrated circuit of claim 17 wherein said 2DEG carrier region, said low resistance doped semiconductor region disposed laterally of said 2DEG carrier region, said another 2DEG carrier region and said second and third low resistance doped semiconductor regions all lie in a common plane.
Layer stacks claimed or described, ordered top of device to substrate.
monolithically integrated GaN HEMT and Schottky diode
Materials described outside the worked examples.
substrate
substrate (sapphire, SiC, silicon, or GaN)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–20 nm | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,946,724Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A HEMT and Schottky diode integrated circuit device comprising: a. a common substrate for said HEMT and Schottky diode; b. a bek b9arrieri layer d isp o sedl o n sa i dimmn substrate an d at l east undr said HEMT; eb. a 2DEG channel layer disposed e n- over said common substrate under said HEMT and adjacent an anode of said Schottky diode; d c. a low resistance layer disposed al so on sa id ba ck barrier layer over said common substrate, the low resistance layer having openings therein under said HEMT and under said Schottky diode, the opening therein under said HEMT having sidewalls which immediately abut sidewalls of said 2DEG channel layer disposed on said common substrate under said HEMT and the opening therein under said Schottky diode having sidewalls which immediately abut sidewalls of said 2DEG channel layer disposed on said common substrate in said opening under said Schottky diode, the 2DEG channel layer disposed on said common substrate in said opening under said Schottky diode having further sidewalls which abut said anode; ed. a top barrier layer disposed over said low resistance layer; -f e. a T-shaped gate, the T-shaped gate inluing havin g a le g projetion thero f disposed over said top barrier layer and over the 2DEG channel layer disposed on said common substrate under said HEMT; Amendment with RCE Re: USSN 13/907,704 Page 7 2f. drain and source electrodes disposed on said low resistance layer and spaced from said T-shaped gate; and 4q. one or more cathode electrodes disposed on said low resistance layer and spaced from said anode.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein said T-shaped gate is formed of two different metals, a first metal forming said projection of said T-shaped gate and a second different metal forming a majority of the remaining portions of the T-shaped gate.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the 2DEG channel layer disposed on said common substrate under said HEMT is essentially laterally centered with respect said projection of said T-shaped gate.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the 2DEG channel layer disposed on said common substrate com p rises two p orti ons di osed.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the low resistance layer comprises a layer of a doped semiconductor.
The HEMT and Schottky diode integrated circuit device of claim 1 further including a cap layer disposed on btceon said top barrier layer.
The HEMT and Schottky diode integrated circuit device of claim 1 further including a back barrier layer disposed on said common substrate and at least under said HEMT.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the low resistance layer is a layer of highly doped semiconductor material.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the T-shaped gate includes a pair of arms which extend laterall y of the le g thereof.
The HEMT and Schottky diode integrated circuit device of claim [[1]] 20 wherein at least a portion of said back barrier layer is disposed between said anode and said substrate.
A diode comprising: a. a metallic anode structure; b. an 2DEG carrier region disposed laterally of said anode structure, the 2DEG carrier region having a proximate edge at a first end said 2DEG carrier region, the first edge being in physical contact with said metallic anode structure, said 2DEG carrier region having a distal edge at a second end of said 2DEG carrier region which is laterally spaced from said proximate edge; c. a low resistance doped semiconductor region disposed laterally of said 2DEG carrier region and spaced from said metallic anode structure, the low resistance doped semiconductor region having a proximate edge in contact with the distal edge of said 2DEG carrier region; and Amendment with RCE Re: USSN 13/907,704 Page 9 d. a metallic cathode structure in contact with said low resistance doped semiconductor region.
An integrated circuit including at least one transistor and at least one diode, the integrated circuit comprising: a. metallic anode structure; b. an 2DEG carrier region disposed laterally of said anode structure, the 2DEG carrier region having a proximate edge at a first end said 2DEG carrier region, the firot proximate edge being in physical contact with said metallic anode structure, said 2DEG carrier region having a distal edge at a second end of said 2DEG carrier region which is laterally spaced from said proximate edge; c. a low resistance doped semiconductor region disposed laterally of said 2DEG carrier region and spaced from said metallic anode structure, the low resistance doped semiconductor region having a proximate edge in contact with the distal edge of said 2DEG carrier region; d. a metallic cathode structure in contact with said low resistance doped semiconductor region; e. a T-shaped gate having a leg which projects from a head portion of said T-shaped gate; f. another 2DEG carrier region disposed under said leg of said T-shaped gate; g. second and third low resistance doped semiconductor regions disposed laterally of said another 2DEG carrier region, the second and third low resistance doped semiconductor regions each having an edge in contact with an ed g e of said another 2DEG carrier re g ion; Amendment with RCE Re: USSN 13/907,704 Page 10 h. a metallic source and drain electrodes in contact respectively with said second and third low resistance doped semiconductor regions; i. said 2DEG carrier region, said low resistance doped semiconductor region disposed laterally of said 2DEG carrier region, said another 2DEG carrier region and said second and third low resistance doped semiconductor regions all supported by a common substrat e and wherein 2 aid 2DE C carrior region, sa id l ow reistance doped emiconductor region diopoeo d l ater ally of sa id 2 DEC carrier r egi on, said another 2DE C carrier regio n a nd said ocoon d and t hird low reistaneo dopodcomion ductor region all lie in a common
The integrated circuit of claim 17 further including a back barrier layer disposed on said common substrate and under said 2DEG carrier region.
The integrated circuit of claim 17 wherein said 2DEG carrier region, said low resistance doped semiconductor region disposed laterally of said 2DEG carrier region, said another 2DEG carrier region and said second and third low resistance doped semiconductor regions all lie in a common plane.
Layer stacks claimed or described, ordered top of device to substrate.
monolithically integrated GaN HEMT and Schottky diode
Materials described outside the worked examples.
substrate
substrate (sapphire, SiC, silicon, or GaN)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–20 nm | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,946,724Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A HEMT and Schottky diode integrated circuit device comprising: a. a common substrate for said HEMT and Schottky diode; b. a bek b9arrieri layer d isp o sedl o n sa i dimmn substrate an d at l east undr said HEMT; eb. a 2DEG channel layer disposed e n- over said common substrate under said HEMT and adjacent an anode of said Schottky diode; d c. a low resistance layer disposed al so on sa id ba ck barrier layer over said common substrate, the low resistance layer having openings therein under said HEMT and under said Schottky diode, the opening therein under said HEMT having sidewalls which immediately abut sidewalls of said 2DEG channel layer disposed on said common substrate under said HEMT and the opening therein under said Schottky diode having sidewalls which immediately abut sidewalls of said 2DEG channel layer disposed on said common substrate in said opening under said Schottky diode, the 2DEG channel layer disposed on said common substrate in said opening under said Schottky diode having further sidewalls which abut said anode; ed. a top barrier layer disposed over said low resistance layer; -f e. a T-shaped gate, the T-shaped gate inluing havin g a le g projetion thero f disposed over said top barrier layer and over the 2DEG channel layer disposed on said common substrate under said HEMT; Amendment with RCE Re: USSN 13/907,704 Page 7 2f. drain and source electrodes disposed on said low resistance layer and spaced from said T-shaped gate; and 4q. one or more cathode electrodes disposed on said low resistance layer and spaced from said anode.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein said T-shaped gate is formed of two different metals, a first metal forming said projection of said T-shaped gate and a second different metal forming a majority of the remaining portions of the T-shaped gate.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the 2DEG channel layer disposed on said common substrate under said HEMT is essentially laterally centered with respect said projection of said T-shaped gate.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the 2DEG channel layer disposed on said common substrate com p rises two p orti ons di osed.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the low resistance layer comprises a layer of a doped semiconductor.
The HEMT and Schottky diode integrated circuit device of claim 1 further including a cap layer disposed on btceon said top barrier layer.
The HEMT and Schottky diode integrated circuit device of claim 1 further including a back barrier layer disposed on said common substrate and at least under said HEMT.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the low resistance layer is a layer of highly doped semiconductor material.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the T-shaped gate includes a pair of arms which extend laterall y of the le g thereof.
The HEMT and Schottky diode integrated circuit device of claim [[1]] 20 wherein at least a portion of said back barrier layer is disposed between said anode and said substrate.
A diode comprising: a. a metallic anode structure; b. an 2DEG carrier region disposed laterally of said anode structure, the 2DEG carrier region having a proximate edge at a first end said 2DEG carrier region, the first edge being in physical contact with said metallic anode structure, said 2DEG carrier region having a distal edge at a second end of said 2DEG carrier region which is laterally spaced from said proximate edge; c. a low resistance doped semiconductor region disposed laterally of said 2DEG carrier region and spaced from said metallic anode structure, the low resistance doped semiconductor region having a proximate edge in contact with the distal edge of said 2DEG carrier region; and Amendment with RCE Re: USSN 13/907,704 Page 9 d. a metallic cathode structure in contact with said low resistance doped semiconductor region.
An integrated circuit including at least one transistor and at least one diode, the integrated circuit comprising: a. metallic anode structure; b. an 2DEG carrier region disposed laterally of said anode structure, the 2DEG carrier region having a proximate edge at a first end said 2DEG carrier region, the firot proximate edge being in physical contact with said metallic anode structure, said 2DEG carrier region having a distal edge at a second end of said 2DEG carrier region which is laterally spaced from said proximate edge; c. a low resistance doped semiconductor region disposed laterally of said 2DEG carrier region and spaced from said metallic anode structure, the low resistance doped semiconductor region having a proximate edge in contact with the distal edge of said 2DEG carrier region; d. a metallic cathode structure in contact with said low resistance doped semiconductor region; e. a T-shaped gate having a leg which projects from a head portion of said T-shaped gate; f. another 2DEG carrier region disposed under said leg of said T-shaped gate; g. second and third low resistance doped semiconductor regions disposed laterally of said another 2DEG carrier region, the second and third low resistance doped semiconductor regions each having an edge in contact with an ed g e of said another 2DEG carrier re g ion; Amendment with RCE Re: USSN 13/907,704 Page 10 h. a metallic source and drain electrodes in contact respectively with said second and third low resistance doped semiconductor regions; i. said 2DEG carrier region, said low resistance doped semiconductor region disposed laterally of said 2DEG carrier region, said another 2DEG carrier region and said second and third low resistance doped semiconductor regions all supported by a common substrat e and wherein 2 aid 2DE C carrior region, sa id l ow reistance doped emiconductor region diopoeo d l ater ally of sa id 2 DEC carrier r egi on, said another 2DE C carrier regio n a nd said ocoon d and t hird low reistaneo dopodcomion ductor region all lie in a common
The integrated circuit of claim 17 further including a back barrier layer disposed on said common substrate and under said 2DEG carrier region.
The integrated circuit of claim 17 wherein said 2DEG carrier region, said low resistance doped semiconductor region disposed laterally of said 2DEG carrier region, said another 2DEG carrier region and said second and third low resistance doped semiconductor regions all lie in a common plane.
Layer stacks claimed or described, ordered top of device to substrate.
monolithically integrated GaN HEMT and Schottky diode
Materials described outside the worked examples.
substrate
substrate (sapphire, SiC, silicon, or GaN)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–20 nm | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,946,724Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A HEMT and Schottky diode integrated circuit device comprising: a. a common substrate for said HEMT and Schottky diode; b. a bek b9arrieri layer d isp o sedl o n sa i dimmn substrate an d at l east undr said HEMT; eb. a 2DEG channel layer disposed e n- over said common substrate under said HEMT and adjacent an anode of said Schottky diode; d c. a low resistance layer disposed al so on sa id ba ck barrier layer over said common substrate, the low resistance layer having openings therein under said HEMT and under said Schottky diode, the opening therein under said HEMT having sidewalls which immediately abut sidewalls of said 2DEG channel layer disposed on said common substrate under said HEMT and the opening therein under said Schottky diode having sidewalls which immediately abut sidewalls of said 2DEG channel layer disposed on said common substrate in said opening under said Schottky diode, the 2DEG channel layer disposed on said common substrate in said opening under said Schottky diode having further sidewalls which abut said anode; ed. a top barrier layer disposed over said low resistance layer; -f e. a T-shaped gate, the T-shaped gate inluing havin g a le g projetion thero f disposed over said top barrier layer and over the 2DEG channel layer disposed on said common substrate under said HEMT; Amendment with RCE Re: USSN 13/907,704 Page 7 2f. drain and source electrodes disposed on said low resistance layer and spaced from said T-shaped gate; and 4q. one or more cathode electrodes disposed on said low resistance layer and spaced from said anode.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein said T-shaped gate is formed of two different metals, a first metal forming said projection of said T-shaped gate and a second different metal forming a majority of the remaining portions of the T-shaped gate.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the 2DEG channel layer disposed on said common substrate under said HEMT is essentially laterally centered with respect said projection of said T-shaped gate.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the 2DEG channel layer disposed on said common substrate com p rises two p orti ons di osed.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the low resistance layer comprises a layer of a doped semiconductor.
The HEMT and Schottky diode integrated circuit device of claim 1 further including a cap layer disposed on btceon said top barrier layer.
The HEMT and Schottky diode integrated circuit device of claim 1 further including a back barrier layer disposed on said common substrate and at least under said HEMT.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the low resistance layer is a layer of highly doped semiconductor material.
The HEMT and Schottky diode integrated circuit device of claim 1 wherein the T-shaped gate includes a pair of arms which extend laterall y of the le g thereof.
The HEMT and Schottky diode integrated circuit device of claim [[1]] 20 wherein at least a portion of said back barrier layer is disposed between said anode and said substrate.
A diode comprising: a. a metallic anode structure; b. an 2DEG carrier region disposed laterally of said anode structure, the 2DEG carrier region having a proximate edge at a first end said 2DEG carrier region, the first edge being in physical contact with said metallic anode structure, said 2DEG carrier region having a distal edge at a second end of said 2DEG carrier region which is laterally spaced from said proximate edge; c. a low resistance doped semiconductor region disposed laterally of said 2DEG carrier region and spaced from said metallic anode structure, the low resistance doped semiconductor region having a proximate edge in contact with the distal edge of said 2DEG carrier region; and Amendment with RCE Re: USSN 13/907,704 Page 9 d. a metallic cathode structure in contact with said low resistance doped semiconductor region.
An integrated circuit including at least one transistor and at least one diode, the integrated circuit comprising: a. metallic anode structure; b. an 2DEG carrier region disposed laterally of said anode structure, the 2DEG carrier region having a proximate edge at a first end said 2DEG carrier region, the firot proximate edge being in physical contact with said metallic anode structure, said 2DEG carrier region having a distal edge at a second end of said 2DEG carrier region which is laterally spaced from said proximate edge; c. a low resistance doped semiconductor region disposed laterally of said 2DEG carrier region and spaced from said metallic anode structure, the low resistance doped semiconductor region having a proximate edge in contact with the distal edge of said 2DEG carrier region; d. a metallic cathode structure in contact with said low resistance doped semiconductor region; e. a T-shaped gate having a leg which projects from a head portion of said T-shaped gate; f. another 2DEG carrier region disposed under said leg of said T-shaped gate; g. second and third low resistance doped semiconductor regions disposed laterally of said another 2DEG carrier region, the second and third low resistance doped semiconductor regions each having an edge in contact with an ed g e of said another 2DEG carrier re g ion; Amendment with RCE Re: USSN 13/907,704 Page 10 h. a metallic source and drain electrodes in contact respectively with said second and third low resistance doped semiconductor regions; i. said 2DEG carrier region, said low resistance doped semiconductor region disposed laterally of said 2DEG carrier region, said another 2DEG carrier region and said second and third low resistance doped semiconductor regions all supported by a common substrat e and wherein 2 aid 2DE C carrior region, sa id l ow reistance doped emiconductor region diopoeo d l ater ally of sa id 2 DEC carrier r egi on, said another 2DE C carrier regio n a nd said ocoon d and t hird low reistaneo dopodcomion ductor region all lie in a common
The integrated circuit of claim 17 further including a back barrier layer disposed on said common substrate and under said 2DEG carrier region.
The integrated circuit of claim 17 wherein said 2DEG carrier region, said low resistance doped semiconductor region disposed laterally of said 2DEG carrier region, said another 2DEG carrier region and said second and third low resistance doped semiconductor regions all lie in a common plane.
Layer stacks claimed or described, ordered top of device to substrate.
monolithically integrated GaN HEMT and Schottky diode
Materials described outside the worked examples.
substrate
substrate (sapphire, SiC, silicon, or GaN)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–20 nm | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
GaN Schottky diode with 2DEG anode contact
AlGaN back barrier layer
AlGaN
GaN 2DEG channel layer
GaN
Pt (T-gate projection metal)
Pt
Au (T-gate head metal)
Au
SiN passivation layer
SiN
SiO₂
Pt/Au ohmic contacts
| — |
GaN Schottky diode with 2DEG anode contact
AlGaN back barrier layer
AlGaN
GaN 2DEG channel layer
GaN
Pt (T-gate projection metal)
Pt
Au (T-gate head metal)
Au
SiN passivation layer
SiN
SiO₂
Pt/Au ohmic contacts
| — |
GaN Schottky diode with 2DEG anode contact
AlGaN back barrier layer
AlGaN
GaN 2DEG channel layer
GaN
Pt (T-gate projection metal)
Pt
Au (T-gate head metal)
Au
SiN passivation layer
SiN
SiO₂
Pt/Au ohmic contacts
| — |
GaN Schottky diode with 2DEG anode contact
AlGaN back barrier layer
AlGaN
GaN 2DEG channel layer
GaN
Pt (T-gate projection metal)
Pt
Au (T-gate head metal)
Au
SiN passivation layer
SiN
SiO₂
Pt/Au ohmic contacts
| — |