Patent
US 8,390,027Gallium Nitride Semiconductor Device and Manufacturing Method Thereof
Noriyuki IWAMURO
US
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US 8,390,027Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a cross sectional view showing the principal part of a GaN- MOSFET according to Example 1 of the invention;
Figure 2 is a cross sectional view showing an arrangement of the principal part of the GaN-MOSFET according to Example 1 of the invention in the step in which the basic layer structure of the semiconductor substrate is completed in the manufacturing process of the MOSFET;
Figure 3 is a cross sectional view showing an arrangement of the principal part of the GaN-MOSFET according to Example 1 of the invention in the step next to that shown in
Figure 4 is a cross sectional view showing an arrangement of the principal part of the GaN-MOSFET according to Example 1 of the invention in the step next to that shown in
Figure 5 is a cross sectional view showing an arrangement of the principal part of the GaN-MOSFET according to Example 1 of the invention in the step next to that shown in
Figure 6 is a cross sectional view showing the principal part of a related silicon semiconductor substrate with GaN layers formed thereon which substrate is disclosed in JP-A-2006-165191; [00 27]
Figure 7 is a diagram showing the breakdown voltage blocking characteristic at turning-off of the GaN-MOSFET according to Example 1 of the invention; [002 8]
Figure 8 is a diagram showing the I -V characteristic at turning-on of the GaN-MOSFET according to Example 1 of the invention together with those of an ordinary Si-IGBT and an ordinary Si-MOSFET; [00 29]
Figure 9 is a cross sectional view showing the principal part of a GaN- MOSFET according to Example 2 of the invention;
Figure 10 is a cross sectional view showing the principal part of a GaN Schottky barrier diode according to Example 3 of the invention;
Figure 11 is a diagram showing the breakdown voltage blocking characteristic of the GaN Schottky barrier diode according to Example 3 of the invention; and
Figure 12 is a diagram showing the forward I-V characteristic of the GaN Schottky barrier diode according to Example 3 of the invention together with that of an ordinary pin diode.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride semiconductor device comprising: a silicon semiconductor substrate; a buffer layer provided on a first surface of the silicon semiconductor substrate for crystal structure conversion and/or crystal quality improvement; and an epitaxial gallium nitride semiconductor layer overlying the buffer layer, the silicon semiconductor substrate having a plurality of trenches formed on the side of the substrate opposite the first surface, each trench reaching through the silicon semiconductor substrate and the buffer layer to the gallium nitride semiconductor layer, and the inside surface of each of the trenches and the other principal surface of the silicon semiconductor substrate being covered with a metal film.
The gallium nitride semiconductor device as claimed in claim 1, wherein the buffer layer further comprises an aluminum nitride layer on the side of the silicon semiconductor substrate and a gallium nitride layer on the upper side thereof.
A method of manufacturing a gallium nitride semiconductor device comprising the steps of: 2 Appln. SN: 12/243,201 Attorney Docket No.: FUJI-051 1 preparing a silicon semiconductor substrate; forming a buffer layer on a first surface of the silicon semiconductor substrate, the buffer layer providing crystal structure conversion and/or crystal quality improvement; forming a gallium nitride semiconductor layer on the buffer layer by epitaxial growth; forming a plurality of trenches in the silicon semiconductor substrate on the other side of the semiconductor substrate, each trench being formed with a depth so that it reaches through the silicon semiconductor substrate and the buffer layer to the gallium nitride semiconductor layer on the first surface; and forming a metal film so as to cover the inside surface of each of the trenches and the other principal surface of the silicon semiconductor substrate.
The method of manufacturing a gallium nitride semiconductor device as claimed in claim 5, wherein the step of forming the buffer layer further comprises the steps of: forming an aluminum nitride layer on the side of the silicon semiconductor substrate; and forming a gallium nitride layer on the upper side the aluminum nitride layer.
Layer stacks claimed or described, ordered top of device to substrate.
vertical gallium nitride semiconductor device
Materials described outside the worked examples.
silicon semiconductor substrate
Si
buffer layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 12 is a diagram showing the forward I-V characteristic of the GaN Schottky barrier diode according to Example 3 of the invention together with that of an ordinary pin diode.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,390,027Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a cross sectional view showing the principal part of a GaN- MOSFET according to Example 1 of the invention;
Figure 2 is a cross sectional view showing an arrangement of the principal part of the GaN-MOSFET according to Example 1 of the invention in the step in which the basic layer structure of the semiconductor substrate is completed in the manufacturing process of the MOSFET;
Figure 3 is a cross sectional view showing an arrangement of the principal part of the GaN-MOSFET according to Example 1 of the invention in the step next to that shown in
Figure 4 is a cross sectional view showing an arrangement of the principal part of the GaN-MOSFET according to Example 1 of the invention in the step next to that shown in
Figure 5 is a cross sectional view showing an arrangement of the principal part of the GaN-MOSFET according to Example 1 of the invention in the step next to that shown in
Figure 6 is a cross sectional view showing the principal part of a related silicon semiconductor substrate with GaN layers formed thereon which substrate is disclosed in JP-A-2006-165191; [00 27]
Figure 7 is a diagram showing the breakdown voltage blocking characteristic at turning-off of the GaN-MOSFET according to Example 1 of the invention; [002 8]
Figure 8 is a diagram showing the I -V characteristic at turning-on of the GaN-MOSFET according to Example 1 of the invention together with those of an ordinary Si-IGBT and an ordinary Si-MOSFET; [00 29]
Figure 9 is a cross sectional view showing the principal part of a GaN- MOSFET according to Example 2 of the invention;
Figure 10 is a cross sectional view showing the principal part of a GaN Schottky barrier diode according to Example 3 of the invention;
Figure 11 is a diagram showing the breakdown voltage blocking characteristic of the GaN Schottky barrier diode according to Example 3 of the invention; and
Figure 12 is a diagram showing the forward I-V characteristic of the GaN Schottky barrier diode according to Example 3 of the invention together with that of an ordinary pin diode.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride semiconductor device comprising: a silicon semiconductor substrate; a buffer layer provided on a first surface of the silicon semiconductor substrate for crystal structure conversion and/or crystal quality improvement; and an epitaxial gallium nitride semiconductor layer overlying the buffer layer, the silicon semiconductor substrate having a plurality of trenches formed on the side of the substrate opposite the first surface, each trench reaching through the silicon semiconductor substrate and the buffer layer to the gallium nitride semiconductor layer, and the inside surface of each of the trenches and the other principal surface of the silicon semiconductor substrate being covered with a metal film.
The gallium nitride semiconductor device as claimed in claim 1, wherein the buffer layer further comprises an aluminum nitride layer on the side of the silicon semiconductor substrate and a gallium nitride layer on the upper side thereof.
A method of manufacturing a gallium nitride semiconductor device comprising the steps of: 2 Appln. SN: 12/243,201 Attorney Docket No.: FUJI-051 1 preparing a silicon semiconductor substrate; forming a buffer layer on a first surface of the silicon semiconductor substrate, the buffer layer providing crystal structure conversion and/or crystal quality improvement; forming a gallium nitride semiconductor layer on the buffer layer by epitaxial growth; forming a plurality of trenches in the silicon semiconductor substrate on the other side of the semiconductor substrate, each trench being formed with a depth so that it reaches through the silicon semiconductor substrate and the buffer layer to the gallium nitride semiconductor layer on the first surface; and forming a metal film so as to cover the inside surface of each of the trenches and the other principal surface of the silicon semiconductor substrate.
The method of manufacturing a gallium nitride semiconductor device as claimed in claim 5, wherein the step of forming the buffer layer further comprises the steps of: forming an aluminum nitride layer on the side of the silicon semiconductor substrate; and forming a gallium nitride layer on the upper side the aluminum nitride layer.
Layer stacks claimed or described, ordered top of device to substrate.
vertical gallium nitride semiconductor device
Materials described outside the worked examples.
silicon semiconductor substrate
Si
buffer layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 12 is a diagram showing the forward I-V characteristic of the GaN Schottky barrier diode according to Example 3 of the invention together with that of an ordinary pin diode.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,390,027Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a cross sectional view showing the principal part of a GaN- MOSFET according to Example 1 of the invention;
Figure 2 is a cross sectional view showing an arrangement of the principal part of the GaN-MOSFET according to Example 1 of the invention in the step in which the basic layer structure of the semiconductor substrate is completed in the manufacturing process of the MOSFET;
Figure 3 is a cross sectional view showing an arrangement of the principal part of the GaN-MOSFET according to Example 1 of the invention in the step next to that shown in
Figure 4 is a cross sectional view showing an arrangement of the principal part of the GaN-MOSFET according to Example 1 of the invention in the step next to that shown in
Figure 5 is a cross sectional view showing an arrangement of the principal part of the GaN-MOSFET according to Example 1 of the invention in the step next to that shown in
Figure 6 is a cross sectional view showing the principal part of a related silicon semiconductor substrate with GaN layers formed thereon which substrate is disclosed in JP-A-2006-165191; [00 27]
Figure 7 is a diagram showing the breakdown voltage blocking characteristic at turning-off of the GaN-MOSFET according to Example 1 of the invention; [002 8]
Figure 8 is a diagram showing the I -V characteristic at turning-on of the GaN-MOSFET according to Example 1 of the invention together with those of an ordinary Si-IGBT and an ordinary Si-MOSFET; [00 29]
Figure 9 is a cross sectional view showing the principal part of a GaN- MOSFET according to Example 2 of the invention;
Figure 10 is a cross sectional view showing the principal part of a GaN Schottky barrier diode according to Example 3 of the invention;
Figure 11 is a diagram showing the breakdown voltage blocking characteristic of the GaN Schottky barrier diode according to Example 3 of the invention; and
Figure 12 is a diagram showing the forward I-V characteristic of the GaN Schottky barrier diode according to Example 3 of the invention together with that of an ordinary pin diode.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride semiconductor device comprising: a silicon semiconductor substrate; a buffer layer provided on a first surface of the silicon semiconductor substrate for crystal structure conversion and/or crystal quality improvement; and an epitaxial gallium nitride semiconductor layer overlying the buffer layer, the silicon semiconductor substrate having a plurality of trenches formed on the side of the substrate opposite the first surface, each trench reaching through the silicon semiconductor substrate and the buffer layer to the gallium nitride semiconductor layer, and the inside surface of each of the trenches and the other principal surface of the silicon semiconductor substrate being covered with a metal film.
The gallium nitride semiconductor device as claimed in claim 1, wherein the buffer layer further comprises an aluminum nitride layer on the side of the silicon semiconductor substrate and a gallium nitride layer on the upper side thereof.
A method of manufacturing a gallium nitride semiconductor device comprising the steps of: 2 Appln. SN: 12/243,201 Attorney Docket No.: FUJI-051 1 preparing a silicon semiconductor substrate; forming a buffer layer on a first surface of the silicon semiconductor substrate, the buffer layer providing crystal structure conversion and/or crystal quality improvement; forming a gallium nitride semiconductor layer on the buffer layer by epitaxial growth; forming a plurality of trenches in the silicon semiconductor substrate on the other side of the semiconductor substrate, each trench being formed with a depth so that it reaches through the silicon semiconductor substrate and the buffer layer to the gallium nitride semiconductor layer on the first surface; and forming a metal film so as to cover the inside surface of each of the trenches and the other principal surface of the silicon semiconductor substrate.
The method of manufacturing a gallium nitride semiconductor device as claimed in claim 5, wherein the step of forming the buffer layer further comprises the steps of: forming an aluminum nitride layer on the side of the silicon semiconductor substrate; and forming a gallium nitride layer on the upper side the aluminum nitride layer.
Layer stacks claimed or described, ordered top of device to substrate.
vertical gallium nitride semiconductor device
Materials described outside the worked examples.
silicon semiconductor substrate
Si
buffer layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 12 is a diagram showing the forward I-V characteristic of the GaN Schottky barrier diode according to Example 3 of the invention together with that of an ordinary pin diode.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,390,027Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a cross sectional view showing the principal part of a GaN- MOSFET according to Example 1 of the invention;
Figure 2 is a cross sectional view showing an arrangement of the principal part of the GaN-MOSFET according to Example 1 of the invention in the step in which the basic layer structure of the semiconductor substrate is completed in the manufacturing process of the MOSFET;
Figure 3 is a cross sectional view showing an arrangement of the principal part of the GaN-MOSFET according to Example 1 of the invention in the step next to that shown in
Figure 4 is a cross sectional view showing an arrangement of the principal part of the GaN-MOSFET according to Example 1 of the invention in the step next to that shown in
Figure 5 is a cross sectional view showing an arrangement of the principal part of the GaN-MOSFET according to Example 1 of the invention in the step next to that shown in
Figure 6 is a cross sectional view showing the principal part of a related silicon semiconductor substrate with GaN layers formed thereon which substrate is disclosed in JP-A-2006-165191; [00 27]
Figure 7 is a diagram showing the breakdown voltage blocking characteristic at turning-off of the GaN-MOSFET according to Example 1 of the invention; [002 8]
Figure 8 is a diagram showing the I -V characteristic at turning-on of the GaN-MOSFET according to Example 1 of the invention together with those of an ordinary Si-IGBT and an ordinary Si-MOSFET; [00 29]
Figure 9 is a cross sectional view showing the principal part of a GaN- MOSFET according to Example 2 of the invention;
Figure 10 is a cross sectional view showing the principal part of a GaN Schottky barrier diode according to Example 3 of the invention;
Figure 11 is a diagram showing the breakdown voltage blocking characteristic of the GaN Schottky barrier diode according to Example 3 of the invention; and
Figure 12 is a diagram showing the forward I-V characteristic of the GaN Schottky barrier diode according to Example 3 of the invention together with that of an ordinary pin diode.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride semiconductor device comprising: a silicon semiconductor substrate; a buffer layer provided on a first surface of the silicon semiconductor substrate for crystal structure conversion and/or crystal quality improvement; and an epitaxial gallium nitride semiconductor layer overlying the buffer layer, the silicon semiconductor substrate having a plurality of trenches formed on the side of the substrate opposite the first surface, each trench reaching through the silicon semiconductor substrate and the buffer layer to the gallium nitride semiconductor layer, and the inside surface of each of the trenches and the other principal surface of the silicon semiconductor substrate being covered with a metal film.
The gallium nitride semiconductor device as claimed in claim 1, wherein the buffer layer further comprises an aluminum nitride layer on the side of the silicon semiconductor substrate and a gallium nitride layer on the upper side thereof.
A method of manufacturing a gallium nitride semiconductor device comprising the steps of: 2 Appln. SN: 12/243,201 Attorney Docket No.: FUJI-051 1 preparing a silicon semiconductor substrate; forming a buffer layer on a first surface of the silicon semiconductor substrate, the buffer layer providing crystal structure conversion and/or crystal quality improvement; forming a gallium nitride semiconductor layer on the buffer layer by epitaxial growth; forming a plurality of trenches in the silicon semiconductor substrate on the other side of the semiconductor substrate, each trench being formed with a depth so that it reaches through the silicon semiconductor substrate and the buffer layer to the gallium nitride semiconductor layer on the first surface; and forming a metal film so as to cover the inside surface of each of the trenches and the other principal surface of the silicon semiconductor substrate.
The method of manufacturing a gallium nitride semiconductor device as claimed in claim 5, wherein the step of forming the buffer layer further comprises the steps of: forming an aluminum nitride layer on the side of the silicon semiconductor substrate; and forming a gallium nitride layer on the upper side the aluminum nitride layer.
Layer stacks claimed or described, ordered top of device to substrate.
vertical gallium nitride semiconductor device
Materials described outside the worked examples.
silicon semiconductor substrate
Si
buffer layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 12 is a diagram showing the forward I-V characteristic of the GaN Schottky barrier diode according to Example 3 of the invention together with that of an ordinary pin diode.
Related documents with shared materials, methods, properties, or citations.
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