Patent
US 9,257,500VERTICAL GAN POWER DEVICE WITH BREAKDOWN VOLTAGE CONTROL
Donald R. Disney
AVOGY, INC.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 9,257,500Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B illustrates how edge termination structures 60 can be used to alleviate field 15 crowding near the edge 50 of the diode. The edge termination …
FIG. 2B illustrates the formation of a second GaN layer 220 coupled to the first GaN layer 210. The second GaN layer 220 has a conductivity type different than …
FIG. 3B illustrates a corresponding cross-sectional view at a cross 15 section 390. In this embodiment, the Schottky barrier diode includes a GaN substrate …
FIG. 4B illustrates a corresponding cross-sectional view at a cross section 490. In this embodiment, 20 the JF E T 400 includes a GaN substrate 200, first GaN …
FIG. 5 is simplified flowchart illustrating an example method of fabricating a vertical 20 GaN power device, such as the diode, Schotty barrier diode, and/or the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical GaN power device, the method comprising: providing a first GaN material having a first conductivity type; forming a second GaN material having a second conductivity type and coupled to the first GaN material to create a p-n junction; and implanting ions through the second GaN material and into a first portion of the first GaN material to form an implanted region extending from within the first GaN material across the p-n junction into the second GaN material, wherein the implanted region spans a first portion of the p-n junction, such that the p-n junction extends from within the implanted region across a boundary of the implanted region into a second portion of the p-n junction, wherein the first portion of the p-n junction has a breakdown voltage which is less than a breakdown voltage of the second portion of the p-n junction.
The method of claim 1, further comprising forming the first portion of the p-n junction such that the second portion of the p-n junction is between an edge of the p-n junction and the first portion of the p-n junction.
The method of claim 1, wherein the first conductivity type is n- type.
The method of claim 1, wherein the vertical GaN power device comprises a diode.
The method of claim 1, wherein the vertical GaN power device comprises a junction field-effect transistor (JFE T).
The method of claim 1, wherein a first dopant concentration of the first GaN material in the implanted region is higher than a second dopant concentration of the first GaN material in the second portion of the p-n junction.
The method of claim 1, further comprising forming one or more edge termination structures.
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN power device with controlled breakdown region
vertical GaN diode
vertical GaN Schottky barrier diode
Materials described outside the worked examples.
first GaN material (n-type)
GaN
silicon implant ions
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is simplified flowchart illustrating an example method of fabricating a vertical 20 GaN power device, such as the diode, Schotty barrier diode, and/or the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 1000–1200 °C | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,257,500Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B illustrates how edge termination structures 60 can be used to alleviate field 15 crowding near the edge 50 of the diode. The edge termination …
FIG. 2B illustrates the formation of a second GaN layer 220 coupled to the first GaN layer 210. The second GaN layer 220 has a conductivity type different than …
FIG. 3B illustrates a corresponding cross-sectional view at a cross 15 section 390. In this embodiment, the Schottky barrier diode includes a GaN substrate …
FIG. 4B illustrates a corresponding cross-sectional view at a cross section 490. In this embodiment, 20 the JF E T 400 includes a GaN substrate 200, first GaN …
FIG. 5 is simplified flowchart illustrating an example method of fabricating a vertical 20 GaN power device, such as the diode, Schotty barrier diode, and/or the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical GaN power device, the method comprising: providing a first GaN material having a first conductivity type; forming a second GaN material having a second conductivity type and coupled to the first GaN material to create a p-n junction; and implanting ions through the second GaN material and into a first portion of the first GaN material to form an implanted region extending from within the first GaN material across the p-n junction into the second GaN material, wherein the implanted region spans a first portion of the p-n junction, such that the p-n junction extends from within the implanted region across a boundary of the implanted region into a second portion of the p-n junction, wherein the first portion of the p-n junction has a breakdown voltage which is less than a breakdown voltage of the second portion of the p-n junction.
The method of claim 1, further comprising forming the first portion of the p-n junction such that the second portion of the p-n junction is between an edge of the p-n junction and the first portion of the p-n junction.
The method of claim 1, wherein the first conductivity type is n- type.
The method of claim 1, wherein the vertical GaN power device comprises a diode.
The method of claim 1, wherein the vertical GaN power device comprises a junction field-effect transistor (JFE T).
The method of claim 1, wherein a first dopant concentration of the first GaN material in the implanted region is higher than a second dopant concentration of the first GaN material in the second portion of the p-n junction.
The method of claim 1, further comprising forming one or more edge termination structures.
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN power device with controlled breakdown region
vertical GaN diode
vertical GaN Schottky barrier diode
Materials described outside the worked examples.
first GaN material (n-type)
GaN
silicon implant ions
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is simplified flowchart illustrating an example method of fabricating a vertical 20 GaN power device, such as the diode, Schotty barrier diode, and/or the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 1000–1200 °C | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,257,500Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B illustrates how edge termination structures 60 can be used to alleviate field 15 crowding near the edge 50 of the diode. The edge termination …
FIG. 2B illustrates the formation of a second GaN layer 220 coupled to the first GaN layer 210. The second GaN layer 220 has a conductivity type different than …
FIG. 3B illustrates a corresponding cross-sectional view at a cross 15 section 390. In this embodiment, the Schottky barrier diode includes a GaN substrate …
FIG. 4B illustrates a corresponding cross-sectional view at a cross section 490. In this embodiment, 20 the JF E T 400 includes a GaN substrate 200, first GaN …
FIG. 5 is simplified flowchart illustrating an example method of fabricating a vertical 20 GaN power device, such as the diode, Schotty barrier diode, and/or the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical GaN power device, the method comprising: providing a first GaN material having a first conductivity type; forming a second GaN material having a second conductivity type and coupled to the first GaN material to create a p-n junction; and implanting ions through the second GaN material and into a first portion of the first GaN material to form an implanted region extending from within the first GaN material across the p-n junction into the second GaN material, wherein the implanted region spans a first portion of the p-n junction, such that the p-n junction extends from within the implanted region across a boundary of the implanted region into a second portion of the p-n junction, wherein the first portion of the p-n junction has a breakdown voltage which is less than a breakdown voltage of the second portion of the p-n junction.
The method of claim 1, further comprising forming the first portion of the p-n junction such that the second portion of the p-n junction is between an edge of the p-n junction and the first portion of the p-n junction.
The method of claim 1, wherein the first conductivity type is n- type.
The method of claim 1, wherein the vertical GaN power device comprises a diode.
The method of claim 1, wherein the vertical GaN power device comprises a junction field-effect transistor (JFE T).
The method of claim 1, wherein a first dopant concentration of the first GaN material in the implanted region is higher than a second dopant concentration of the first GaN material in the second portion of the p-n junction.
The method of claim 1, further comprising forming one or more edge termination structures.
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN power device with controlled breakdown region
vertical GaN diode
vertical GaN Schottky barrier diode
Materials described outside the worked examples.
first GaN material (n-type)
GaN
silicon implant ions
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is simplified flowchart illustrating an example method of fabricating a vertical 20 GaN power device, such as the diode, Schotty barrier diode, and/or the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 1000–1200 °C | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,257,500Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B illustrates how edge termination structures 60 can be used to alleviate field 15 crowding near the edge 50 of the diode. The edge termination …
FIG. 2B illustrates the formation of a second GaN layer 220 coupled to the first GaN layer 210. The second GaN layer 220 has a conductivity type different than …
FIG. 3B illustrates a corresponding cross-sectional view at a cross 15 section 390. In this embodiment, the Schottky barrier diode includes a GaN substrate …
FIG. 4B illustrates a corresponding cross-sectional view at a cross section 490. In this embodiment, 20 the JF E T 400 includes a GaN substrate 200, first GaN …
FIG. 5 is simplified flowchart illustrating an example method of fabricating a vertical 20 GaN power device, such as the diode, Schotty barrier diode, and/or the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical GaN power device, the method comprising: providing a first GaN material having a first conductivity type; forming a second GaN material having a second conductivity type and coupled to the first GaN material to create a p-n junction; and implanting ions through the second GaN material and into a first portion of the first GaN material to form an implanted region extending from within the first GaN material across the p-n junction into the second GaN material, wherein the implanted region spans a first portion of the p-n junction, such that the p-n junction extends from within the implanted region across a boundary of the implanted region into a second portion of the p-n junction, wherein the first portion of the p-n junction has a breakdown voltage which is less than a breakdown voltage of the second portion of the p-n junction.
The method of claim 1, further comprising forming the first portion of the p-n junction such that the second portion of the p-n junction is between an edge of the p-n junction and the first portion of the p-n junction.
The method of claim 1, wherein the first conductivity type is n- type.
The method of claim 1, wherein the vertical GaN power device comprises a diode.
The method of claim 1, wherein the vertical GaN power device comprises a junction field-effect transistor (JFE T).
The method of claim 1, wherein a first dopant concentration of the first GaN material in the implanted region is higher than a second dopant concentration of the first GaN material in the second portion of the p-n junction.
The method of claim 1, further comprising forming one or more edge termination structures.
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN power device with controlled breakdown region
vertical GaN diode
vertical GaN Schottky barrier diode
Materials described outside the worked examples.
first GaN material (n-type)
GaN
silicon implant ions
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is simplified flowchart illustrating an example method of fabricating a vertical 20 GaN power device, such as the diode, Schotty barrier diode, and/or the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 1000–1200 °C | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
vertical GaN junction field-effect transistor (JFET)
| — |
vertical GaN junction field-effect transistor (JFET)
| — |
vertical GaN junction field-effect transistor (JFET)
| — |
vertical GaN junction field-effect transistor (JFET)
| — |