Patent
US 10,580,768Gallium Arsenide Cell
Jui-Chieh Chiu
US
Copyright © 2026 Matter42. All rights reserved.
Patent details
Patent
US 10,580,768Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. [0012]
FIG. 2 is a schematic circuit diagram of the GaAs cell of
FIG. 3 is a schematic layout diagram of a logic circuit according to an embodiment of the present invention. [0013]
FIG. 4 is a schematic circuit diagram of the logic circuit of
FIG. 5 is a schematic circuit diagram of a logic circuit in the art. SVG 16145176.09-28-2018.JMLL₃RQVRXEAPX4.SPEC.2.26.318.2390.330.2426.svg 0.12 0.04 …
FIG. 6 is a schematic layout diagram of the logic circuit ofFIG. 5. SVG 16145176.09-28-2018.JMLL₃RQVRXEAPX4.SPEC.2.28.318.2549.330.2585.svg 0.12 0.04 Chemistry …
FIG. 7 is a schematic layout diagram of a GaAs cell accordingto an embodiment of the present invention. SVG …
FIG. 8 is a schematic layout diagram of a GaAs cell accordingto an embodiment of the present invention. SVG …
FIG. 9 is a schematic layout diagram of a logic circuitaccording to an embodiment of the present invention. [00 19]
FIG. 10 is a schematic circuit diagram of the logic circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaAs (Gallium Arsenide) cell, comprising: at least a GaAs substrates; a plurality of drain electrodes and a plurality of source electrodes, disposed on the at least a GaAs substrates; a gate electrode, disposed between the plurality of drain electrodes and the plurality of source electrodes, elongated along a first direction; a first anchor at a first end of the gate electrode; and a second anchor at a second end of the gate electrode, wherein the second anchor is apart from the first anchor; wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor and a second width of the second anchor along the second direction; wherein the plurality of drain electrodes are disposed by a first side of the gate electrode and distributed over the first direction parallel to the gate electrode; wherein the plurality of source electrodes are disposed by a second side of the gate electrode and distributed over the first direction parallel to the gate electrode; wherein the first side and the second are opposite at the second direction. Currently amended
The GaAs cell of claim 1, wherein the gate length of the gate electrode remains constant. Original
The GaAs cell of claim 1, wherein the gate length of the gate electrode is less than 0.5 m. Original
The GaAs cell of claim 1, wherein the gate electrode, the plurality of drain electrodes and the plurality of source electrodes form a plurality of transistors. Original
The GaAs cell of claim 1, wherein a first contact is formed on the first anchor, a second contact is formed on the second anchor, the first anchor is coupled to a first metal line through the first contact to receive a gate signal corresponding to a first sub-circuit, and the second anchor is coupled to a second metal line through the second contact to receive the gate signal corresponding to a second sub-circuit. Original
The GaAs cell of claim 1, wherein the plurality of drain electrodes are not directly and electrically connected. New
A logic circuit, comprising: a plurality of GaAs (Gallium Arsenide) cells, wherein a GaAs cell comprises: at least a GaAs substrates; a plurality of drain electrodes and a plurality of source electrodes, disposed on the at least a GaAs substrates; a gate electrode, disposed between the plurality of drain electrodes and the plurality of source electrodes, elongated along a first direction, wherein the gate electrode, the plurality of drain electrodes and the plurality of source electrodes form a plurality of transistors; a first anchor at a first end of the gate electrode; and a second anchor at a second end of the gate electrode, wherein the second anchor is apart from the first anchor; wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor and a second width of the second anchor along the second direction; wherein the plurality of drain electrodes are disposed by a first side of the gate electrode and distributed over the first direction parallel to the gate electrode; wherein the plurality of source electrodes are disposed by a second side of the gate electrode and distributed over the first direction parallel to the gate electrode: wherein the first side and the second are opposite at the second direction; wherein the plurality of GaAs cells are connected to each other, at least one of the gate electrode in GaAs cells receives an input signal, one of transistor in GaAs cells produces an output signal and coupled to a positive voltage supply, and one of transistor in GaAs cells is electrically connected to a ground. Currently amended
The logic circuit of claim 8, wherein at least one of GaAs cell is coupled to the positive voltage supply through at least an active load. Original
The logic circuit of claim 8, wherein at least one of GaAs cell is coupled to the positive voltage supply through at least a passive load. Original
The logic circuit of claim 8, wherein the plurality of drain electrodes are not directly and electrically connected. New
A logic circuit, comprising: a GaAs (Gallium Arsenide) cell, comprising: at least a GaAs substrates; a plurality of drain electrodes and a plurality of source electrodes, disposed on the at least a GaAs substrates; a gate electrode, disposed between the plurality of drain electrodes and the plurality of source electrodes, elongated along a first direction, wherein the gate electrode, the plurality of drain electrodes and the plurality of source electrodes form a first transistor and a second transistor; a first anchor at a first end of the gate electrode; and a second anchor at a second end of the gate electrode, wherein the second anchor is apart from the first anchor; wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor and a second width of the second anchor along the second direction; wherein the plurality of drain electrodes are disposed by a first side of the gate electrode and distributed over the first direction parallel to the gate electrode; wherein the plurality of source electrodes are disposed by a second side of the gate electrode and distributed over the first direction parallel to the gate electrode: wherein the first side and the second are opposite at the second direction; a load, coupled to the first transistor; a third transistor, coupled to the second transistor; wherein the first transistor and the load form a logic sub-circuit; wherein the second transistor and the third transistor for a buffer sub-circuit. Currently amended
The logic circuit of claim 11, wherein the logic circuit is a DCFL (Direct Coupled Field Effect Transistor Logic) inverter. Original
30 15. The logic circuit of claim 11, wherein the plurality of drain electrodes are not directly and electrically connected. New
Layer stacks claimed or described, ordered top of device to substrate.
GaAs cell
logic circuit comprising plurality of GaAs cells
Materials described outside the worked examples.
Gallium Arsenide
GaAs
Related documents with shared materials, methods, properties, or citations.
Patent details
Patent
US 10,580,768Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. [0012]
FIG. 2 is a schematic circuit diagram of the GaAs cell of
FIG. 3 is a schematic layout diagram of a logic circuit according to an embodiment of the present invention. [0013]
FIG. 4 is a schematic circuit diagram of the logic circuit of
FIG. 5 is a schematic circuit diagram of a logic circuit in the art. SVG 16145176.09-28-2018.JMLL₃RQVRXEAPX4.SPEC.2.26.318.2390.330.2426.svg 0.12 0.04 …
FIG. 6 is a schematic layout diagram of the logic circuit ofFIG. 5. SVG 16145176.09-28-2018.JMLL₃RQVRXEAPX4.SPEC.2.28.318.2549.330.2585.svg 0.12 0.04 Chemistry …
FIG. 7 is a schematic layout diagram of a GaAs cell accordingto an embodiment of the present invention. SVG …
FIG. 8 is a schematic layout diagram of a GaAs cell accordingto an embodiment of the present invention. SVG …
FIG. 9 is a schematic layout diagram of a logic circuitaccording to an embodiment of the present invention. [00 19]
FIG. 10 is a schematic circuit diagram of the logic circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaAs (Gallium Arsenide) cell, comprising: at least a GaAs substrates; a plurality of drain electrodes and a plurality of source electrodes, disposed on the at least a GaAs substrates; a gate electrode, disposed between the plurality of drain electrodes and the plurality of source electrodes, elongated along a first direction; a first anchor at a first end of the gate electrode; and a second anchor at a second end of the gate electrode, wherein the second anchor is apart from the first anchor; wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor and a second width of the second anchor along the second direction; wherein the plurality of drain electrodes are disposed by a first side of the gate electrode and distributed over the first direction parallel to the gate electrode; wherein the plurality of source electrodes are disposed by a second side of the gate electrode and distributed over the first direction parallel to the gate electrode; wherein the first side and the second are opposite at the second direction. Currently amended
The GaAs cell of claim 1, wherein the gate length of the gate electrode remains constant. Original
The GaAs cell of claim 1, wherein the gate length of the gate electrode is less than 0.5 m. Original
The GaAs cell of claim 1, wherein the gate electrode, the plurality of drain electrodes and the plurality of source electrodes form a plurality of transistors. Original
The GaAs cell of claim 1, wherein a first contact is formed on the first anchor, a second contact is formed on the second anchor, the first anchor is coupled to a first metal line through the first contact to receive a gate signal corresponding to a first sub-circuit, and the second anchor is coupled to a second metal line through the second contact to receive the gate signal corresponding to a second sub-circuit. Original
The GaAs cell of claim 1, wherein the plurality of drain electrodes are not directly and electrically connected. New
A logic circuit, comprising: a plurality of GaAs (Gallium Arsenide) cells, wherein a GaAs cell comprises: at least a GaAs substrates; a plurality of drain electrodes and a plurality of source electrodes, disposed on the at least a GaAs substrates; a gate electrode, disposed between the plurality of drain electrodes and the plurality of source electrodes, elongated along a first direction, wherein the gate electrode, the plurality of drain electrodes and the plurality of source electrodes form a plurality of transistors; a first anchor at a first end of the gate electrode; and a second anchor at a second end of the gate electrode, wherein the second anchor is apart from the first anchor; wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor and a second width of the second anchor along the second direction; wherein the plurality of drain electrodes are disposed by a first side of the gate electrode and distributed over the first direction parallel to the gate electrode; wherein the plurality of source electrodes are disposed by a second side of the gate electrode and distributed over the first direction parallel to the gate electrode: wherein the first side and the second are opposite at the second direction; wherein the plurality of GaAs cells are connected to each other, at least one of the gate electrode in GaAs cells receives an input signal, one of transistor in GaAs cells produces an output signal and coupled to a positive voltage supply, and one of transistor in GaAs cells is electrically connected to a ground. Currently amended
The logic circuit of claim 8, wherein at least one of GaAs cell is coupled to the positive voltage supply through at least an active load. Original
The logic circuit of claim 8, wherein at least one of GaAs cell is coupled to the positive voltage supply through at least a passive load. Original
The logic circuit of claim 8, wherein the plurality of drain electrodes are not directly and electrically connected. New
A logic circuit, comprising: a GaAs (Gallium Arsenide) cell, comprising: at least a GaAs substrates; a plurality of drain electrodes and a plurality of source electrodes, disposed on the at least a GaAs substrates; a gate electrode, disposed between the plurality of drain electrodes and the plurality of source electrodes, elongated along a first direction, wherein the gate electrode, the plurality of drain electrodes and the plurality of source electrodes form a first transistor and a second transistor; a first anchor at a first end of the gate electrode; and a second anchor at a second end of the gate electrode, wherein the second anchor is apart from the first anchor; wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor and a second width of the second anchor along the second direction; wherein the plurality of drain electrodes are disposed by a first side of the gate electrode and distributed over the first direction parallel to the gate electrode; wherein the plurality of source electrodes are disposed by a second side of the gate electrode and distributed over the first direction parallel to the gate electrode: wherein the first side and the second are opposite at the second direction; a load, coupled to the first transistor; a third transistor, coupled to the second transistor; wherein the first transistor and the load form a logic sub-circuit; wherein the second transistor and the third transistor for a buffer sub-circuit. Currently amended
The logic circuit of claim 11, wherein the logic circuit is a DCFL (Direct Coupled Field Effect Transistor Logic) inverter. Original
30 15. The logic circuit of claim 11, wherein the plurality of drain electrodes are not directly and electrically connected. New
Layer stacks claimed or described, ordered top of device to substrate.
GaAs cell
logic circuit comprising plurality of GaAs cells
Materials described outside the worked examples.
Gallium Arsenide
GaAs
Related documents with shared materials, methods, properties, or citations.
Patent details
Patent
US 10,580,768Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. [0012]
FIG. 2 is a schematic circuit diagram of the GaAs cell of
FIG. 3 is a schematic layout diagram of a logic circuit according to an embodiment of the present invention. [0013]
FIG. 4 is a schematic circuit diagram of the logic circuit of
FIG. 5 is a schematic circuit diagram of a logic circuit in the art. SVG 16145176.09-28-2018.JMLL₃RQVRXEAPX4.SPEC.2.26.318.2390.330.2426.svg 0.12 0.04 …
FIG. 6 is a schematic layout diagram of the logic circuit ofFIG. 5. SVG 16145176.09-28-2018.JMLL₃RQVRXEAPX4.SPEC.2.28.318.2549.330.2585.svg 0.12 0.04 Chemistry …
FIG. 7 is a schematic layout diagram of a GaAs cell accordingto an embodiment of the present invention. SVG …
FIG. 8 is a schematic layout diagram of a GaAs cell accordingto an embodiment of the present invention. SVG …
FIG. 9 is a schematic layout diagram of a logic circuitaccording to an embodiment of the present invention. [00 19]
FIG. 10 is a schematic circuit diagram of the logic circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaAs (Gallium Arsenide) cell, comprising: at least a GaAs substrates; a plurality of drain electrodes and a plurality of source electrodes, disposed on the at least a GaAs substrates; a gate electrode, disposed between the plurality of drain electrodes and the plurality of source electrodes, elongated along a first direction; a first anchor at a first end of the gate electrode; and a second anchor at a second end of the gate electrode, wherein the second anchor is apart from the first anchor; wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor and a second width of the second anchor along the second direction; wherein the plurality of drain electrodes are disposed by a first side of the gate electrode and distributed over the first direction parallel to the gate electrode; wherein the plurality of source electrodes are disposed by a second side of the gate electrode and distributed over the first direction parallel to the gate electrode; wherein the first side and the second are opposite at the second direction. Currently amended
The GaAs cell of claim 1, wherein the gate length of the gate electrode remains constant. Original
The GaAs cell of claim 1, wherein the gate length of the gate electrode is less than 0.5 m. Original
The GaAs cell of claim 1, wherein the gate electrode, the plurality of drain electrodes and the plurality of source electrodes form a plurality of transistors. Original
The GaAs cell of claim 1, wherein a first contact is formed on the first anchor, a second contact is formed on the second anchor, the first anchor is coupled to a first metal line through the first contact to receive a gate signal corresponding to a first sub-circuit, and the second anchor is coupled to a second metal line through the second contact to receive the gate signal corresponding to a second sub-circuit. Original
The GaAs cell of claim 1, wherein the plurality of drain electrodes are not directly and electrically connected. New
A logic circuit, comprising: a plurality of GaAs (Gallium Arsenide) cells, wherein a GaAs cell comprises: at least a GaAs substrates; a plurality of drain electrodes and a plurality of source electrodes, disposed on the at least a GaAs substrates; a gate electrode, disposed between the plurality of drain electrodes and the plurality of source electrodes, elongated along a first direction, wherein the gate electrode, the plurality of drain electrodes and the plurality of source electrodes form a plurality of transistors; a first anchor at a first end of the gate electrode; and a second anchor at a second end of the gate electrode, wherein the second anchor is apart from the first anchor; wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor and a second width of the second anchor along the second direction; wherein the plurality of drain electrodes are disposed by a first side of the gate electrode and distributed over the first direction parallel to the gate electrode; wherein the plurality of source electrodes are disposed by a second side of the gate electrode and distributed over the first direction parallel to the gate electrode: wherein the first side and the second are opposite at the second direction; wherein the plurality of GaAs cells are connected to each other, at least one of the gate electrode in GaAs cells receives an input signal, one of transistor in GaAs cells produces an output signal and coupled to a positive voltage supply, and one of transistor in GaAs cells is electrically connected to a ground. Currently amended
The logic circuit of claim 8, wherein at least one of GaAs cell is coupled to the positive voltage supply through at least an active load. Original
The logic circuit of claim 8, wherein at least one of GaAs cell is coupled to the positive voltage supply through at least a passive load. Original
The logic circuit of claim 8, wherein the plurality of drain electrodes are not directly and electrically connected. New
A logic circuit, comprising: a GaAs (Gallium Arsenide) cell, comprising: at least a GaAs substrates; a plurality of drain electrodes and a plurality of source electrodes, disposed on the at least a GaAs substrates; a gate electrode, disposed between the plurality of drain electrodes and the plurality of source electrodes, elongated along a first direction, wherein the gate electrode, the plurality of drain electrodes and the plurality of source electrodes form a first transistor and a second transistor; a first anchor at a first end of the gate electrode; and a second anchor at a second end of the gate electrode, wherein the second anchor is apart from the first anchor; wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor and a second width of the second anchor along the second direction; wherein the plurality of drain electrodes are disposed by a first side of the gate electrode and distributed over the first direction parallel to the gate electrode; wherein the plurality of source electrodes are disposed by a second side of the gate electrode and distributed over the first direction parallel to the gate electrode: wherein the first side and the second are opposite at the second direction; a load, coupled to the first transistor; a third transistor, coupled to the second transistor; wherein the first transistor and the load form a logic sub-circuit; wherein the second transistor and the third transistor for a buffer sub-circuit. Currently amended
The logic circuit of claim 11, wherein the logic circuit is a DCFL (Direct Coupled Field Effect Transistor Logic) inverter. Original
30 15. The logic circuit of claim 11, wherein the plurality of drain electrodes are not directly and electrically connected. New
Layer stacks claimed or described, ordered top of device to substrate.
GaAs cell
logic circuit comprising plurality of GaAs cells
Materials described outside the worked examples.
Gallium Arsenide
GaAs
Related documents with shared materials, methods, properties, or citations.
Patent details
Patent
US 10,580,768Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. [0012]
FIG. 2 is a schematic circuit diagram of the GaAs cell of
FIG. 3 is a schematic layout diagram of a logic circuit according to an embodiment of the present invention. [0013]
FIG. 4 is a schematic circuit diagram of the logic circuit of
FIG. 5 is a schematic circuit diagram of a logic circuit in the art. SVG 16145176.09-28-2018.JMLL₃RQVRXEAPX4.SPEC.2.26.318.2390.330.2426.svg 0.12 0.04 …
FIG. 6 is a schematic layout diagram of the logic circuit ofFIG. 5. SVG 16145176.09-28-2018.JMLL₃RQVRXEAPX4.SPEC.2.28.318.2549.330.2585.svg 0.12 0.04 Chemistry …
FIG. 7 is a schematic layout diagram of a GaAs cell accordingto an embodiment of the present invention. SVG …
FIG. 8 is a schematic layout diagram of a GaAs cell accordingto an embodiment of the present invention. SVG …
FIG. 9 is a schematic layout diagram of a logic circuitaccording to an embodiment of the present invention. [00 19]
FIG. 10 is a schematic circuit diagram of the logic circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaAs (Gallium Arsenide) cell, comprising: at least a GaAs substrates; a plurality of drain electrodes and a plurality of source electrodes, disposed on the at least a GaAs substrates; a gate electrode, disposed between the plurality of drain electrodes and the plurality of source electrodes, elongated along a first direction; a first anchor at a first end of the gate electrode; and a second anchor at a second end of the gate electrode, wherein the second anchor is apart from the first anchor; wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor and a second width of the second anchor along the second direction; wherein the plurality of drain electrodes are disposed by a first side of the gate electrode and distributed over the first direction parallel to the gate electrode; wherein the plurality of source electrodes are disposed by a second side of the gate electrode and distributed over the first direction parallel to the gate electrode; wherein the first side and the second are opposite at the second direction. Currently amended
The GaAs cell of claim 1, wherein the gate length of the gate electrode remains constant. Original
The GaAs cell of claim 1, wherein the gate length of the gate electrode is less than 0.5 m. Original
The GaAs cell of claim 1, wherein the gate electrode, the plurality of drain electrodes and the plurality of source electrodes form a plurality of transistors. Original
The GaAs cell of claim 1, wherein a first contact is formed on the first anchor, a second contact is formed on the second anchor, the first anchor is coupled to a first metal line through the first contact to receive a gate signal corresponding to a first sub-circuit, and the second anchor is coupled to a second metal line through the second contact to receive the gate signal corresponding to a second sub-circuit. Original
The GaAs cell of claim 1, wherein the plurality of drain electrodes are not directly and electrically connected. New
A logic circuit, comprising: a plurality of GaAs (Gallium Arsenide) cells, wherein a GaAs cell comprises: at least a GaAs substrates; a plurality of drain electrodes and a plurality of source electrodes, disposed on the at least a GaAs substrates; a gate electrode, disposed between the plurality of drain electrodes and the plurality of source electrodes, elongated along a first direction, wherein the gate electrode, the plurality of drain electrodes and the plurality of source electrodes form a plurality of transistors; a first anchor at a first end of the gate electrode; and a second anchor at a second end of the gate electrode, wherein the second anchor is apart from the first anchor; wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor and a second width of the second anchor along the second direction; wherein the plurality of drain electrodes are disposed by a first side of the gate electrode and distributed over the first direction parallel to the gate electrode; wherein the plurality of source electrodes are disposed by a second side of the gate electrode and distributed over the first direction parallel to the gate electrode: wherein the first side and the second are opposite at the second direction; wherein the plurality of GaAs cells are connected to each other, at least one of the gate electrode in GaAs cells receives an input signal, one of transistor in GaAs cells produces an output signal and coupled to a positive voltage supply, and one of transistor in GaAs cells is electrically connected to a ground. Currently amended
The logic circuit of claim 8, wherein at least one of GaAs cell is coupled to the positive voltage supply through at least an active load. Original
The logic circuit of claim 8, wherein at least one of GaAs cell is coupled to the positive voltage supply through at least a passive load. Original
The logic circuit of claim 8, wherein the plurality of drain electrodes are not directly and electrically connected. New
A logic circuit, comprising: a GaAs (Gallium Arsenide) cell, comprising: at least a GaAs substrates; a plurality of drain electrodes and a plurality of source electrodes, disposed on the at least a GaAs substrates; a gate electrode, disposed between the plurality of drain electrodes and the plurality of source electrodes, elongated along a first direction, wherein the gate electrode, the plurality of drain electrodes and the plurality of source electrodes form a first transistor and a second transistor; a first anchor at a first end of the gate electrode; and a second anchor at a second end of the gate electrode, wherein the second anchor is apart from the first anchor; wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor and a second width of the second anchor along the second direction; wherein the plurality of drain electrodes are disposed by a first side of the gate electrode and distributed over the first direction parallel to the gate electrode; wherein the plurality of source electrodes are disposed by a second side of the gate electrode and distributed over the first direction parallel to the gate electrode: wherein the first side and the second are opposite at the second direction; a load, coupled to the first transistor; a third transistor, coupled to the second transistor; wherein the first transistor and the load form a logic sub-circuit; wherein the second transistor and the third transistor for a buffer sub-circuit. Currently amended
The logic circuit of claim 11, wherein the logic circuit is a DCFL (Direct Coupled Field Effect Transistor Logic) inverter. Original
30 15. The logic circuit of claim 11, wherein the plurality of drain electrodes are not directly and electrically connected. New
Layer stacks claimed or described, ordered top of device to substrate.
GaAs cell
logic circuit comprising plurality of GaAs cells
Materials described outside the worked examples.
Gallium Arsenide
GaAs
Related documents with shared materials, methods, properties, or citations.
logic circuit comprising single GaAs cell with logic and buffer sub-circuits
HEMT (High Electron Mobility Transistor) within GaAs cell
logic circuit comprising single GaAs cell with logic and buffer sub-circuits
HEMT (High Electron Mobility Transistor) within GaAs cell
logic circuit comprising single GaAs cell with logic and buffer sub-circuits
HEMT (High Electron Mobility Transistor) within GaAs cell
logic circuit comprising single GaAs cell with logic and buffer sub-circuits
HEMT (High Electron Mobility Transistor) within GaAs cell