Patent
US 10,432,200Gallium Arsenide Cell and Logic Circuit
Jui-Chieh Chiu
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,432,200Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. [0011]
FIG. 2 is a schematic circuit diagram of the GaAs cell of
FIG. 3 is a curve of gate-to-gate spacing versus equivalent resistance. [0012]
FIG. 4 is a schematic layout diagram of a GaAs cell in the art. [0013]
FIG. 5 is a schematic circuit diagram of a logic circuit according to an embodiment of the present invention. [0014]
FIG. 6 is a schematic layout diagram of the logic circuit of
FIG. 7 is a schematic layout diagram of a logic circuit in the art. [0016]
FIG. 8 is a schematic layout diagram of a GaAs cell according to an embodiment of the present invention. [0017]
FIG. 9 is a schematic layout diagram of a GaAs cell according to an embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaAs (Gallium Arsenide) cell, comprising: a GaAs substrate; a drain electrode and a source electrode, disposed on the GaAs substrate; a plurality of gate electrodes, disposed between the drain electrode and the source electrode, elongated on a first direction, wherein a gate electrode among the plurality of gate electrodes comprises a first end and a second end; a plurality of first anchors, wherein a first anchor among the plurality of first anchors is disposed at a first end of the gate electrode; and a plurality of second anchors, wherein a second anchor among the plurality of second anchors is disposed at a second end of the gate electrode; wherein a first gate electrode and a second gate electrode among the plurality of gate electrodes are spaced by a gate-to-gate spacing, the first gate electrode and the drain electrode are spaced by a first gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the first gate-to-terminal spacing.
The GaAs cell of claim 1, wherein the second gate electrode and the source electrode are spaced by a second gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the second gate-to-terminal spacing.
The GaAs cell of claim 1, wherein a side of the gate electrode is aligned with a side of the first anchor corresponding to the gate electrode.
The GaAs cell of claim 1, wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor corresponding to the gate electrode and a second width of the second anchor corresponding to the gate electrode along the second direction.
The GaAs cell of claim 1, wherein a gate length of the gate electrode on a second direction is less than or equal to 0.5 pm.
The GaAs cell of claim 1, wherein the gate-to-gate spacing is between 0.7 pm and 1 pm.
The GaAs cell of claim 1, wherein the second anchor among the plurality of second anchors is coupled to a metal line through a contact, to receive a gate signal.
The CaAs cell of claim 1, wherein a first side of the first anchor, a second side of the second anchor and a side of the gate electrode are aligned.
A logic circuit, comprising: a GaAs (Gallium Arsenide) cell, comprising: a GaAs substrate; a drain electrode and a source electrode, disposed on the GaAs substrate; a plurality of gate electrodes, disposed between the drain electrode and the source electrode, wherein a gate electrode among the plurality of gate electrodes comprises a first end and a second end; a plurality of first anchors, wherein a first anchor among the plurality of first anchors is disposed at a first end of the gate electrode; and a plurality of second anchors, wherein a second anchor among the plurality of second anchors is disposed at a second end of the gate electrode; wherein a first gate electrode and a second gate electrode among the plurality of gate electrodes are spaced by a gate-to-gate spacing, the first gate electrode and the drain electrode are spaced by a first gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the first gate-to-terminal spacing; and a load circuit, comprising a first terminal and a second terminal, wherein the first terminal receives a positive voltage and the second terminal is connected to the drain electrode.
The logic circuit of claim 9, wherein the load circuit comprises a resistor.
The logic circuit of claim 9, wherein the load circuit comprises a transistor.
The logic circuit of claim 9, wherein the second gate electrode and the source electrode are spaced by a second gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the second gate-to-terminal spacing.
The logic circuit of claim 9, wherein a side of the gate electrode is aligned with a side of the first anchor corresponding to the gate electrode.
The logic circuit of claim 9, wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor corresponding to the gate electrode and a second width of the second anchor corresponding to the gate electrode along the second direction.
The logic circuit of claim 9, wherein a gate length of the gate electrode on a second direction is equal to or less than 0.5 pm.
The logic circuit of claim 9, wherein the gate-to-gate spacing is between 0.7 p m and 1 pm.
The logic circuit of claim 9, wherein the second anchor among the plurality of second anchors is coupled to a metal line through a contact, to receive a gate signal.
The logic circuit of claim 9, wherein a first side of the first anchor, a second side of the second anchor and a side of the gate electrode are aligned.
Layer stacks claimed or described, ordered top of device to substrate.
GaAs cell (HEMT-based transistor with multiple gate electrodes and anchors)
Logic circuit (NAND gate comprising GaAs cell and load circuit)
No layer stack recorded.
Materials described outside the worked examples.
Gallium Arsenide
GaAs
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
equivalent resistance between two gate electrodes at gate-to-gate spacing > 1 µm | >0.8 kΩ | GaAs |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,432,200Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. [0011]
FIG. 2 is a schematic circuit diagram of the GaAs cell of
FIG. 3 is a curve of gate-to-gate spacing versus equivalent resistance. [0012]
FIG. 4 is a schematic layout diagram of a GaAs cell in the art. [0013]
FIG. 5 is a schematic circuit diagram of a logic circuit according to an embodiment of the present invention. [0014]
FIG. 6 is a schematic layout diagram of the logic circuit of
FIG. 7 is a schematic layout diagram of a logic circuit in the art. [0016]
FIG. 8 is a schematic layout diagram of a GaAs cell according to an embodiment of the present invention. [0017]
FIG. 9 is a schematic layout diagram of a GaAs cell according to an embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaAs (Gallium Arsenide) cell, comprising: a GaAs substrate; a drain electrode and a source electrode, disposed on the GaAs substrate; a plurality of gate electrodes, disposed between the drain electrode and the source electrode, elongated on a first direction, wherein a gate electrode among the plurality of gate electrodes comprises a first end and a second end; a plurality of first anchors, wherein a first anchor among the plurality of first anchors is disposed at a first end of the gate electrode; and a plurality of second anchors, wherein a second anchor among the plurality of second anchors is disposed at a second end of the gate electrode; wherein a first gate electrode and a second gate electrode among the plurality of gate electrodes are spaced by a gate-to-gate spacing, the first gate electrode and the drain electrode are spaced by a first gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the first gate-to-terminal spacing.
The GaAs cell of claim 1, wherein the second gate electrode and the source electrode are spaced by a second gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the second gate-to-terminal spacing.
The GaAs cell of claim 1, wherein a side of the gate electrode is aligned with a side of the first anchor corresponding to the gate electrode.
The GaAs cell of claim 1, wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor corresponding to the gate electrode and a second width of the second anchor corresponding to the gate electrode along the second direction.
The GaAs cell of claim 1, wherein a gate length of the gate electrode on a second direction is less than or equal to 0.5 pm.
The GaAs cell of claim 1, wherein the gate-to-gate spacing is between 0.7 pm and 1 pm.
The GaAs cell of claim 1, wherein the second anchor among the plurality of second anchors is coupled to a metal line through a contact, to receive a gate signal.
The CaAs cell of claim 1, wherein a first side of the first anchor, a second side of the second anchor and a side of the gate electrode are aligned.
A logic circuit, comprising: a GaAs (Gallium Arsenide) cell, comprising: a GaAs substrate; a drain electrode and a source electrode, disposed on the GaAs substrate; a plurality of gate electrodes, disposed between the drain electrode and the source electrode, wherein a gate electrode among the plurality of gate electrodes comprises a first end and a second end; a plurality of first anchors, wherein a first anchor among the plurality of first anchors is disposed at a first end of the gate electrode; and a plurality of second anchors, wherein a second anchor among the plurality of second anchors is disposed at a second end of the gate electrode; wherein a first gate electrode and a second gate electrode among the plurality of gate electrodes are spaced by a gate-to-gate spacing, the first gate electrode and the drain electrode are spaced by a first gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the first gate-to-terminal spacing; and a load circuit, comprising a first terminal and a second terminal, wherein the first terminal receives a positive voltage and the second terminal is connected to the drain electrode.
The logic circuit of claim 9, wherein the load circuit comprises a resistor.
The logic circuit of claim 9, wherein the load circuit comprises a transistor.
The logic circuit of claim 9, wherein the second gate electrode and the source electrode are spaced by a second gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the second gate-to-terminal spacing.
The logic circuit of claim 9, wherein a side of the gate electrode is aligned with a side of the first anchor corresponding to the gate electrode.
The logic circuit of claim 9, wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor corresponding to the gate electrode and a second width of the second anchor corresponding to the gate electrode along the second direction.
The logic circuit of claim 9, wherein a gate length of the gate electrode on a second direction is equal to or less than 0.5 pm.
The logic circuit of claim 9, wherein the gate-to-gate spacing is between 0.7 p m and 1 pm.
The logic circuit of claim 9, wherein the second anchor among the plurality of second anchors is coupled to a metal line through a contact, to receive a gate signal.
The logic circuit of claim 9, wherein a first side of the first anchor, a second side of the second anchor and a side of the gate electrode are aligned.
Layer stacks claimed or described, ordered top of device to substrate.
GaAs cell (HEMT-based transistor with multiple gate electrodes and anchors)
Logic circuit (NAND gate comprising GaAs cell and load circuit)
No layer stack recorded.
Materials described outside the worked examples.
Gallium Arsenide
GaAs
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
equivalent resistance between two gate electrodes at gate-to-gate spacing > 1 µm | >0.8 kΩ | GaAs |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,432,200Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. [0011]
FIG. 2 is a schematic circuit diagram of the GaAs cell of
FIG. 3 is a curve of gate-to-gate spacing versus equivalent resistance. [0012]
FIG. 4 is a schematic layout diagram of a GaAs cell in the art. [0013]
FIG. 5 is a schematic circuit diagram of a logic circuit according to an embodiment of the present invention. [0014]
FIG. 6 is a schematic layout diagram of the logic circuit of
FIG. 7 is a schematic layout diagram of a logic circuit in the art. [0016]
FIG. 8 is a schematic layout diagram of a GaAs cell according to an embodiment of the present invention. [0017]
FIG. 9 is a schematic layout diagram of a GaAs cell according to an embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaAs (Gallium Arsenide) cell, comprising: a GaAs substrate; a drain electrode and a source electrode, disposed on the GaAs substrate; a plurality of gate electrodes, disposed between the drain electrode and the source electrode, elongated on a first direction, wherein a gate electrode among the plurality of gate electrodes comprises a first end and a second end; a plurality of first anchors, wherein a first anchor among the plurality of first anchors is disposed at a first end of the gate electrode; and a plurality of second anchors, wherein a second anchor among the plurality of second anchors is disposed at a second end of the gate electrode; wherein a first gate electrode and a second gate electrode among the plurality of gate electrodes are spaced by a gate-to-gate spacing, the first gate electrode and the drain electrode are spaced by a first gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the first gate-to-terminal spacing.
The GaAs cell of claim 1, wherein the second gate electrode and the source electrode are spaced by a second gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the second gate-to-terminal spacing.
The GaAs cell of claim 1, wherein a side of the gate electrode is aligned with a side of the first anchor corresponding to the gate electrode.
The GaAs cell of claim 1, wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor corresponding to the gate electrode and a second width of the second anchor corresponding to the gate electrode along the second direction.
The GaAs cell of claim 1, wherein a gate length of the gate electrode on a second direction is less than or equal to 0.5 pm.
The GaAs cell of claim 1, wherein the gate-to-gate spacing is between 0.7 pm and 1 pm.
The GaAs cell of claim 1, wherein the second anchor among the plurality of second anchors is coupled to a metal line through a contact, to receive a gate signal.
The CaAs cell of claim 1, wherein a first side of the first anchor, a second side of the second anchor and a side of the gate electrode are aligned.
A logic circuit, comprising: a GaAs (Gallium Arsenide) cell, comprising: a GaAs substrate; a drain electrode and a source electrode, disposed on the GaAs substrate; a plurality of gate electrodes, disposed between the drain electrode and the source electrode, wherein a gate electrode among the plurality of gate electrodes comprises a first end and a second end; a plurality of first anchors, wherein a first anchor among the plurality of first anchors is disposed at a first end of the gate electrode; and a plurality of second anchors, wherein a second anchor among the plurality of second anchors is disposed at a second end of the gate electrode; wherein a first gate electrode and a second gate electrode among the plurality of gate electrodes are spaced by a gate-to-gate spacing, the first gate electrode and the drain electrode are spaced by a first gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the first gate-to-terminal spacing; and a load circuit, comprising a first terminal and a second terminal, wherein the first terminal receives a positive voltage and the second terminal is connected to the drain electrode.
The logic circuit of claim 9, wherein the load circuit comprises a resistor.
The logic circuit of claim 9, wherein the load circuit comprises a transistor.
The logic circuit of claim 9, wherein the second gate electrode and the source electrode are spaced by a second gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the second gate-to-terminal spacing.
The logic circuit of claim 9, wherein a side of the gate electrode is aligned with a side of the first anchor corresponding to the gate electrode.
The logic circuit of claim 9, wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor corresponding to the gate electrode and a second width of the second anchor corresponding to the gate electrode along the second direction.
The logic circuit of claim 9, wherein a gate length of the gate electrode on a second direction is equal to or less than 0.5 pm.
The logic circuit of claim 9, wherein the gate-to-gate spacing is between 0.7 p m and 1 pm.
The logic circuit of claim 9, wherein the second anchor among the plurality of second anchors is coupled to a metal line through a contact, to receive a gate signal.
The logic circuit of claim 9, wherein a first side of the first anchor, a second side of the second anchor and a side of the gate electrode are aligned.
Layer stacks claimed or described, ordered top of device to substrate.
GaAs cell (HEMT-based transistor with multiple gate electrodes and anchors)
Logic circuit (NAND gate comprising GaAs cell and load circuit)
No layer stack recorded.
Materials described outside the worked examples.
Gallium Arsenide
GaAs
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
equivalent resistance between two gate electrodes at gate-to-gate spacing > 1 µm | >0.8 kΩ | GaAs |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,432,200Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. [0011]
FIG. 2 is a schematic circuit diagram of the GaAs cell of
FIG. 3 is a curve of gate-to-gate spacing versus equivalent resistance. [0012]
FIG. 4 is a schematic layout diagram of a GaAs cell in the art. [0013]
FIG. 5 is a schematic circuit diagram of a logic circuit according to an embodiment of the present invention. [0014]
FIG. 6 is a schematic layout diagram of the logic circuit of
FIG. 7 is a schematic layout diagram of a logic circuit in the art. [0016]
FIG. 8 is a schematic layout diagram of a GaAs cell according to an embodiment of the present invention. [0017]
FIG. 9 is a schematic layout diagram of a GaAs cell according to an embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaAs (Gallium Arsenide) cell, comprising: a GaAs substrate; a drain electrode and a source electrode, disposed on the GaAs substrate; a plurality of gate electrodes, disposed between the drain electrode and the source electrode, elongated on a first direction, wherein a gate electrode among the plurality of gate electrodes comprises a first end and a second end; a plurality of first anchors, wherein a first anchor among the plurality of first anchors is disposed at a first end of the gate electrode; and a plurality of second anchors, wherein a second anchor among the plurality of second anchors is disposed at a second end of the gate electrode; wherein a first gate electrode and a second gate electrode among the plurality of gate electrodes are spaced by a gate-to-gate spacing, the first gate electrode and the drain electrode are spaced by a first gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the first gate-to-terminal spacing.
The GaAs cell of claim 1, wherein the second gate electrode and the source electrode are spaced by a second gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the second gate-to-terminal spacing.
The GaAs cell of claim 1, wherein a side of the gate electrode is aligned with a side of the first anchor corresponding to the gate electrode.
The GaAs cell of claim 1, wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor corresponding to the gate electrode and a second width of the second anchor corresponding to the gate electrode along the second direction.
The GaAs cell of claim 1, wherein a gate length of the gate electrode on a second direction is less than or equal to 0.5 pm.
The GaAs cell of claim 1, wherein the gate-to-gate spacing is between 0.7 pm and 1 pm.
The GaAs cell of claim 1, wherein the second anchor among the plurality of second anchors is coupled to a metal line through a contact, to receive a gate signal.
The CaAs cell of claim 1, wherein a first side of the first anchor, a second side of the second anchor and a side of the gate electrode are aligned.
A logic circuit, comprising: a GaAs (Gallium Arsenide) cell, comprising: a GaAs substrate; a drain electrode and a source electrode, disposed on the GaAs substrate; a plurality of gate electrodes, disposed between the drain electrode and the source electrode, wherein a gate electrode among the plurality of gate electrodes comprises a first end and a second end; a plurality of first anchors, wherein a first anchor among the plurality of first anchors is disposed at a first end of the gate electrode; and a plurality of second anchors, wherein a second anchor among the plurality of second anchors is disposed at a second end of the gate electrode; wherein a first gate electrode and a second gate electrode among the plurality of gate electrodes are spaced by a gate-to-gate spacing, the first gate electrode and the drain electrode are spaced by a first gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the first gate-to-terminal spacing; and a load circuit, comprising a first terminal and a second terminal, wherein the first terminal receives a positive voltage and the second terminal is connected to the drain electrode.
The logic circuit of claim 9, wherein the load circuit comprises a resistor.
The logic circuit of claim 9, wherein the load circuit comprises a transistor.
The logic circuit of claim 9, wherein the second gate electrode and the source electrode are spaced by a second gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the second gate-to-terminal spacing.
The logic circuit of claim 9, wherein a side of the gate electrode is aligned with a side of the first anchor corresponding to the gate electrode.
The logic circuit of claim 9, wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor corresponding to the gate electrode and a second width of the second anchor corresponding to the gate electrode along the second direction.
The logic circuit of claim 9, wherein a gate length of the gate electrode on a second direction is equal to or less than 0.5 pm.
The logic circuit of claim 9, wherein the gate-to-gate spacing is between 0.7 p m and 1 pm.
The logic circuit of claim 9, wherein the second anchor among the plurality of second anchors is coupled to a metal line through a contact, to receive a gate signal.
The logic circuit of claim 9, wherein a first side of the first anchor, a second side of the second anchor and a side of the gate electrode are aligned.
Layer stacks claimed or described, ordered top of device to substrate.
GaAs cell (HEMT-based transistor with multiple gate electrodes and anchors)
Logic circuit (NAND gate comprising GaAs cell and load circuit)
No layer stack recorded.
Materials described outside the worked examples.
Gallium Arsenide
GaAs
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
equivalent resistance between two gate electrodes at gate-to-gate spacing > 1 µm | >0.8 kΩ | GaAs |
Related documents with shared materials, methods, properties, or citations.
PSEUDOMORPHIC INGAAS ON GAAS FOR GATE-ALL-AROUND TRANSISTORS
PSEUDOMORPHIC INGAAS ON GAAS FOR GATE-ALL-AROUND TRANSISTORS
PSEUDOMORPHIC INGAAS ON GAAS FOR GATE-ALL-AROUND TRANSISTORS