Patent
US 9,246,062Zinc Stannate Ohmic Contacts for P-Type Gallium Nitride
Jianhua Hu, Heng Kai Hsu, Tong Ju, Minh Huu Le et al.
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,246,062Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A. Optional step 603 of patterning a formed layer and/or forming one or more intervening layers (e.g., buffer layers, barrier layers, seed or nucleation …
FIG. 2 is a block diagram of an example of a PVD chamber configured for co-sputtering. Substrate 201 receives a first sputtered material 262 from a first target …
FIG. 3. Step 401 of preparing the substrate and any underlying layer(s) may include, for example, cleaning and degassing the substrate, forming a p-GaN …
FIG. 4. [0054] Although the foregoing examples have been described in some detail to aid understanding, the invention is not limited to the details in the …
FIG. 5 E or 5 F formed by constructing a nanolaminate with varying thicknesses or distributions of layers 55 1, 552 and/or 553). [0052]
FIG. 6 is a flowchart of an example process for fabricating an LED stack. Detailed Description of Example Embodiments [0019] A detailed description of one or …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device, comprising: a semiconductor layer having a work function greater than or equal to 4.2 eV; and a conductive layer adjacent to the semiconductor layer; wherein the conductive layer comprises zinc, tin, and oxygen; wherein a weight ratio of zinc to tin in the conductive layer is between about 1:2 and about 2:1; and wherein the conductive layer is operable as an ohmic contact to the semiconductor layer.
The device of claim 1, wherein the semiconductor layer comprises p-GaN.
The device of claim 1, wherein a thickness of the conductive layer is between about 2 0nm and about 200nm.
The device of claim 1, wherein a thickness of the conductive layer is between about 100 nm.
The device of claim 1, wherein a work function of the conductive layer is greater than about 5 eV.
The device of claim 1, wherein the conductive layer further comprises a dopant.
The device of claim 1, wherein the conductive layer is at least 30% crystalline.
The device of claim 1, wherein the conductive layer has absorption coefficient below 0.03%/nm for wavelengths between about 400nm and about 800nm. 15 PATENT Docket No. I M1252US
A method, comprising: providing a substrate comprising a semiconductor structure; and forming a conductive layer over the semiconductor structure; wherein a work function of the semiconductor structure is greater than about 4.2 eV; wherein the conductive layer is operable as an ohmic contact to the semiconductor structure; wherein the conductive layer comprises zinc, tin, and oxygen; and wherein a weight ratio of zinc to tin in the conductive layer is between about 1:2 and about 2:1.
The method of claim 11, wherein the forming of the conductive layer comprises sputtering.
The method of claim 11, wherein the forming of the conductive layer comprises doping with wt% or less of indium or aluminum.
The method of claim 11, wherein the forming of the conductive layer comprises co- sputtering from a zinc oxide target and a tin oxide target.
The method of claim 11, wherein the forming of the conductive layer comprises annealing.
Layer stacks claimed or described, ordered top of device to substrate.
optoelectronic device with zinc stannate ohmic contact
Materials described outside the worked examples.
zinc stannate
ZnSnO₃
high-work-function semiconductor
p-GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
absorption coefficient below 0.03%/nm for 400-800 nm | ≤ 0.03 %/nm | ZnSnO₃ |
conductive layer work function >5 eV | ≥ 5 eV |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,246,062Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A. Optional step 603 of patterning a formed layer and/or forming one or more intervening layers (e.g., buffer layers, barrier layers, seed or nucleation …
FIG. 2 is a block diagram of an example of a PVD chamber configured for co-sputtering. Substrate 201 receives a first sputtered material 262 from a first target …
FIG. 3. Step 401 of preparing the substrate and any underlying layer(s) may include, for example, cleaning and degassing the substrate, forming a p-GaN …
FIG. 4. [0054] Although the foregoing examples have been described in some detail to aid understanding, the invention is not limited to the details in the …
FIG. 5 E or 5 F formed by constructing a nanolaminate with varying thicknesses or distributions of layers 55 1, 552 and/or 553). [0052]
FIG. 6 is a flowchart of an example process for fabricating an LED stack. Detailed Description of Example Embodiments [0019] A detailed description of one or …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device, comprising: a semiconductor layer having a work function greater than or equal to 4.2 eV; and a conductive layer adjacent to the semiconductor layer; wherein the conductive layer comprises zinc, tin, and oxygen; wherein a weight ratio of zinc to tin in the conductive layer is between about 1:2 and about 2:1; and wherein the conductive layer is operable as an ohmic contact to the semiconductor layer.
The device of claim 1, wherein the semiconductor layer comprises p-GaN.
The device of claim 1, wherein a thickness of the conductive layer is between about 2 0nm and about 200nm.
The device of claim 1, wherein a thickness of the conductive layer is between about 100 nm.
The device of claim 1, wherein a work function of the conductive layer is greater than about 5 eV.
The device of claim 1, wherein the conductive layer further comprises a dopant.
The device of claim 1, wherein the conductive layer is at least 30% crystalline.
The device of claim 1, wherein the conductive layer has absorption coefficient below 0.03%/nm for wavelengths between about 400nm and about 800nm. 15 PATENT Docket No. I M1252US
A method, comprising: providing a substrate comprising a semiconductor structure; and forming a conductive layer over the semiconductor structure; wherein a work function of the semiconductor structure is greater than about 4.2 eV; wherein the conductive layer is operable as an ohmic contact to the semiconductor structure; wherein the conductive layer comprises zinc, tin, and oxygen; and wherein a weight ratio of zinc to tin in the conductive layer is between about 1:2 and about 2:1.
The method of claim 11, wherein the forming of the conductive layer comprises sputtering.
The method of claim 11, wherein the forming of the conductive layer comprises doping with wt% or less of indium or aluminum.
The method of claim 11, wherein the forming of the conductive layer comprises co- sputtering from a zinc oxide target and a tin oxide target.
The method of claim 11, wherein the forming of the conductive layer comprises annealing.
Layer stacks claimed or described, ordered top of device to substrate.
optoelectronic device with zinc stannate ohmic contact
Materials described outside the worked examples.
zinc stannate
ZnSnO₃
high-work-function semiconductor
p-GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
absorption coefficient below 0.03%/nm for 400-800 nm | ≤ 0.03 %/nm | ZnSnO₃ |
conductive layer work function >5 eV | ≥ 5 eV |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,246,062Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A. Optional step 603 of patterning a formed layer and/or forming one or more intervening layers (e.g., buffer layers, barrier layers, seed or nucleation …
FIG. 2 is a block diagram of an example of a PVD chamber configured for co-sputtering. Substrate 201 receives a first sputtered material 262 from a first target …
FIG. 3. Step 401 of preparing the substrate and any underlying layer(s) may include, for example, cleaning and degassing the substrate, forming a p-GaN …
FIG. 4. [0054] Although the foregoing examples have been described in some detail to aid understanding, the invention is not limited to the details in the …
FIG. 5 E or 5 F formed by constructing a nanolaminate with varying thicknesses or distributions of layers 55 1, 552 and/or 553). [0052]
FIG. 6 is a flowchart of an example process for fabricating an LED stack. Detailed Description of Example Embodiments [0019] A detailed description of one or …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device, comprising: a semiconductor layer having a work function greater than or equal to 4.2 eV; and a conductive layer adjacent to the semiconductor layer; wherein the conductive layer comprises zinc, tin, and oxygen; wherein a weight ratio of zinc to tin in the conductive layer is between about 1:2 and about 2:1; and wherein the conductive layer is operable as an ohmic contact to the semiconductor layer.
The device of claim 1, wherein the semiconductor layer comprises p-GaN.
The device of claim 1, wherein a thickness of the conductive layer is between about 2 0nm and about 200nm.
The device of claim 1, wherein a thickness of the conductive layer is between about 100 nm.
The device of claim 1, wherein a work function of the conductive layer is greater than about 5 eV.
The device of claim 1, wherein the conductive layer further comprises a dopant.
The device of claim 1, wherein the conductive layer is at least 30% crystalline.
The device of claim 1, wherein the conductive layer has absorption coefficient below 0.03%/nm for wavelengths between about 400nm and about 800nm. 15 PATENT Docket No. I M1252US
A method, comprising: providing a substrate comprising a semiconductor structure; and forming a conductive layer over the semiconductor structure; wherein a work function of the semiconductor structure is greater than about 4.2 eV; wherein the conductive layer is operable as an ohmic contact to the semiconductor structure; wherein the conductive layer comprises zinc, tin, and oxygen; and wherein a weight ratio of zinc to tin in the conductive layer is between about 1:2 and about 2:1.
The method of claim 11, wherein the forming of the conductive layer comprises sputtering.
The method of claim 11, wherein the forming of the conductive layer comprises doping with wt% or less of indium or aluminum.
The method of claim 11, wherein the forming of the conductive layer comprises co- sputtering from a zinc oxide target and a tin oxide target.
The method of claim 11, wherein the forming of the conductive layer comprises annealing.
Layer stacks claimed or described, ordered top of device to substrate.
optoelectronic device with zinc stannate ohmic contact
Materials described outside the worked examples.
zinc stannate
ZnSnO₃
high-work-function semiconductor
p-GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
absorption coefficient below 0.03%/nm for 400-800 nm | ≤ 0.03 %/nm | ZnSnO₃ |
conductive layer work function >5 eV | ≥ 5 eV |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,246,062Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A. Optional step 603 of patterning a formed layer and/or forming one or more intervening layers (e.g., buffer layers, barrier layers, seed or nucleation …
FIG. 2 is a block diagram of an example of a PVD chamber configured for co-sputtering. Substrate 201 receives a first sputtered material 262 from a first target …
FIG. 3. Step 401 of preparing the substrate and any underlying layer(s) may include, for example, cleaning and degassing the substrate, forming a p-GaN …
FIG. 4. [0054] Although the foregoing examples have been described in some detail to aid understanding, the invention is not limited to the details in the …
FIG. 5 E or 5 F formed by constructing a nanolaminate with varying thicknesses or distributions of layers 55 1, 552 and/or 553). [0052]
FIG. 6 is a flowchart of an example process for fabricating an LED stack. Detailed Description of Example Embodiments [0019] A detailed description of one or …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device, comprising: a semiconductor layer having a work function greater than or equal to 4.2 eV; and a conductive layer adjacent to the semiconductor layer; wherein the conductive layer comprises zinc, tin, and oxygen; wherein a weight ratio of zinc to tin in the conductive layer is between about 1:2 and about 2:1; and wherein the conductive layer is operable as an ohmic contact to the semiconductor layer.
The device of claim 1, wherein the semiconductor layer comprises p-GaN.
The device of claim 1, wherein a thickness of the conductive layer is between about 2 0nm and about 200nm.
The device of claim 1, wherein a thickness of the conductive layer is between about 100 nm.
The device of claim 1, wherein a work function of the conductive layer is greater than about 5 eV.
The device of claim 1, wherein the conductive layer further comprises a dopant.
The device of claim 1, wherein the conductive layer is at least 30% crystalline.
The device of claim 1, wherein the conductive layer has absorption coefficient below 0.03%/nm for wavelengths between about 400nm and about 800nm. 15 PATENT Docket No. I M1252US
A method, comprising: providing a substrate comprising a semiconductor structure; and forming a conductive layer over the semiconductor structure; wherein a work function of the semiconductor structure is greater than about 4.2 eV; wherein the conductive layer is operable as an ohmic contact to the semiconductor structure; wherein the conductive layer comprises zinc, tin, and oxygen; and wherein a weight ratio of zinc to tin in the conductive layer is between about 1:2 and about 2:1.
The method of claim 11, wherein the forming of the conductive layer comprises sputtering.
The method of claim 11, wherein the forming of the conductive layer comprises doping with wt% or less of indium or aluminum.
The method of claim 11, wherein the forming of the conductive layer comprises co- sputtering from a zinc oxide target and a tin oxide target.
The method of claim 11, wherein the forming of the conductive layer comprises annealing.
Layer stacks claimed or described, ordered top of device to substrate.
optoelectronic device with zinc stannate ohmic contact
Materials described outside the worked examples.
zinc stannate
ZnSnO₃
high-work-function semiconductor
p-GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
absorption coefficient below 0.03%/nm for 400-800 nm | ≤ 0.03 %/nm | ZnSnO₃ |
conductive layer work function >5 eV | ≥ 5 eV |
Related documents with shared materials, methods, properties, or citations.
dopant (aluminum or indium)
zinc oxide sputtering target
ZnO
tin oxide sputtering target
SnO₂
semiconductor layer work function >=4.2 eV | ≥ 4.2 eV | high-work-function semiconductor |
contact resistance <0.005 Ohm-cm2 | ≤ 0.005 Ohm-cm2 | ZnSnO₃ |
Thickness | 400–800 nm | — |
Duration | 3–10 minutes | — |
dopant (aluminum or indium)
zinc oxide sputtering target
ZnO
tin oxide sputtering target
SnO₂
semiconductor layer work function >=4.2 eV | ≥ 4.2 eV | high-work-function semiconductor |
contact resistance <0.005 Ohm-cm2 | ≤ 0.005 Ohm-cm2 | ZnSnO₃ |
Thickness | 400–800 nm | — |
Duration | 3–10 minutes | — |
dopant (aluminum or indium)
zinc oxide sputtering target
ZnO
tin oxide sputtering target
SnO₂
semiconductor layer work function >=4.2 eV | ≥ 4.2 eV | high-work-function semiconductor |
contact resistance <0.005 Ohm-cm2 | ≤ 0.005 Ohm-cm2 | ZnSnO₃ |
Thickness | 400–800 nm | — |
Duration | 3–10 minutes | — |
dopant (aluminum or indium)
zinc oxide sputtering target
ZnO
tin oxide sputtering target
SnO₂
semiconductor layer work function >=4.2 eV | ≥ 4.2 eV | high-work-function semiconductor |
contact resistance <0.005 Ohm-cm2 | ≤ 0.005 Ohm-cm2 | ZnSnO₃ |
Thickness | 400–800 nm | — |
Duration | 3–10 minutes | — |