Patent
US 8,497,499METHOD TO MODIFY THE CONDUCTIVITY OF GRAPHENE
Dragomir Davidovic
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,497,499Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A is a top plan view of one embodiment of a graphene transistor. [0015]
FIG. 2 is a graph showing resistance as a function of gate voltage in one experimental embodiment.
FIG. 3, relates resistance measurements of the graphene ribbon embodied in a field effect transistor in the experimental embodiment as a function of a voltage …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gated electrical device, comprising: a. a non-conductive substrate; b. a flat graphene structure disposed on the non-conductive substrate; c. a metal gate deposited directly on a portion of the flat graphene structure, the metal gate including a first metal that has a high contact resistance with graphene wherein the first metal comprises copper; and d. two electrical contacts, each placed on the flat graphene structure so that the metal gate is disposed between the two electrical contacts.
The gated electrical device of Claim 1, wherein the substrate comprises a material selected from a group consisting of: silicon oxide and silicon carbide.
The gated electrical device of Claim 1, wherein the graphene structure comprises a graphene ribbon.
The gated electrical device of Claim 1, wherein the graphene structure comprises a single layer of graphene.
The gated electrical device of Claim 1, wherein the graphene structure comprises a plurality of layers of graphene.
The gated electrical device of Claim 1, wherein the graphene structure has a Fermi surface that includes a hexagonal pattern and wherein the first metal has a Fermi surface that lies within the hexagonal pattern of the Fermi surface of the graphene.
The gated electrical device of Claim 1, wherein the two electrical contacts include a second metal that has a low contact resistance with graphene.
canceled
A gated electrical device, comprising: a. a silicon oxide substrate; b. a graphene ribbon disposed on the substrate, the graphene ribbon including at least one layer of graphene; c. a copper gate layer deposited directly on a portion of the graphene structure; and d. two electrical contacts, each placed on the graphene structure so that the metal gate is disposed between the electrical contacts, the electrical contacts including titanium coated with gold.
A method of making a gated electrical device, comprising the steps of: a. disposing a flat graphene structure onto a non-conductive substrate; Application No. 12/902,360 Amendment dated 04/29/2013 Reply to Office Action dated 01/24/2013 Page 4 of 7 b. depositing a metal gate directly on a portion of the fl at graphene structure, the metal gate including a first metal that has a high contact resistance with graphene wherein the first metal comprises copper; and c. depositing two electrical contacts on the flat graphene structure so that the metal gate is disposed between the two electrical contacts
The method of Claim 12, wherein the substrate comprises a material selected from a group consisting of: silicon oxide and silicon carbide.
The method of Claim 12, wherein the graphene structure comprises a graphene ribbon.
The method of Claim 12, wherein the graphene structure comprises a single layer of graphene.
The method of Claim 12, wherein the graphene structure comprises a plurality of layers of graphene.
The method of Claim 12, wherein the graphene structure has a Fermi surface that includes a hexagonal pattern and further comprising the step of selecting the first metal so that the first metal has a Fermi surface that lies within the hexagonal pattern of the Fermi surface of the graphene.
The method of Claim 12, wherein the electrical contacts include a second metal that has a low contact resistance with graphene.
canceled
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials1 process step
A graphene ribbon 1 µm wide and 10 µm long grown on silicon carbide and patterned by lithography was used. A 10 nm thick copper layer was deposited as the metal gate directly on the graphene ribbon. Electrical contacts were titanium layers coated with gold. The copper gate made poor electrical contact with graphene while the Ti/Au contacts made good electrical contact.
Layer stacks claimed or described, ordered top of device to substrate.
gated electrical device (field-effect transistor)
gated electrical device with silicon oxide substrate and Ti/Au contacts
Materials described outside the worked examples.
low contact resistance metal (electrical contacts)
silicon oxide
SiO₂
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A is a top plan view of one embodiment of a graphene transistor. [0015]
Related documents with shared materials, methods, properties, or citations.
CIRCUIT INCLUDING A NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE HAVING A GRAPHENE CHANNEL, AND METHOD OF OPERATING THE CIRUCIT
METHODS FOR N-TYPE DOPING OF GRAPHENE, AND N-TYPE-DOPED GRAPHENE COMPOSITIONS
Patent
Atlas literature
Patent
US 8,497,499Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A is a top plan view of one embodiment of a graphene transistor. [0015]
FIG. 2 is a graph showing resistance as a function of gate voltage in one experimental embodiment.
FIG. 3, relates resistance measurements of the graphene ribbon embodied in a field effect transistor in the experimental embodiment as a function of a voltage …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gated electrical device, comprising: a. a non-conductive substrate; b. a flat graphene structure disposed on the non-conductive substrate; c. a metal gate deposited directly on a portion of the flat graphene structure, the metal gate including a first metal that has a high contact resistance with graphene wherein the first metal comprises copper; and d. two electrical contacts, each placed on the flat graphene structure so that the metal gate is disposed between the two electrical contacts.
The gated electrical device of Claim 1, wherein the substrate comprises a material selected from a group consisting of: silicon oxide and silicon carbide.
The gated electrical device of Claim 1, wherein the graphene structure comprises a graphene ribbon.
The gated electrical device of Claim 1, wherein the graphene structure comprises a single layer of graphene.
The gated electrical device of Claim 1, wherein the graphene structure comprises a plurality of layers of graphene.
The gated electrical device of Claim 1, wherein the graphene structure has a Fermi surface that includes a hexagonal pattern and wherein the first metal has a Fermi surface that lies within the hexagonal pattern of the Fermi surface of the graphene.
The gated electrical device of Claim 1, wherein the two electrical contacts include a second metal that has a low contact resistance with graphene.
canceled
A gated electrical device, comprising: a. a silicon oxide substrate; b. a graphene ribbon disposed on the substrate, the graphene ribbon including at least one layer of graphene; c. a copper gate layer deposited directly on a portion of the graphene structure; and d. two electrical contacts, each placed on the graphene structure so that the metal gate is disposed between the electrical contacts, the electrical contacts including titanium coated with gold.
A method of making a gated electrical device, comprising the steps of: a. disposing a flat graphene structure onto a non-conductive substrate; Application No. 12/902,360 Amendment dated 04/29/2013 Reply to Office Action dated 01/24/2013 Page 4 of 7 b. depositing a metal gate directly on a portion of the fl at graphene structure, the metal gate including a first metal that has a high contact resistance with graphene wherein the first metal comprises copper; and c. depositing two electrical contacts on the flat graphene structure so that the metal gate is disposed between the two electrical contacts
The method of Claim 12, wherein the substrate comprises a material selected from a group consisting of: silicon oxide and silicon carbide.
The method of Claim 12, wherein the graphene structure comprises a graphene ribbon.
The method of Claim 12, wherein the graphene structure comprises a single layer of graphene.
The method of Claim 12, wherein the graphene structure comprises a plurality of layers of graphene.
The method of Claim 12, wherein the graphene structure has a Fermi surface that includes a hexagonal pattern and further comprising the step of selecting the first metal so that the first metal has a Fermi surface that lies within the hexagonal pattern of the Fermi surface of the graphene.
The method of Claim 12, wherein the electrical contacts include a second metal that has a low contact resistance with graphene.
canceled
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials1 process step
A graphene ribbon 1 µm wide and 10 µm long grown on silicon carbide and patterned by lithography was used. A 10 nm thick copper layer was deposited as the metal gate directly on the graphene ribbon. Electrical contacts were titanium layers coated with gold. The copper gate made poor electrical contact with graphene while the Ti/Au contacts made good electrical contact.
Layer stacks claimed or described, ordered top of device to substrate.
gated electrical device (field-effect transistor)
gated electrical device with silicon oxide substrate and Ti/Au contacts
Materials described outside the worked examples.
low contact resistance metal (electrical contacts)
silicon oxide
SiO₂
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A is a top plan view of one embodiment of a graphene transistor. [0015]
Related documents with shared materials, methods, properties, or citations.
CIRCUIT INCLUDING A NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE HAVING A GRAPHENE CHANNEL, AND METHOD OF OPERATING THE CIRUCIT
METHODS FOR N-TYPE DOPING OF GRAPHENE, AND N-TYPE-DOPED GRAPHENE COMPOSITIONS
Patent
Atlas literature
Patent
US 8,497,499Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A is a top plan view of one embodiment of a graphene transistor. [0015]
FIG. 2 is a graph showing resistance as a function of gate voltage in one experimental embodiment.
FIG. 3, relates resistance measurements of the graphene ribbon embodied in a field effect transistor in the experimental embodiment as a function of a voltage …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gated electrical device, comprising: a. a non-conductive substrate; b. a flat graphene structure disposed on the non-conductive substrate; c. a metal gate deposited directly on a portion of the flat graphene structure, the metal gate including a first metal that has a high contact resistance with graphene wherein the first metal comprises copper; and d. two electrical contacts, each placed on the flat graphene structure so that the metal gate is disposed between the two electrical contacts.
The gated electrical device of Claim 1, wherein the substrate comprises a material selected from a group consisting of: silicon oxide and silicon carbide.
The gated electrical device of Claim 1, wherein the graphene structure comprises a graphene ribbon.
The gated electrical device of Claim 1, wherein the graphene structure comprises a single layer of graphene.
The gated electrical device of Claim 1, wherein the graphene structure comprises a plurality of layers of graphene.
The gated electrical device of Claim 1, wherein the graphene structure has a Fermi surface that includes a hexagonal pattern and wherein the first metal has a Fermi surface that lies within the hexagonal pattern of the Fermi surface of the graphene.
The gated electrical device of Claim 1, wherein the two electrical contacts include a second metal that has a low contact resistance with graphene.
canceled
A gated electrical device, comprising: a. a silicon oxide substrate; b. a graphene ribbon disposed on the substrate, the graphene ribbon including at least one layer of graphene; c. a copper gate layer deposited directly on a portion of the graphene structure; and d. two electrical contacts, each placed on the graphene structure so that the metal gate is disposed between the electrical contacts, the electrical contacts including titanium coated with gold.
A method of making a gated electrical device, comprising the steps of: a. disposing a flat graphene structure onto a non-conductive substrate; Application No. 12/902,360 Amendment dated 04/29/2013 Reply to Office Action dated 01/24/2013 Page 4 of 7 b. depositing a metal gate directly on a portion of the fl at graphene structure, the metal gate including a first metal that has a high contact resistance with graphene wherein the first metal comprises copper; and c. depositing two electrical contacts on the flat graphene structure so that the metal gate is disposed between the two electrical contacts
The method of Claim 12, wherein the substrate comprises a material selected from a group consisting of: silicon oxide and silicon carbide.
The method of Claim 12, wherein the graphene structure comprises a graphene ribbon.
The method of Claim 12, wherein the graphene structure comprises a single layer of graphene.
The method of Claim 12, wherein the graphene structure comprises a plurality of layers of graphene.
The method of Claim 12, wherein the graphene structure has a Fermi surface that includes a hexagonal pattern and further comprising the step of selecting the first metal so that the first metal has a Fermi surface that lies within the hexagonal pattern of the Fermi surface of the graphene.
The method of Claim 12, wherein the electrical contacts include a second metal that has a low contact resistance with graphene.
canceled
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials1 process step
A graphene ribbon 1 µm wide and 10 µm long grown on silicon carbide and patterned by lithography was used. A 10 nm thick copper layer was deposited as the metal gate directly on the graphene ribbon. Electrical contacts were titanium layers coated with gold. The copper gate made poor electrical contact with graphene while the Ti/Au contacts made good electrical contact.
Layer stacks claimed or described, ordered top of device to substrate.
gated electrical device (field-effect transistor)
gated electrical device with silicon oxide substrate and Ti/Au contacts
Materials described outside the worked examples.
low contact resistance metal (electrical contacts)
silicon oxide
SiO₂
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A is a top plan view of one embodiment of a graphene transistor. [0015]
Related documents with shared materials, methods, properties, or citations.
CIRCUIT INCLUDING A NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE HAVING A GRAPHENE CHANNEL, AND METHOD OF OPERATING THE CIRUCIT
METHODS FOR N-TYPE DOPING OF GRAPHENE, AND N-TYPE-DOPED GRAPHENE COMPOSITIONS
Patent
Atlas literature
Patent
US 8,497,499Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A is a top plan view of one embodiment of a graphene transistor. [0015]
FIG. 2 is a graph showing resistance as a function of gate voltage in one experimental embodiment.
FIG. 3, relates resistance measurements of the graphene ribbon embodied in a field effect transistor in the experimental embodiment as a function of a voltage …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gated electrical device, comprising: a. a non-conductive substrate; b. a flat graphene structure disposed on the non-conductive substrate; c. a metal gate deposited directly on a portion of the flat graphene structure, the metal gate including a first metal that has a high contact resistance with graphene wherein the first metal comprises copper; and d. two electrical contacts, each placed on the flat graphene structure so that the metal gate is disposed between the two electrical contacts.
The gated electrical device of Claim 1, wherein the substrate comprises a material selected from a group consisting of: silicon oxide and silicon carbide.
The gated electrical device of Claim 1, wherein the graphene structure comprises a graphene ribbon.
The gated electrical device of Claim 1, wherein the graphene structure comprises a single layer of graphene.
The gated electrical device of Claim 1, wherein the graphene structure comprises a plurality of layers of graphene.
The gated electrical device of Claim 1, wherein the graphene structure has a Fermi surface that includes a hexagonal pattern and wherein the first metal has a Fermi surface that lies within the hexagonal pattern of the Fermi surface of the graphene.
The gated electrical device of Claim 1, wherein the two electrical contacts include a second metal that has a low contact resistance with graphene.
canceled
A gated electrical device, comprising: a. a silicon oxide substrate; b. a graphene ribbon disposed on the substrate, the graphene ribbon including at least one layer of graphene; c. a copper gate layer deposited directly on a portion of the graphene structure; and d. two electrical contacts, each placed on the graphene structure so that the metal gate is disposed between the electrical contacts, the electrical contacts including titanium coated with gold.
A method of making a gated electrical device, comprising the steps of: a. disposing a flat graphene structure onto a non-conductive substrate; Application No. 12/902,360 Amendment dated 04/29/2013 Reply to Office Action dated 01/24/2013 Page 4 of 7 b. depositing a metal gate directly on a portion of the fl at graphene structure, the metal gate including a first metal that has a high contact resistance with graphene wherein the first metal comprises copper; and c. depositing two electrical contacts on the flat graphene structure so that the metal gate is disposed between the two electrical contacts
The method of Claim 12, wherein the substrate comprises a material selected from a group consisting of: silicon oxide and silicon carbide.
The method of Claim 12, wherein the graphene structure comprises a graphene ribbon.
The method of Claim 12, wherein the graphene structure comprises a single layer of graphene.
The method of Claim 12, wherein the graphene structure comprises a plurality of layers of graphene.
The method of Claim 12, wherein the graphene structure has a Fermi surface that includes a hexagonal pattern and further comprising the step of selecting the first metal so that the first metal has a Fermi surface that lies within the hexagonal pattern of the Fermi surface of the graphene.
The method of Claim 12, wherein the electrical contacts include a second metal that has a low contact resistance with graphene.
canceled
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials1 process step
A graphene ribbon 1 µm wide and 10 µm long grown on silicon carbide and patterned by lithography was used. A 10 nm thick copper layer was deposited as the metal gate directly on the graphene ribbon. Electrical contacts were titanium layers coated with gold. The copper gate made poor electrical contact with graphene while the Ti/Au contacts made good electrical contact.
Layer stacks claimed or described, ordered top of device to substrate.
gated electrical device (field-effect transistor)
gated electrical device with silicon oxide substrate and Ti/Au contacts
Materials described outside the worked examples.
low contact resistance metal (electrical contacts)
silicon oxide
SiO₂
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A is a top plan view of one embodiment of a graphene transistor. [0015]
Related documents with shared materials, methods, properties, or citations.
CIRCUIT INCLUDING A NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE HAVING A GRAPHENE CHANNEL, AND METHOD OF OPERATING THE CIRUCIT
METHODS FOR N-TYPE DOPING OF GRAPHENE, AND N-TYPE-DOPED GRAPHENE COMPOSITIONS
aluminum
Al
FIG. 2 is a graph showing resistance as a function of gate voltage in one experimental embodiment.
FIG. 2 is a graph showing resistance as a function of gate voltage in one experimental embodiment.
FIG. 3, relates resistance measurements of the graphene ribbon embodied in a field effect transistor in the experimental embodiment as a function of a voltage …
aluminum
Al
FIG. 2 is a graph showing resistance as a function of gate voltage in one experimental embodiment.
FIG. 2 is a graph showing resistance as a function of gate voltage in one experimental embodiment.
FIG. 3, relates resistance measurements of the graphene ribbon embodied in a field effect transistor in the experimental embodiment as a function of a voltage …
aluminum
Al
FIG. 2 is a graph showing resistance as a function of gate voltage in one experimental embodiment.
FIG. 2 is a graph showing resistance as a function of gate voltage in one experimental embodiment.
FIG. 3, relates resistance measurements of the graphene ribbon embodied in a field effect transistor in the experimental embodiment as a function of a voltage …
aluminum
Al
FIG. 2 is a graph showing resistance as a function of gate voltage in one experimental embodiment.
FIG. 2 is a graph showing resistance as a function of gate voltage in one experimental embodiment.
FIG. 3, relates resistance measurements of the graphene ribbon embodied in a field effect transistor in the experimental embodiment as a function of a voltage …